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11. 发明授权

US08539409B1 Simultaneous development of complementary IC families 有权
标题翻译：互补IC家族同时发展
公开(公告)号：US08539409B1
公开(公告)日：2013-09-17
申请号：US13178599
申请日：2011-07-08
申请人： Shawn Murray , John Schadt , Steven J. Fong , Luan Phoc Chau , Thomas R. Gustafson
发明人： Shawn Murray , John Schadt , Steven J. Fong , Luan Phoc Chau , Thomas R. Gustafson
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： Two (or more) different, but complementary, families of integrated circuits having the same layout are developed simultaneously where the different families are achieved by changing one or more design parameters of transistors used to implement the integrated circuits. For example, a low-power (but low-speed) family of one or more ICs (e.g., for handheld applications) can be achieved by designing at least some transistors with relatively high threshold-voltage (Vt) levels, while a different, but complementary, high-speed (but high-power) family of one or more ICs (e.g., for server applications) can be achieved by designing corresponding transistors with relatively low Vt levels. In this way, the two families can share in common all but a very few masks used to fabricate the ICs of the different families.
摘要翻译：同时开发具有相同布局的两个（或更多）不同但互补的集成电路系列，其中通过改变用于实现集成电路的晶体管的一个或多个设计参数来实现不同系列。例如，可以通过设计至少一些具有相对高的阈值电压（Vt）电平的晶体管来实现一个或多个IC的低功率（但是低速）系列（例如用于手持应用）但是可以通过设计具有相对较低Vt电平的相应晶体管来实现一个或多个IC（例如，用于服务器应用）的互补的高速（但是高功率）系列。这样一来，这两个家庭可以共同分享，只有很少的面具用于制造不同家庭的IC。

12. 发明授权

US07183798B1 Synchronous memory 有权
标题翻译：同步存储器
公开(公告)号：US07183798B1
公开(公告)日：2007-02-27
申请号：US11041319
申请日：2005-01-24
申请人： Xiaojie He , Sajitha Wijesuriya , Claudia Stanley , John Schadt
发明人： Xiaojie He , Sajitha Wijesuriya , Claudia Stanley , John Schadt
IPC分类号： H03K19/173
CPC分类号： H03K19/1776 , H03K19/17728 , H03K19/1774
摘要： Systems and methods are disclosed herein to provide improved memory techniques for logic blocks within a programmable logic device. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a first and a second logic slice adapted to receive a first and a second clock signal. The first and second logic slices may be combined to form wider and deeper memory and single port or synchronous dual port memory.
摘要翻译：本文公开了系统和方法，以为可编程逻辑器件内的逻辑块提供改进的存储器技术。例如，根据本发明的实施例，可编程逻辑器件包括适于接收第一和第二时钟信号的第一和第二逻辑片。可以组合第一和第二逻辑片以形成更宽更深的存储器和单端口或同步双端口存储器。

13. 发明授权

US08912933B1 Serializer with multiple stages 有权
标题翻译：具有多个阶段的串行器
公开(公告)号：US08912933B1
公开(公告)日：2014-12-16
申请号：US13616173
申请日：2012-09-14
申请人： Fulong Zhang , Ling Wang , John Schadt
发明人： Fulong Zhang , Ling Wang , John Schadt
IPC分类号： H03M9/00
CPC分类号： H03M9/00
摘要： In certain embodiments of the invention, a serializer has a transfer stage that transfers N-bit parallel data from a relatively slow timing domain to a relatively fast timing domain and a serializing stage that converts the parallel data into serialized data. Between the transfer stage and the serializing stage is an update stage that buffers the data and can be used to toggle the serializer between an N−1 operating mode and an N+1 operating mode.
摘要翻译：在本发明的某些实施例中，串行器具有将N位并行数据从相对较慢的定时域传送到相对较快的定时域的传送级，以及将并行数据转换成串行数据的串行级。在传送级和序列化级之间是缓存数据并可用于在N-1操作模式和N + 1操作模式之间切换串行器的更新阶段。

14. 发明授权

US07573770B1 Distributed front-end FIFO for source-synchronized interfaces with non-continuous clocks 有权
标题翻译：分布式前端FIFO，用于具有非连续时钟的源同步接口
公开(公告)号：US07573770B1
公开(公告)日：2009-08-11
申请号：US11778457
申请日：2007-07-16
申请人： Fulong Zhang , Harold Scholz , Larry Fenstermaker , John Schadt
发明人： Fulong Zhang , Harold Scholz , Larry Fenstermaker , John Schadt
IPC分类号： G11C7/00
CPC分类号： G06F5/06
摘要： In one embodiment of the invention, an integrated circuit, such as an FPGA, comprises a distributed FIFO architecture that supports data transfer from an external device, such as an SDRAM, via an interface that receives a non-continuous, asynchronous strobe clock and a data lane having a plurality of bit lines from the external device. The distributed FIFO architecture comprise a FIFO for each bit line and a FIFO controller. Under control of the FIFO controller, data is written into each FIFO using a FIFO write clock based on the strobe clock, while data is read out from each FIFO using a FIFO read clock based on a local reference clock of the integrated circuit. The distributed FIFO architecture is designed to handle a range of possible phase differences between the FIFO write and read clocks to safely convert from the asynchronous, non-continuous strobe domain to a local continuous clock domain.
摘要翻译：在本发明的一个实施例中，诸如FPGA的集成电路包括分布式FIFO架构，其支持诸如SDRAM的外部设备的数据传输，所述接口接收非连续异步选通时钟和数据通道具有来自外部设备的多个位线。分布式FIFO架构包括用于每个位线的FIFO和FIFO控制器。在FIFO控制器的控制下，使用基于选通时钟的FIFO写时钟将数据写入每个FIFO，而使用基于集成电路的本地参考时钟的FIFO读时钟从每个FIFO读出数据。分布式FIFO架构旨在处理FIFO写入和读取时钟之间可能的相位差范围，以安全地将异步非连续选通域转换为本地连续时钟域。

15. 发明授权

US07808855B1 Distributed front-end FIFO for source-synchronous interfaces with non-continuous clocks 有权
标题翻译：分布式前端FIFO，用于具有非连续时钟的源同步接口
公开(公告)号：US07808855B1
公开(公告)日：2010-10-05
申请号：US12538810
申请日：2009-08-10
申请人： Fulong Zhang , Harold Scholz , Larry Fenstermaker , John Schadt
发明人： Fulong Zhang , Harold Scholz , Larry Fenstermaker , John Schadt
IPC分类号： G11C7/00
CPC分类号： G06F5/06
摘要： In one embodiment, an integrated circuit such as an FPGA includes one or more data I/O blocks, one or more FIFOs, and a FIFO controller. At least one data I/O block receives an incoming bit stream from an external device. At least one FIFO is connected to receive a corresponding incoming bit stream from a corresponding data I/O block. The FIFO controller controls operations of the one or more FIFOs, such that (i) bits from the corresponding data I/O block are written into the at least one FIFO using a FIFO write clock that is based on an incoming clock signal and (ii) bits are read out from the at least one FIFO using a FIFO read clock that is based on a local reference clock signal.
摘要翻译：在一个实施例中，诸如FPGA的集成电路包括一个或多个数据I / O块，一个或多个FIFO和FIFO控制器。至少一个数据I / O块从外部设备接收输入位流。连接至少一个FIFO以从相应的数据I / O块接收相应的输入位流。 FIFO控制器控制一个或多个FIFO的操作，使得（i）来自对应数据I / O块的位被使用基于输入时钟信号的FIFO写入时钟写入到至少一个FIFO中，并且（ii ）位使用基于本地参考时钟信号的FIFO读时钟从至少一个FIFO读出。

16. 发明授权

US06940779B2 Programmable broadcast initialization of memory blocks 有权
公开(公告)号：US06940779B2
公开(公告)日：2005-09-06
申请号：US10641260
申请日：2003-08-13
申请人： Zheng (Jeff) Chen , John Schadt , Barry Britton
发明人： Zheng (Jeff) Chen , John Schadt , Barry Britton
IPC分类号： H03K19/177 , G11C7/00
CPC分类号： H03K19/17772 , H03K19/17756 , H03K19/1776 , H03K19/17764
摘要： Systems and methods are disclosed herein to initialize memory blocks of a programmable logic device. For example in accordance with an embodiment of the present invention, a system bus extension is provided for the memory blocks that functions as a unidirectional broadcasting write bus. A read bus may also be provided to read data stored in the memory blocks.

17. 发明申请

US20050035781A1 Programmable broadcast initialization of memory blocks 有权
标题翻译：内存块的可编程广播初始化
公开(公告)号：US20050035781A1
公开(公告)日：2005-02-17
申请号：US10641260
申请日：2003-08-13
申请人： Zheng Chen , John Schadt , Barry Britton
发明人： Zheng Chen , John Schadt , Barry Britton
IPC分类号： H03K19/177 , H03K19/173
CPC分类号： H03K19/17772 , H03K19/17756 , H03K19/1776 , H03K19/17764
摘要： Systems and methods are disclosed herein to initialize memory blocks of a programmable logic device. For example in accordance with an embodiment of the present invention, a system bus extension is provided for the memory blocks that functions as a unidirectional broadcasting write bus. A read bus may also be provided to read data stored in the memory blocks.
摘要翻译：这里公开了系统和方法来初始化可编程逻辑器件的存储器块。例如，根据本发明的实施例，为用作单向广播写总线的存储器块提供系统总线扩展。还可以提供读总线来读取存储在存储块中的数据。

18. 发明授权

US08461894B1 Low-power configurable delay element 有权
标题翻译：低功耗可配置延迟元件
公开(公告)号：US08461894B1
公开(公告)日：2013-06-11
申请号：US13585142
申请日：2012-08-14
申请人： Fulong Zhang , Zheng Chen , Chien Kuang Chen , John Schadt
发明人： Fulong Zhang , Zheng Chen , Chien Kuang Chen , John Schadt
IPC分类号： H03H11/26
CPC分类号： H03K5/131
摘要： In one embodiment, a configurable delay element has three stages. The first stage has an 8-buffer first delay chain and an (8×1) first mux that selects one of the eight first-delay-chain outputs. The second stage has a 24-buffer second delay chain connected to receive the first-mux output and organized into three 8-buffer sub-chains and a (4×1) second mux that selects one of the four second-delay-chain outputs. The third stage has a 96-buffer third delay chain connected to receive the second-mux output and organized into three 32-buffer sub-chains and a (4×1) third mux that selects one of the four third-delay-chain outputs as the delay-element output signal. A delay-element controller provides glitch-less updates to the signal used to control the delay-element muxes by timing those updates to occur when all delay-element buffers have the same state. The controller bases the update timing on the delay-element output signal.
摘要翻译：在一个实施例中，可配置延迟元件具有三个阶段。第一级具有8缓冲器第一延迟链和（8×1）第一多路复用器，其选择八个第一延迟链输出之一。第二级具有连接的24缓冲器第二延迟链，用于接收第一多路复用器输出并被组织成三个8缓冲子链和选择四个第二延迟链输出之一的（4×1）第二复用器。第三级具有96缓冲器第三延迟链，用于接收第二多路复用器输出，并组织成三个32缓冲子链和（4×1）第三复用器，选择四个第三延迟链输出中的一个作为延迟元件输出信号。延迟元件控制器通过定时在所有延迟元件缓冲器具有相同状态时进行定时的这些更新来为用于控制延迟元件多路复用器的信号提供无故障更新。控制器基于延迟元件输出信号的更新时序。

19. 发明授权

US08324934B1 Programmable buffer 有权
标题翻译：可编程缓冲器
公开(公告)号：US08324934B1
公开(公告)日：2012-12-04
申请号：US13007688
申请日：2011-01-17
申请人： Keith Truong , John Schadt , Ravi Lall , William Andrews
发明人： Keith Truong , John Schadt , Ravi Lall , William Andrews
IPC分类号： H03K19/094
CPC分类号： H03K19/0941 , H03K3/0377
摘要： In one embodiment of the invention, a programmable device, such as an FPGA, has a programmable input buffer with a VCCIO-powered buffer stage for high-voltage signaling and a VCC-powered buffer stage for low-voltage signaling. In addition to a main driver section, the VCCIO-powered buffer stage has a mixed-mode section for handling multiple different over-drive and multiple different under-drive conditions, a hysteresis section for providing multiple different trip-point hysteresis modes of operation, and a level-shifting section with look-ahead circuitry that enables the main driver section to be implemented with low-power, high-threshold devices, while still enabling the VCCIO-powered buffer stage to operate with low skew and high speed.
摘要翻译：在本发明的一个实施例中，诸如FPGA的可编程器件具有可编程输入缓冲器，其具有用于高电压信号的VCCIO供电缓冲级和用于低电压信号的VCC供电缓冲级。除主驱动器部分外，VCCIO供电的缓冲级具有混合模式部分，用于处理多个不同的过驱动和多个不同的驱动下条件，滞后部分用于提供多种不同的跳变点滞后操作模式，以及具有先行电路的电平转换部分，其使得主驱动器部分能够用低功率，高阈值器件实现，同时仍然使得VCCIO供电的缓冲器级以低歪斜和高速度运行。

20. 发明授权

US08248136B1 Low-power, glitch-less, configurable delay element 有权
标题翻译：低功耗，无毛刺，可配置延迟元件
公开(公告)号：US08248136B1
公开(公告)日：2012-08-21
申请号：US13007804
申请日：2011-01-17
申请人： Fulong Zhang , Zheng Chen , Chien Kuang Chen , John Schadt
发明人： Fulong Zhang , Zheng Chen , Chien Kuang Chen , John Schadt
IPC分类号： H03H11/26
CPC分类号： H03K5/131
摘要： In one embodiment, a configurable delay element has three stages. The first stage has an 8-buffer first delay chain and an (8×1) first mux that selects one of the eight first-delay-chain outputs. The second stage has a 24-buffer second delay chain connected to receive the first-mux output and organized into three 8-buffer sub-chains and a (4×1) second mux that selects one of the four second-delay-chain outputs. The third stage has a 96-buffer third delay chain connected to receive the second-mux output and organized into three 32-buffer sub-chains and a (4×1) third mux that selects one of the four third-delay-chain outputs as the delay-element output signal. A delay-element controller provides glitch-less updates to the signal used to control the delay-element muxes by timing those updates to occur when all delay-element buffers have the same state. The controller bases the update timing on the delay-element output signal.
摘要翻译：在一个实施例中，可配置延迟元件具有三个阶段。第一级具有8缓冲器第一延迟链和（8×1）第一多路复用器，其选择八个第一延迟链输出之一。第二级具有连接的24缓冲器第二延迟链，用于接收第一多路复用器输出并被组织成三个8缓冲子链和选择四个第二延迟链输出之一的（4×1）第二复用器。第三级具有96缓冲器第三延迟链，用于接收第二多路复用器输出，并组织成三个32缓冲子链和（4×1）第三复用器，选择四个第三延迟链输出中的一个作为延迟元件输出信号。延迟元件控制器通过定时在所有延迟元件缓冲器具有相同状态时进行定时的这些更新来为用于控制延迟元件多路复用器的信号提供无故障更新。控制器基于延迟元件输出信号的更新时序。

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