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1. 发明授权

US08912933B1 Serializer with multiple stages 有权
标题翻译：具有多个阶段的串行器
公开(公告)号：US08912933B1
公开(公告)日：2014-12-16
申请号：US13616173
申请日：2012-09-14
申请人： Fulong Zhang , Ling Wang , John Schadt
发明人： Fulong Zhang , Ling Wang , John Schadt
IPC分类号： H03M9/00
CPC分类号： H03M9/00
摘要： In certain embodiments of the invention, a serializer has a transfer stage that transfers N-bit parallel data from a relatively slow timing domain to a relatively fast timing domain and a serializing stage that converts the parallel data into serialized data. Between the transfer stage and the serializing stage is an update stage that buffers the data and can be used to toggle the serializer between an N−1 operating mode and an N+1 operating mode.
摘要翻译：在本发明的某些实施例中，串行器具有将N位并行数据从相对较慢的定时域传送到相对较快的定时域的传送级，以及将并行数据转换成串行数据的串行级。在传送级和序列化级之间是缓存数据并可用于在N-1操作模式和N + 1操作模式之间切换串行器的更新阶段。

2. 发明授权

US08274412B1 Serializer with odd gearing ratio 有权
标题翻译：具有奇数传动比的串行器
公开(公告)号：US08274412B1
公开(公告)日：2012-09-25
申请号：US12987393
申请日：2011-01-10
申请人： Fulong Zhang , Ling Wang , John Schadt
发明人： Fulong Zhang , Ling Wang , John Schadt
IPC分类号： H03M9/00
CPC分类号： H03M9/00
摘要： In certain embodiments of the invention, a serializer has (a) an initial, transfer stage that transfers incoming parallel data from a relatively slow timing domain to a relatively fast timing domain and (b) a final, serializing stage that converts the parallel data into serialized data. Between the transfer stage and the serializing stage is an update stage that (i) buffers data between the initial and final stages and (ii) can be used to toggle the serializer between an N−1 operating mode (that serializes (N−1) bits of parallel data) and an N+1 operating mode (that serializes (N+1) bits of parallel data) to achieve a net N:1 gearing ratio where N is an odd integer. The serializer can be configurable to support other gearing ratios as well.
摘要翻译：在本发明的某些实施例中，串行器具有（a）初始传送级，其将输入的并行数据从相对较慢的定时域传送到相对较快的定时域，以及（b）将并行数据转换成序列化数据。在转移阶段和序列化阶段之间是更新阶段，（i）缓冲初始阶段和最后阶段之间的数据，（ii）可用于在N-1操作模式（序列化（N-1）并行数据的位）和N + 1工作模式（串行化并行数据的（N + 1）位），以实现净N：1的传动比，其中N是奇整数。串行器可以配置为支持其他传动比。

3. 发明授权

US07808855B1 Distributed front-end FIFO for source-synchronous interfaces with non-continuous clocks 有权
标题翻译：分布式前端FIFO，用于具有非连续时钟的源同步接口
公开(公告)号：US07808855B1
公开(公告)日：2010-10-05
申请号：US12538810
申请日：2009-08-10
申请人： Fulong Zhang , Harold Scholz , Larry Fenstermaker , John Schadt
发明人： Fulong Zhang , Harold Scholz , Larry Fenstermaker , John Schadt
IPC分类号： G11C7/00
CPC分类号： G06F5/06
摘要： In one embodiment, an integrated circuit such as an FPGA includes one or more data I/O blocks, one or more FIFOs, and a FIFO controller. At least one data I/O block receives an incoming bit stream from an external device. At least one FIFO is connected to receive a corresponding incoming bit stream from a corresponding data I/O block. The FIFO controller controls operations of the one or more FIFOs, such that (i) bits from the corresponding data I/O block are written into the at least one FIFO using a FIFO write clock that is based on an incoming clock signal and (ii) bits are read out from the at least one FIFO using a FIFO read clock that is based on a local reference clock signal.
摘要翻译：在一个实施例中，诸如FPGA的集成电路包括一个或多个数据I / O块，一个或多个FIFO和FIFO控制器。至少一个数据I / O块从外部设备接收输入位流。连接至少一个FIFO以从相应的数据I / O块接收相应的输入位流。 FIFO控制器控制一个或多个FIFO的操作，使得（i）来自对应数据I / O块的位被使用基于输入时钟信号的FIFO写入时钟写入到至少一个FIFO中，并且（ii ）位使用基于本地参考时钟信号的FIFO读时钟从至少一个FIFO读出。

4. 发明授权

US07573770B1 Distributed front-end FIFO for source-synchronized interfaces with non-continuous clocks 有权
标题翻译：分布式前端FIFO，用于具有非连续时钟的源同步接口
公开(公告)号：US07573770B1
公开(公告)日：2009-08-11
申请号：US11778457
申请日：2007-07-16
申请人： Fulong Zhang , Harold Scholz , Larry Fenstermaker , John Schadt
发明人： Fulong Zhang , Harold Scholz , Larry Fenstermaker , John Schadt
IPC分类号： G11C7/00
CPC分类号： G06F5/06
摘要： In one embodiment of the invention, an integrated circuit, such as an FPGA, comprises a distributed FIFO architecture that supports data transfer from an external device, such as an SDRAM, via an interface that receives a non-continuous, asynchronous strobe clock and a data lane having a plurality of bit lines from the external device. The distributed FIFO architecture comprise a FIFO for each bit line and a FIFO controller. Under control of the FIFO controller, data is written into each FIFO using a FIFO write clock based on the strobe clock, while data is read out from each FIFO using a FIFO read clock based on a local reference clock of the integrated circuit. The distributed FIFO architecture is designed to handle a range of possible phase differences between the FIFO write and read clocks to safely convert from the asynchronous, non-continuous strobe domain to a local continuous clock domain.
摘要翻译：在本发明的一个实施例中，诸如FPGA的集成电路包括分布式FIFO架构，其支持诸如SDRAM的外部设备的数据传输，所述接口接收非连续异步选通时钟和数据通道具有来自外部设备的多个位线。分布式FIFO架构包括用于每个位线的FIFO和FIFO控制器。在FIFO控制器的控制下，使用基于选通时钟的FIFO写时钟将数据写入每个FIFO，而使用基于集成电路的本地参考时钟的FIFO读时钟从每个FIFO读出数据。分布式FIFO架构旨在处理FIFO写入和读取时钟之间可能的相位差范围，以安全地将异步非连续选通域转换为本地连续时钟域。

5. 发明授权

US08461894B1 Low-power configurable delay element 有权
标题翻译：低功耗可配置延迟元件
公开(公告)号：US08461894B1
公开(公告)日：2013-06-11
申请号：US13585142
申请日：2012-08-14
申请人： Fulong Zhang , Zheng Chen , Chien Kuang Chen , John Schadt
发明人： Fulong Zhang , Zheng Chen , Chien Kuang Chen , John Schadt
IPC分类号： H03H11/26
CPC分类号： H03K5/131
摘要： In one embodiment, a configurable delay element has three stages. The first stage has an 8-buffer first delay chain and an (8×1) first mux that selects one of the eight first-delay-chain outputs. The second stage has a 24-buffer second delay chain connected to receive the first-mux output and organized into three 8-buffer sub-chains and a (4×1) second mux that selects one of the four second-delay-chain outputs. The third stage has a 96-buffer third delay chain connected to receive the second-mux output and organized into three 32-buffer sub-chains and a (4×1) third mux that selects one of the four third-delay-chain outputs as the delay-element output signal. A delay-element controller provides glitch-less updates to the signal used to control the delay-element muxes by timing those updates to occur when all delay-element buffers have the same state. The controller bases the update timing on the delay-element output signal.
摘要翻译：在一个实施例中，可配置延迟元件具有三个阶段。第一级具有8缓冲器第一延迟链和（8×1）第一多路复用器，其选择八个第一延迟链输出之一。第二级具有连接的24缓冲器第二延迟链，用于接收第一多路复用器输出并被组织成三个8缓冲子链和选择四个第二延迟链输出之一的（4×1）第二复用器。第三级具有96缓冲器第三延迟链，用于接收第二多路复用器输出，并组织成三个32缓冲子链和（4×1）第三复用器，选择四个第三延迟链输出中的一个作为延迟元件输出信号。延迟元件控制器通过定时在所有延迟元件缓冲器具有相同状态时进行定时的这些更新来为用于控制延迟元件多路复用器的信号提供无故障更新。控制器基于延迟元件输出信号的更新时序。

6. 发明授权

US08248136B1 Low-power, glitch-less, configurable delay element 有权
标题翻译：低功耗，无毛刺，可配置延迟元件
公开(公告)号：US08248136B1
公开(公告)日：2012-08-21
申请号：US13007804
申请日：2011-01-17
申请人： Fulong Zhang , Zheng Chen , Chien Kuang Chen , John Schadt
发明人： Fulong Zhang , Zheng Chen , Chien Kuang Chen , John Schadt
IPC分类号： H03H11/26
CPC分类号： H03K5/131
摘要： In one embodiment, a configurable delay element has three stages. The first stage has an 8-buffer first delay chain and an (8×1) first mux that selects one of the eight first-delay-chain outputs. The second stage has a 24-buffer second delay chain connected to receive the first-mux output and organized into three 8-buffer sub-chains and a (4×1) second mux that selects one of the four second-delay-chain outputs. The third stage has a 96-buffer third delay chain connected to receive the second-mux output and organized into three 32-buffer sub-chains and a (4×1) third mux that selects one of the four third-delay-chain outputs as the delay-element output signal. A delay-element controller provides glitch-less updates to the signal used to control the delay-element muxes by timing those updates to occur when all delay-element buffers have the same state. The controller bases the update timing on the delay-element output signal.
摘要翻译：在一个实施例中，可配置延迟元件具有三个阶段。第一级具有8缓冲器第一延迟链和（8×1）第一多路复用器，其选择八个第一延迟链输出之一。第二级具有连接的24缓冲器第二延迟链，用于接收第一多路复用器输出并被组织成三个8缓冲子链和选择四个第二延迟链输出之一的（4×1）第二复用器。第三级具有96缓冲器第三延迟链，用于接收第二多路复用器输出，并组织成三个32缓冲子链和（4×1）第三复用器，选择四个第三延迟链输出中的一个作为延迟元件输出信号。延迟元件控制器通过定时在所有延迟元件缓冲器具有相同状态时进行定时的这些更新来为用于控制延迟元件多路复用器的信号提供无故障更新。控制器基于延迟元件输出信号的更新时序。

7. 发明授权

US07009433B2 Digitally controlled delay cells 有权
标题翻译：数字控制延时单元
公开(公告)号：US07009433B2
公开(公告)日：2006-03-07
申请号：US10447451
申请日：2003-05-28
申请人： Fulong Zhang , William B. Andrews , Phillip Johnson , Hal Scholz , Zheng (Jeff) Chen , John Schadt
发明人： Fulong Zhang , William B. Andrews , Phillip Johnson , Hal Scholz , Zheng (Jeff) Chen , John Schadt
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03K5/133 , H03K2005/00058 , H03L7/0805
摘要： Systems and methods are disclosed herein to implement signal delay in integrated circuits. For example, in accordance with an embodiment of the present invention, a master delay circuit may digitally control one or more slave delay cells to support various applications of a programmable logic device.
摘要翻译：本文公开了在集成电路中实现信号延迟的系统和方法。例如，根据本发明的实施例，主延迟电路可以数字地控制一个或多个从延迟单元以支持可编程逻辑器件的各种应用。

8. 发明授权

US07109754B1 Synchronization of programmable multiplexers and demultiplexers 有权
公开(公告)号：US07109754B1
公开(公告)日：2006-09-19
申请号：US11044089
申请日：2005-01-27
申请人： Fulong Zhang
发明人： Fulong Zhang
IPC分类号： H03K19/173
CPC分类号： H03K19/1774 , H03K5/135 , H03K5/1506 , H03K19/1737 , H03K19/17744
摘要： Systems and methods are disclosed to provide clock and data synchronization for input/output interfaces of a programmable logic device. In accordance with one embodiment, a phase-locked loop or a delay-locked loop is employed to synchronize signals for input/output circuitry. In accordance with another embodiment, a clock divider along with an edge clock distribution scheme is employed to distribute clock and reset signals for input/output circuitry.

9. 发明授权

US07009423B1 Programmable I/O interfaces for FPGAs and other PLDs 有权
标题翻译：用于FPGA和其他PLD的可编程I / O接口
公开(公告)号：US07009423B1
公开(公告)日：2006-03-07
申请号：US11134152
申请日：2005-05-20
申请人： William B. Andrews , Fulong Zhang , Harold Scholz
发明人： William B. Andrews , Fulong Zhang , Harold Scholz
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1087 , H03K19/17744
摘要： A programmable logic device (PLD), such as a field programmable gate array (FPGA) has a logic core surrounded on one or more sides by an input/output (I/O) interface having one or more programmable I/O buffers (PIBs). At least one PIB can be programmed to perform two or more of (a) a pass-through data input mode, (b) an input register mode; (c) a double data rate (DDR) input mode, (d) one or more demux input modes, (e) one or more DDR demux input modes. In addition or alternatively, at least one PIB can be programmed to perform two or more of (a) a pass-through data output mode, (b) an output register mode, (c) a DDR output mode, (d) one or more mux output modes, and (e) one or more DDR mux output modes. As such, devices of the present invention are flexible enough to support both low-rate and high-rate interface applications, while efficiently using device resources.
摘要翻译：诸如现场可编程门阵列（FPGA）的可编程逻辑器件（PLD）具有通过具有一个或多个可编程I / O缓冲器（PIB）的输入/输出（I / O）接口在一侧或多侧上包围的逻辑核）。至少一个PIB可以被编程为执行（a）直通数据输入模式，（b）输入寄存器模式中的两个或更多个; （c）双数据速率（DDR）输入模式，（d）一个或多个解复用器输入模式，（e）一个或多个DDR解复用器输入模式。另外或替代地，至少一个PIB可被编程为执行（a）直通数据输出模式，（b）输出寄存器模式，（c）DDR输出模式，（d）一个或多个更多多路输出模式，（e）一个或多个DDR多路复用器输出模式。因此，本发明的设备足够灵活，以支持低速率和高速率的接口应用，同时有效地利用设备资源。

10. 发明授权

US06856171B1 Synchronization of programmable multiplexers and demultiplexers 有权
标题翻译：可编程多路复用器和解复用器的同步
公开(公告)号：US06856171B1
公开(公告)日：2005-02-15
申请号：US10460385
申请日：2003-06-11
申请人： Fulong Zhang
发明人： Fulong Zhang
IPC分类号： H03K5/135 , H03K5/15 , H03K19/173 , H03K19/177 , H03K19/00
CPC分类号： H03K19/1774 , H03K5/135 , H03K5/1506 , H03K19/1737 , H03K19/17744
摘要： Systems and methods are disclosed to provide clock and data synchronization for input/output interfaces of a programmable logic device. In accordance with one embodiment, a phase-locked loop or a delay-locked loop is employed to synchronize signals for input/output circuitry. In accordance with another embodiment, a clock divider along with an edge clock distribution scheme is employed to distribute clock and reset signals for input/output circuitry.
摘要翻译：公开了系统和方法来为可编程逻辑器件的输入/输出接口提供时钟和数据同步。根据一个实施例，采用锁相环或延迟锁定环来对用于输入/输出电路的信号进行同步。根据另一个实施例，采用时钟分频器以及边沿时钟分配方案来分配用于输入/输出电路的时钟和复位信号。

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