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1. 发明授权

US06940779B2 Programmable broadcast initialization of memory blocks 有权
公开(公告)号：US06940779B2
公开(公告)日：2005-09-06
申请号：US10641260
申请日：2003-08-13
申请人： Zheng (Jeff) Chen , John Schadt , Barry Britton
发明人： Zheng (Jeff) Chen , John Schadt , Barry Britton
IPC分类号： H03K19/177 , G11C7/00
CPC分类号： H03K19/17772 , H03K19/17756 , H03K19/1776 , H03K19/17764
摘要： Systems and methods are disclosed herein to initialize memory blocks of a programmable logic device. For example in accordance with an embodiment of the present invention, a system bus extension is provided for the memory blocks that functions as a unidirectional broadcasting write bus. A read bus may also be provided to read data stored in the memory blocks.

2. 发明授权

US07554357B2 Efficient configuration of daisy-chained programmable logic devices 有权
标题翻译：菊花链可编程逻辑器件的高效配置
公开(公告)号：US07554357B2
公开(公告)日：2009-06-30
申请号：US11346817
申请日：2006-02-03
申请人： Zheng (Jeff) Chen , Barry Britton , Harold Scholz
发明人： Zheng (Jeff) Chen , Barry Britton , Harold Scholz
IPC分类号： H03K19/173
CPC分类号： G06F17/5054
摘要： In one embodiment, a programmable logic device includes: a multiplexer adapted to select a compressed configuration bitstream from a plurality of external serial interface memories; a serial interface processor adapted to command the bitstream selection by the multiplexer; and a bitstream decompressor adapted to decompress the selected configuration bitstream into a decompressed configuration bitstream.
摘要翻译：在一个实施例中，可编程逻辑器件包括：多路复用器，适于从多个外部串行接口存储器中选择压缩配置比特流; 串行接口处理器，适于通过多路复用器命令比特流选择; 以及适于将所选配置比特流解压缩为解压配置比特流的比特流解压缩器。

3. 发明申请

US20050035781A1 Programmable broadcast initialization of memory blocks 有权
标题翻译：内存块的可编程广播初始化
公开(公告)号：US20050035781A1
公开(公告)日：2005-02-17
申请号：US10641260
申请日：2003-08-13
申请人： Zheng Chen , John Schadt , Barry Britton
发明人： Zheng Chen , John Schadt , Barry Britton
IPC分类号： H03K19/177 , H03K19/173
CPC分类号： H03K19/17772 , H03K19/17756 , H03K19/1776 , H03K19/17764
摘要： Systems and methods are disclosed herein to initialize memory blocks of a programmable logic device. For example in accordance with an embodiment of the present invention, a system bus extension is provided for the memory blocks that functions as a unidirectional broadcasting write bus. A read bus may also be provided to read data stored in the memory blocks.
摘要翻译：这里公开了系统和方法来初始化可编程逻辑器件的存储器块。例如，根据本发明的实施例，为用作单向广播写总线的存储器块提供系统总线扩展。还可以提供读总线来读取存储在存储块中的数据。

4. 发明授权

US07605606B1 Area efficient routing architectures for programmable logic devices 有权
标题翻译：用于可编程逻辑器件的区域高效路由架构
公开(公告)号：US07605606B1
公开(公告)日：2009-10-20
申请号：US11498646
申请日：2006-08-03
申请人： Ming H. Ding , Sajitha Wijesuriya , Jun Zhao , Om P. Agrawal , Barry Britton , Xiaojie He
发明人： Ming H. Ding , Sajitha Wijesuriya , Jun Zhao , Om P. Agrawal , Barry Britton , Xiaojie He
IPC分类号： H03K19/177
CPC分类号： H03K19/17736
摘要： Systems and methods provide programmable logic block architectures and routing architectures for the programmable logic blocks. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of programmable logic blocks and a plurality of logic block slices within each of the programmable logic blocks. A first routing circuit provides global signal routing within the programmable logic device for the corresponding programmable logic block. A first input routing circuit receives signals from the first routing circuit and routes the signals to the logic block slices within the corresponding programmable logic block.
摘要翻译：系统和方法为可编程逻辑块提供可编程逻辑块架构和路由架构。例如，根据本发明的实施例，可编程逻辑器件包括多个可编程逻辑块和每个可编程逻辑块内的多个逻辑块片。第一路由电路在可编程逻辑器件内为相应的可编程逻辑块提供全局信号路由。第一输入路由电路从第一路由电路接收信号并将信号路由到相应的可编程逻辑块内的逻辑块片段。

5. 发明授权

US07532646B2 Distributed multiple-channel alignment scheme 有权
标题翻译：分布式多通道校准方案
公开(公告)号：US07532646B2
公开(公告)日：2009-05-12
申请号：US11064477
申请日：2005-02-23
申请人： Wai-Bor Leung , Barry Britton , Akila Subramaniam
发明人： Wai-Bor Leung , Barry Britton , Akila Subramaniam
IPC分类号： H04J3/06 , H04J3/02
CPC分类号： H04L25/14
摘要： A channel-alignment circuit has a controller and a plurality of channel-alignment blocks. Each channel-alignment block synchronizes two or more channels. The controller coordinates the synchronization of channels by the blocks such that (i) channels in each of one or more groups of two or more blocks are synchronized, and (ii) each group of blocks is synchronized independently of any other group.
摘要翻译：通道对准电路具有控制器和多个通道对准块。每个通道对齐块同步两个或更多个通道。控制器通过块协调通道的同步，使得（i）两个或更多个块的一个或多个组中的每一个中的信道被同步，并且（ii）每组块独立于任何其他组同步。

6. 发明授权

US08319521B1 Safe programming of key information into non-volatile memory for a programmable logic device 有权
标题翻译：将密钥信息安全地编程到可编程逻辑器件的非易失性存储器中
公开(公告)号：US08319521B1
公开(公告)日：2012-11-27
申请号：US13076300
申请日：2011-03-30
申请人： Wei Han , Barry Britton , Eric Lee , Zheng Chen , Warren Juenemann , Mose Wahlstrom
发明人： Wei Han , Barry Britton , Eric Lee , Zheng Chen , Warren Juenemann , Mose Wahlstrom
IPC分类号： H03K19/177 , H01L25/00
CPC分类号： H03K19/17764 , H03K19/17768
摘要： A programmable logic device (PLD) is disclosed that includes a non-volatile memory; a shadow register; and a data shift register (DSR) configurable to receive control information from an external programming tool, wherein the DSR is configured to shift the control information into the shadow register if the PLD is in a first programming mode, the PLD being configurable to operate in the first programming mode using the control information stored in the shadow register without the control information being stored in the non-volatile memory.
摘要翻译：公开了一种包括非易失性存储器的可编程逻辑器件（PLD）; 影子寄存器以及数据移位寄存器（DSR），其被配置为从外部编程工具接收控制信息，其中所述DSR被配置为如果所述PLD处于第一编程模式，则将所述控制信息移位到所述影子寄存器中，所述PLD可配置为在使用存储在影子寄存器中的控制信息的第一编程模式，而不将控制信息存储在非易失性存储器中。

7. 发明授权

US07599457B2 Clock-and-data-recovery system having a multi-phase clock generator for one or more channel circuits 有权
标题翻译：具有用于一个或多个信道电路的多相时钟发生器的时钟和数据恢复系统
公开(公告)号：US07599457B2
公开(公告)日：2009-10-06
申请号：US11199287
申请日：2005-08-08
申请人： Phillip Johnson , Zheng Chen , Barry Britton
发明人： Phillip Johnson , Zheng Chen , Barry Britton
IPC分类号： H04L7/02
CPC分类号： H04L7/0338 , H03L7/0812
摘要： In one embodiment of the invention, a clock-and-data-recovery (CDR) system has a multi-phase clock generator that generates a plurality of phase-offset clock signals and one or more channel circuits, each receiving a (different) input data signal and all of the phase-offset clock signals and generates an output data stream and a recovered clock signal. Each channel circuit has a plurality of data registers (e.g., flip-flops), each receiving the input data signal at its clock input port and a different one of the phase-offset clock signals at its data input port, such that the flip-flop is triggered at each (rising) edge in the input data signal. The channel circuit processes the outputs from the different flip-flops to select an appropriate phase-offset clock signal for use in sampling the input data signal to generate the output data stream, where the recovered clock signal is generated from the selected phase-offset clock signal.
摘要翻译：在本发明的一个实施例中，时钟和数据恢复（CDR）系统具有产生多个相位偏移时钟信号的多相时钟发生器和一个或多个信道电路，每个信道电路接收（不同的）输入数据信号和所有相位偏移时钟信号，并产生输出数据流和恢复的时钟信号。每个通道电路具有多个数据寄存器（例如，触发器），每个数据寄存器在其时钟输入端口接收输入数据信号，并在其数据输入端口接收不同的相位偏移时钟信号，触发器在输入数据信号的每个（上升沿）触发。通道电路处理来自不同触发器的输出以选择合适的相位偏移时钟信号，以用于对输入数据信号进行采样以产生输出数据流，其中从所选择的相位偏移时钟产生恢复的时钟信号信号。

8. 发明申请

US20060187966A1 Distributed multiple-channel alignment scheme 有权
公开(公告)号：US20060187966A1
公开(公告)日：2006-08-24
申请号：US11064477
申请日：2005-02-23
申请人： Wai-Bor Leung , Barry Britton , Akila Subramaniam
发明人： Wai-Bor Leung , Barry Britton , Akila Subramaniam
IPC分类号： H04J3/06
CPC分类号： H04L25/14
摘要： A channel-alignment circuit has a controller and a plurality of channel-alignment blocks. Each channel-alignment block synchronizes two or more channels. The controller coordinates the synchronization of channels by the blocks such that (i) channels in each of one or more groups of two or more blocks are synchronized, and (ii) each group of blocks is synchronized independently of any other group.

9. 发明授权

US08531222B1 Phase locked loop circuit with selectable feedback paths 有权
标题翻译：具有可选反馈路径的锁相环电路
公开(公告)号：US08531222B1
公开(公告)日：2013-09-10
申请号：US13079595
申请日：2011-04-04
申请人： Barry Britton , Richard Booth , Phillip L. Johnson , Yang Xu , Tawei David Li
发明人： Barry Britton , Richard Booth , Phillip L. Johnson , Yang Xu , Tawei David Li
IPC分类号： H03L7/06
CPC分类号： H03L7/0802 , H03L7/095 , H03L7/14 , H03L7/18 , H03L2207/08
摘要： A phase locked loop (PLL) circuit is provided with selectable feedback paths. In one example, a method of operating a device includes passing a clock signal provided by a PLL circuit of the device through an internal feedback path of the PLL circuit to provide a first input signal to the PLL circuit while at least one external circuit of an external feedback path of the device is disabled during a low power operation mode of the device. The method also includes detecting a lock between the first input signal and a reference signal during the low power operation mode. The lock indicates that the clock signal is operating at a frequency used during a normal operation mode of the device. The method also includes passing the clock signal through the external feedback path to provide a second input signal to the PLL circuit. The method also includes switching from detecting a lock between the first input signal and the reference signal to detecting a lock between the second input signal and the reference signal if the external circuit is enabled for the normal operation mode.
摘要翻译：锁相环（PLL）电路具有可选择的反馈路径。在一个示例中，操作设备的方法包括通过PLL电路的内部反馈路径传递由该器件的PLL电路提供的时钟信号，以向PLL电路提供第一输入信号，同时至少一个外部电路在器件的低功耗操作模式下，器件的外部反馈通路被禁止。该方法还包括在低功率操作模式期间检测第一输入信号和参考信号之间的锁定。锁定指示时钟信号以在设备的正常操作模式期间使用的频率操作。该方法还包括使时钟信号通过外部反馈路径以向PLL电路提供第二输入信号。该方法还包括如果外部电路用于正常操作模式，则从检测第一输入信号和参考信号之间的锁定切换到检测第二输入信号和参考信号之间的锁定。

10. 发明授权

US07378872B1 Programmable logic device architecture with multiple slice types 有权
标题翻译：具有多种切片类型的可编程逻辑器件架构
公开(公告)号：US07378872B1
公开(公告)日：2008-05-27
申请号：US11445620
申请日：2006-06-02
申请人： Om P. Agrawal , Barry Britton , Xiaojie He , Sajitha Wijesuriya , Ming H. Ding , Jun Zhao
发明人： Om P. Agrawal , Barry Britton , Xiaojie He , Sajitha Wijesuriya , Ming H. Ding , Jun Zhao
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17728
摘要： Systems and methods are disclosed herein to provide logic block slice architectures and programmable logic block architectures along with control logic architectures in accordance with embodiments of the present invention. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of programmable logic blocks, with at least one of the programmable logic blocks having at least a first, a second, and a third logic block slice of different logic block slice types.
摘要翻译：本文公开了系统和方法，以根据本发明的实施例提供逻辑块片段架构和可编程逻辑块架构以及控制逻辑架构。例如，根据本发明的实施例，可编程逻辑器件包括多个可编程逻辑块，其中至少一个可编程逻辑块具有至少第一，第二和第三逻辑块片不同的逻辑块片类型。

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