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11. 发明授权

US07545170B2 Source driver and level shifting method thereof 有权
标题翻译：源驱动器及其电平转换方法
公开(公告)号：US07545170B2
公开(公告)日：2009-06-09
申请号：US11675427
申请日：2007-02-15
申请人： Yu-Jui Chang , Wen-Teng Fan
发明人： Yu-Jui Chang , Wen-Teng Fan
IPC分类号： H03K19/0175
CPC分类号： H03K3/35613 , G09G3/3688 , G09G2310/027 , G09G2310/0289
摘要： The present invention provides a source driver comprising a shift register, a line buffer for storing a data signal and outputting a buffered data signal, and a level shifter for generating a level-shifted data signal based on the buffered data signal. The line buffer further comprises a charge pump supplying a pumped voltage based on a voltage source and a buffer powered by the pumped voltage and outputting a buffered data signal based on the data signal.
摘要翻译：本发明提供了一种源驱动器，包括移位寄存器，用于存储数据信号并输出缓冲数据信号的行缓冲器，以及用于基于缓冲的数据信号产生电平移位数据信号的电平转换器。线路缓冲器还包括电荷泵，其提供基于电压源的泵浦电压和由泵浦电压供电的缓冲器，并且基于数据信号输出缓冲的数据信号。

12. 发明授权

US08390614B2 Timing controller and clock signal detection circuit thereof 有权
标题翻译：定时控制器及其时钟信号检测电路
公开(公告)号：US08390614B2
公开(公告)日：2013-03-05
申请号：US12719649
申请日：2010-03-08
申请人： Wen-Teng Fan , Shih-Chun Lin
发明人： Wen-Teng Fan , Shih-Chun Lin
IPC分类号： G06F3/038 , G09G5/00
CPC分类号： G06F3/038 , H03L7/06
摘要： The clock signal detection circuit includes a lock detection circuit, a duty cycle detection circuit, a first logic circuit, and a counter. The lock detection circuit detects whether an input clock signal and a feedback clock signal of a delay locked loop are in phase. The duty cycle detection circuit detects whether the duty cycle of the input clock signal is within a percentage range. The first logic circuit, electrically connected to the lock detection circuit and the duty cycle detection circuit, outputs a detecting result signal which is at first logic level when the input clock signal are in phase with the feedback clock signal, and the duty cycle of the input clock signal is within a percentage range. The counter outputs a lock detection signal which is at the first logic level when the detecting result signal has maintained at the first logic level for a first constant period of time.
摘要翻译：时钟信号检测电路包括锁定检测电路，占空比检测电路，第一逻辑电路和计数器。锁定检测电路检测延迟锁定环路的输入时钟信号和反馈时钟信号是否同相。占空比检测电路检测输入时钟信号的占空比是否在百分比范围内。与锁定检测电路和占空比检测电路电连接的第一逻辑电路输出当输入时钟信号与反馈时钟信号同相时处于第一逻辑电平的检测结果信号，输入时钟信号在百分比范围内。当检测结果信号在第一恒定时间段内保持在第一逻辑电平时，计数器输出处于第一逻辑电平的锁定检测信号。

13. 发明授权

US08180006B2 Spread-spectrum generator 有权
标题翻译：扩频发生器
公开(公告)号：US08180006B2
公开(公告)日：2012-05-15
申请号：US12540817
申请日：2009-08-13
申请人： Wen-Teng Fan , Shih-Chun Lin
发明人： Wen-Teng Fan , Shih-Chun Lin
IPC分类号： H04L7/00 , H03D3/24 , H04B1/00
CPC分类号： H04B15/06 , H04B2215/064 , H04B2215/067
摘要： A spread-spectrum generator is provided. The spread-spectrum generator includes a delay module and a control module. The delay module is controlled by a first control signal to delay an input signal by a delay time, and thereby generate a delay signal. The control module is coupled to the delay module for detecting a first edge of the delay signal, and thereby generating the first control signal. Accordingly, the spread-spectrum generator can spread the frequency of the input signal by delaying the input signal by various delay time, and the spread-spectrum generator can also reduce electromagnetic interference (EMI).
摘要翻译：提供扩频发生器。扩频发生器包括延迟模块和控制模块。延迟模块由第一控制信号控制，以将输入信号延迟延迟时间，从而产生延迟信号。控制模块耦合到延迟模块，用于检测延迟信号的第一边缘，从而产生第一控制信号。因此，扩频发生器可以通过延迟输入信号各种延迟时间来扩展输入信号的频率，扩频发生器也可以减小电磁干扰（EMI）。

14. 发明授权

US07847603B2 Driving circuits in electronic device 有权
标题翻译：电子设备中的驱动电路
公开(公告)号：US07847603B2
公开(公告)日：2010-12-07
申请号：US12030513
申请日：2008-02-13
申请人： Wen-Teng Fan
发明人： Wen-Teng Fan
IPC分类号： H03B1/00
CPC分类号： G09G3/20 , G09G2310/0275 , H03K19/01707
摘要： In driving circuits, signal enhancing circuits are used to enhance driving ability of driving signals. Further, source follower transistors may further enhance driving ability of the driving circuits by conducting more current to loading, so that output signals of the driving circuits may transit more rapidly. In other words, the pull high ability of the driving circuits is enhanced.
摘要翻译：在驱动电路中，信号增强电路用于提高驱动信号的驱动能力。此外，源极跟随器晶体管可以通过传导更多的电流到负载来进一步增强驱动电路的驱动能力，使得驱动电路的输出信号可以更快地转换。换句话说，驱动电路的拉高能力得到提高。

15. 发明申请

US20100149171A1 SOURCE DRIVER FOR DRIVING A PANEL AND RELATED METHOD FOR CONTROLLING A DISPLAY 审中-公开
标题翻译：用于驱动面板的驱动器和用于控制显示器的相关方法
公开(公告)号：US20100149171A1
公开(公告)日：2010-06-17
申请号：US12335542
申请日：2008-12-16
申请人： Da-Rong Huang , Wen-Teng Fan
发明人： Da-Rong Huang , Wen-Teng Fan
IPC分类号： G09G5/00
CPC分类号： G09G3/3688 , G09G3/3614 , G09G2310/0291 , G09G2330/023
摘要： A source driver for driving a panel includes an output buffer. The output buffer includes a first amplifier, a second amplifier, and an internal switching unit. The first amplifier includes a first stage and a second stage. The second amplifier includes a first stage and a second stage. The internal switching unit selectively connects the first stages and the second stages of the first amplifier and the second amplifier. At a charge sharing stage, the internal switching unit performs charge sharing between the second stage of the first amplifier and the second stage of the second amplifier.
摘要翻译：用于驱动面板的源驱动器包括输出缓冲器。输出缓冲器包括第一放大器，第二放大器和内部开关单元。第一放大器包括第一级和第二级。第二放大器包括第一级和第二级。内部开关单元选择性地连接第一放大器和第二放大器的第一级和第二级。在电荷共享阶段，内部开关单元执行第一放大器的第二级与第二放大器的第二级之间的电荷共享。

16. 发明授权

US07639227B2 Integrated circuit capable of synchronizing multiple outputs of buffers 有权
标题翻译：能够同步多个缓冲器输出的集成电路
公开(公告)号：US07639227B2
公开(公告)日：2009-12-29
申请号：US11380009
申请日：2006-04-25
申请人： Kai-Lan Chuang , Chuan-Che Lee , Wen-Teng Fan
发明人： Kai-Lan Chuang , Chuan-Che Lee , Wen-Teng Fan
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G09G3/2092
摘要： A source driver of an LCD includes a first and second power sources, a first and second inversion units, a first and second charging switches, and a first and second discharging switches. The first charging switch is coupled to the first power source, a first end of the first inversion unit, and a second end of the second inversion unit. The second charging switch is coupled to the first power source, a first end of the second inversion unit, and a second end of the first inversion unit. The first discharging switch is coupled to the second power source, the second end of the first inversion unit, and the first end of the second inversion unit. The second discharging switch is coupled to the second power source, the second end of the second inversion unit, and the first end of the first inversion unit.
摘要翻译： LCD的源极驱动器包括第一和第二电源，第一和第二反相单元，第一和第二充电开关以及第一和第二放电开关。第一充电开关耦合到第一电源，第一反转单元的第一端和第二反转单元的第二端。第二充电开关耦合到第一电源，第二反转单元的第一端和第一反转单元的第二端。第一放电开关耦合到第二电源，第一反转单元的第二端和第二反转单元的第一端。第二放电开关耦合到第二电源，第二反转单元的第二端和第一反转单元的第一端。

17. 发明申请

US20110038397A1 SPREAD-SPECTRUM GENERATOR 有权
标题翻译：扩频发生器
公开(公告)号：US20110038397A1
公开(公告)日：2011-02-17
申请号：US12540817
申请日：2009-08-13
申请人： Wen-Teng Fan , Shih-Chun Lin
发明人： Wen-Teng Fan , Shih-Chun Lin
IPC分类号： H04B1/69
CPC分类号： H04B15/06 , H04B2215/064 , H04B2215/067
摘要： A spread-spectrum generator is provided. The spread-spectrum generator includes a delay module and a control module. The delay module is controlled by a first control signal to delay an input signal by a delay time, and thereby generate a delay signal. The control module is coupled to the delay module for detecting a first edge of the delay signal, and thereby generating the first control signal. Accordingly, the spread-spectrum generator can spread the frequency of the input signal by delaying the input signal by various delay time, and the spread-spectrum generator can also reduce electromagnetic interference (EMI).
摘要翻译：提供扩频发生器。扩频发生器包括延迟模块和控制模块。延迟模块由第一控制信号控制，以将输入信号延迟延迟时间，从而产生延迟信号。控制模块耦合到延迟模块，用于检测延迟信号的第一边缘，从而产生第一控制信号。因此，扩频发生器可以通过延迟输入信号各种延迟时间来扩展输入信号的频率，扩频发生器也可以减小电磁干扰（EMI）。

18. 发明申请

US20100245368A1 METHOD FOR TRANSMITTING IMAGE DATA THROUGH RSDS TRANSMISSION INTERFACES 有权
标题翻译：通过RSDS传输接口传输图像数据的方法
公开(公告)号：US20100245368A1
公开(公告)日：2010-09-30
申请号：US12411172
申请日：2009-03-25
申请人： Ying-Lieh Chen , Wen-Teng Fan , Chao-Ching Chi
发明人： Ying-Lieh Chen , Wen-Teng Fan , Chao-Ching Chi
IPC分类号： G06T1/20
CPC分类号： G09G3/20 , G09G2370/14
摘要： A method for transmitting image data in a display is provided. The method includes the steps of: sending first pixel data through a first bus to a source driver; sending second pixel data through a second bus to the source driver; reorganizing the first pixel data and the second pixel data in the source driver; and generating third pixel data according to the reorganization of the first pixel data and the second pixel data for channels in the source driver. A display is also disclosed herein.
摘要翻译：提供了一种在显示器中传送图像数据的方法。该方法包括以下步骤：通过第一总线将第一像素数据发送到源驱动器; 通过第二总线向源驱动器发送第二像素数据; 重新组织源驱动器中的第一像素数据和第二像素数据; 以及根据所述源驱动器中的所述第一像素数据和所述第二像素数据的重新组合来生成第三像素数据。本文还公开了一种显示器。

19. 发明申请

US20090206878A1 LEVEL SHIFT CIRCUIT FOR A DRIVING CIRCUIT 审中-公开
标题翻译：驱动电路的电平转换电路
公开(公告)号：US20090206878A1
公开(公告)日：2009-08-20
申请号：US12031162
申请日：2008-02-14
申请人： Wen-Teng Fan
发明人： Wen-Teng Fan
IPC分类号： H03K19/0175
CPC分类号： H03K3/356139
摘要： Provided is a level shift circuit for a driving circuit. The level shift circuit includes: a cross-coupled transistor pair, for receiving a first input signal and a second input signal and for providing a first output signal and a second output signal; a first transistor, coupled to a first power supply and to the cross-coupled transistor pair, further receiving a first control signal; a second transistor, coupled to the cross-coupled transistor pair and for receiving a second control signal; and a third transistor, coupled to the cross-coupled transistor pair and for receiving the second control signal. The first control signal, the second control signal, the first output signal and the second output signal are all referenced to the first power supply, and the first input signal and the second input signal are referenced to a second power supply lower than the first power supply.
摘要翻译：提供了一种用于驱动电路的电平移位电路。电平移位电路包括：交叉耦合晶体管对，用于接收第一输入信号和第二输入信号，并用于提供第一输出信号和第二输出信号; 第一晶体管，耦合到第一电源和交叉耦合晶体管对，进一步接收第一控制信号; 第二晶体管，耦合到交叉耦合晶体管对并用于接收第二控制信号; 以及耦合到所述交叉耦合晶体管对并用于接收所述第二控制信号的第三晶体管。第一控制信号，第二控制信号，第一输出信号和第二输出信号均以第一电源为基准，第一输入信号和第二输入信号参考低于第一电源的第二电源供应。

20. 发明授权

US08222941B2 Phase selector 有权
标题翻译：相位选择器
公开(公告)号：US08222941B2
公开(公告)日：2012-07-17
申请号：US12759886
申请日：2010-04-14
申请人： Wen-Teng Fan , Chan-Fei Lin , Shih-Chun Lin
发明人： Wen-Teng Fan , Chan-Fei Lin , Shih-Chun Lin
IPC分类号： H03L7/00
CPC分类号： H03K5/135 , H03K2005/00052 , H03L7/0812
摘要： A phase selector including a plurality of buffers, a multiplexer, a first inverter, and a selecting circuit is provided. Each of the buffers provides a clock signal, and the clock signals have different phases. The multiplexer selectively outputs one of the clock signals as a switch signal according to a first control signal, wherein the first control signal is first portion of bits of a selecting signal. The input terminal of the first inverter receives a second control signal, wherein the second control signal is second portion of bits of the selecting signal, and the output terminal of the first inverter outputs an inverted signal. The selecting circuit transmits the second control signal of the selecting signal or the inverted signal to the output terminal of the phase selector according to the logic state of the switch signal.
摘要翻译：提供了包括多个缓冲器的相位选择器，多路复用器，第一反相器和选择电路。每个缓冲器提供时钟信号，并且时钟信号具有不同的相位。复用器根据第一控制信号选择性地输出其中一个时钟信号作为开关信号，其中第一控制信号是选择信号的位的第一部分。第一反相器的输入端接收第二控制信号，其中第二控制信号是选择信号的位的第二部分，第一反相器的输出端输出反相信号。选择电路根据开关信号的逻辑状态将选择信号或反相信号的第二控制信号发送到相位选择器的输出端。

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