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11. 发明申请

US20060246720A1 Method to improve thermal stability of silicides with additives 审中-公开
标题翻译：提高添加剂硅化物热稳定性的方法
公开(公告)号：US20060246720A1
公开(公告)日：2006-11-02
申请号：US11117152
申请日：2005-04-28
申请人： Chii-Ming Wu , Shih-Wei Chou , Cheng-Tung Lin , Chih-Wei Chang , Shau-Lin Shue
发明人： Chii-Ming Wu , Shih-Wei Chou , Cheng-Tung Lin , Chih-Wei Chang , Shau-Lin Shue
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L21/28518
摘要： A semiconductor method of manufacture involving suicides is provided. Embodiments comprise forming a stacked arrangement of layers, the stacked arrangement of layers comprising an additive layer on a substrate, and a metal layer on the additive layer, annealing the stacked arrangement of layers to form a metal silicide layer on the substrate, wherein the metal silicide layer includes an additive from the additive layer. Alternative embodiments include etching the stacked arrangement of layers to remove an unreacted material layer. In an alternative embodiment, the stacked arrangement of layer comprises a metal layer on a substrate, an additive layer on the metal layer, and an optional oxygen barrier layer on the additive layer. An annealing process forms a metal silicide containing an additive. Metal silicides formed according to embodiments are particularly resistant to agglomeration during high temperature processing.
摘要翻译：提供涉及自杀的半导体制造方法。实施例包括形成层的堆叠布置，在衬底上包括添加层的层的堆叠排列以及添加层上的金属层，退火层的层叠布置以在衬底上形成金属硅化物层，其中金属硅化物层包括来自添加剂层的添加剂。替代实施例包括蚀刻层的堆叠布置以去除未反应的材料层。在替代实施例中，层的堆叠布置包括在基底上的金属层，金属层上的添加层和在添加剂层上的任选的氧阻隔层。退火工艺形成含有添加剂的金属硅化物。根据实施例形成的金属硅化物特别耐高温处理期间的附聚。

12. 发明申请

US20050272235A1 Method of forming silicided gate structure 失效
标题翻译：形成硅化栅结构的方法
公开(公告)号：US20050272235A1
公开(公告)日：2005-12-08
申请号：US10859730
申请日：2004-06-03
申请人： Chii-Ming Wu , Cheng-Tung Lin , Mei-Yun Wang , Chih-Wei Chang , Shau-Lin Shue
发明人： Chii-Ming Wu , Cheng-Tung Lin , Mei-Yun Wang , Chih-Wei Chang , Shau-Lin Shue
IPC分类号： H01L21/28 , H01L21/285 , H01L21/336 , H01L21/4763 , H01L29/49
CPC分类号： H01L21/28097 , H01L21/28518 , H01L29/4975 , H01L29/66507 , H01L29/785
摘要： A method of forming a silicided gate of a field effect transistor on a substrate having active regions is provided. The method includes the following steps: (a) forming a silicide in at least a first portion of a gate; (b) after step (a), depositing a metal over the active regions and said gate; and (c) annealing to cause the metal to react to form silicide in the active regions, wherein the thickness of said gate silicide is greater than the thickness of said silicide in said active regions.
摘要翻译：提供了在具有有源区的基板上形成场效应晶体管的硅化物栅的方法。该方法包括以下步骤：（a）在栅极的至少第一部分中形成硅化物; （b）在步骤（a）之后，在有源区域和所述栅极上沉积金属; 和（c）退火以引起金属反应以在有源区中形成硅化物，其中所述栅极硅化物的厚度大于所述有源区中所述硅化物的厚度。

13. 发明申请

US20050092598A1 Sputtering process with temperature control for salicide application 审中-公开
标题翻译：用于自杀剂应用的温度控制的溅射过程
公开(公告)号：US20050092598A1
公开(公告)日：2005-05-05
申请号：US10702970
申请日：2003-11-05
申请人： Mei-Yun Wang , Chih-Wei Chang , Chii-Ming Wu , Cheng-Tung Lin , Shau-Lin Shue
发明人： Mei-Yun Wang , Chih-Wei Chang , Chii-Ming Wu , Cheng-Tung Lin , Shau-Lin Shue
IPC分类号： C23C14/16 , H01L21/285 , C23C16/00 , C23C14/32
CPC分类号： H01L21/28518 , C23C14/16
摘要： A process for reducing the thermal budget and enhancing stability in the thermal budget of a metal salicide process used in the formation of metal salicides on substrates, thus eliminating or reducing salicide spiking and junction leakage in microelectronic devices fabricated on the substrates. According to a typical embodiment, a substrate is cooled to a sub-processing temperature which is lower than the metal deposition processing temperature and the salicide-forming metal is deposited onto the reduced-temperature substrate.
摘要翻译：一种用于降低热预算并增强用于在基材上形成金属硅化物的金属硅化物工艺的热预算中的稳定性的方法，从而消除或减少在衬底上制造的微电子器件中的自杀剂尖峰和结漏电。根据典型的实施方式，将基板冷却至比金属沉积处理温度低的副处理温度，并将形成自杀型化合物的金属沉积在还原温度基板上。

14. 发明授权

US07446042B2 Method for silicide formation on semiconductor devices 有权
标题翻译：在半导体器件上形成硅化物的方法
公开(公告)号：US07446042B2
公开(公告)日：2008-11-04
申请号：US11343648
申请日：2006-01-30
申请人： Chii-Ming Wu , Shih-Wei Chou , Gin Jei Wang , Cheng-Tung Lin , Chih-Wei Chang , Shau-Lin Shue
发明人： Chii-Ming Wu , Shih-Wei Chou , Gin Jei Wang , Cheng-Tung Lin , Chih-Wei Chang , Shau-Lin Shue
IPC分类号： H01L21/44
CPC分类号： H01L21/28518
摘要： A method for forming nickel silicide includes degassing a semiconductor substrate that includes a silicon surface. After the degassing operation, the substrate is cooled prior to a metal deposition process, during a metal deposition process, or both. The cooling suppresses the temperature of the substrate to a temperature less than the temperature required for the formation of nickel silicide. Nickel diffusion is minimized during the deposition process. After deposition, an annealing process is used to urge the formation of a uniform silicide film. In various embodiments, the metal film may include a binary phase alloy containing nickel and a further element.
摘要翻译：一种形成硅化镍的方法包括对包含硅表面的半导体衬底脱气。在脱气操作之后，在金属沉积工艺，金属沉积工艺期间或两者之间冷却基板。冷却将基板的温度抑制到低于形成硅化镍所需的温度的温度。在沉积过程中镍的扩散最小化。沉积后，使用退火工艺来促使形成均匀的硅化物膜。在各种实施例中，金属膜可以包括含有镍和另一元素的二元相合金。

15. 发明授权

US07396767B2 Semiconductor structure including silicide regions and method of making same 有权
标题翻译：包括硅化物区域的半导体结构及其制造方法
公开(公告)号：US07396767B2
公开(公告)日：2008-07-08
申请号：US10892915
申请日：2004-07-16
申请人： Chii-Ming Wu , Cheng-Tung Lin , Mei-Yun Wang , Chih-Wei Chang , Shau-Lin Shue
发明人： Chii-Ming Wu , Cheng-Tung Lin , Mei-Yun Wang , Chih-Wei Chang , Shau-Lin Shue
IPC分类号： H01L21/44
CPC分类号： H01L29/66507 , H01L21/28097 , H01L29/458 , H01L29/4908
摘要： A method of forming a silicided gate on a substrate having active regions, comprising the steps of: forming a first silicide in the active regions from a first material; and forming a second silicide in the gate from a second material, wherein the first silicide forms a barrier against the second material forming a silicide in the active regions during the second silicide forming step, wherein said second silicide is thicker than said first silicide.
摘要翻译：一种在具有有源区的衬底上形成硅化栅的方法，包括以下步骤：在有源区中从第一材料形成第一硅化物; 以及从所述第二材料在所述栅极中形成第二硅化物，其中所述第一硅化物在所述第二硅化物形成步骤期间在所述有源区中形成抵抗所述第二材料形成硅化物的势垒，其中所述第二硅化物比所述第一硅化物厚。

16. 发明申请

US20060011996A1 Semiconductor structure including silicide regions and method of making same 有权
标题翻译：包括硅化物区域的半导体结构及其制造方法
公开(公告)号：US20060011996A1
公开(公告)日：2006-01-19
申请号：US10892915
申请日：2004-07-16
申请人： Chii-Ming Wu , Cheng-Tung Lin , Mei-Yun Wang , Chih-Wei Chang , Shau-Lin Shue
发明人： Chii-Ming Wu , Cheng-Tung Lin , Mei-Yun Wang , Chih-Wei Chang , Shau-Lin Shue
IPC分类号： H01L21/336 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/66507 , H01L21/28097 , H01L29/458 , H01L29/4908
摘要： A method of forming a silicided gate on a substrate having active regions, comprising the steps of: forming a first silicide in the active regions from a first material; and forming a second silicide in the gate from a second material, wherein the first silicide forms a barrier against the second material forming a silicide in the active regions during the second silicide forming step, wherein said second silicide is thicker than said first silicide.
摘要翻译：一种在具有有源区的衬底上形成硅化栅的方法，包括以下步骤：在有源区中从第一材料形成第一硅化物; 以及从所述第二材料在所述栅极中形成第二硅化物，其中所述第一硅化物在所述第二硅化物形成步骤期间在所述有源区中形成抵抗所述第二材料形成硅化物的势垒，其中所述第二硅化物比所述第一硅化物厚。

17. 发明申请

US20070221993A1 Method for making a thermally stable silicide 审中-公开
标题翻译：制造耐热硅化物的方法
公开(公告)号：US20070221993A1
公开(公告)日：2007-09-27
申请号：US11389309
申请日：2006-03-27
申请人： Shau-Lin Shue , Chen-Hua Yu , Cheng-Tung Lin , Chii-Ming Wu , Shih-Wei Chou , Gin Wang , Cp Lo , Chih-W Chang
发明人： Shau-Lin Shue , Chen-Hua Yu , Cheng-Tung Lin , Chii-Ming Wu , Shih-Wei Chou , Gin Wang , Cp Lo , Chih-W Chang
IPC分类号： H01L27/12 , H01L27/01 , H01L31/0392
CPC分类号： H01L29/665 , H01L21/76243 , H01L29/785
摘要： A semiconductor device and method of manufacturing are provided that include forming an alloy layer having the formula MbX over a silicon-containing substrate, where Mb is a metal and X is an alloying additive, the alloy layer being annealed to form a metal alloy silicide layer on the gate region and in active regions of the semiconductor device.
摘要翻译：提供一种半导体器件和制造方法，包括在含硅衬底上形成具有式MbX的合金层，其中Mb是金属，X是合金添加剂，合金层被退火以形成金属合金硅化物层在栅极区域和半导体器件的有源区中。

18. 发明授权

US08822293B2 Self-aligned halo/pocket implantation for reducing leakage and source/drain resistance in MOS devices 有权
标题翻译：自对准晕圈/凹穴注入，用于减少MOS器件中的漏电和源极/漏极电阻
公开(公告)号：US08822293B2
公开(公告)日：2014-09-02
申请号：US12048119
申请日：2008-03-13
申请人： Chen-Hua Yu , Yihang Chiu , Shu-Tine Yang , Jyh-Cherng Sheu , Chu-Yun Fu , Cheng-Tung Lin
发明人： Chen-Hua Yu , Yihang Chiu , Shu-Tine Yang , Jyh-Cherng Sheu , Chu-Yun Fu , Cheng-Tung Lin
IPC分类号： H01L21/336 , H01L29/78 , H01L21/265 , H01L29/66 , H01L29/165
CPC分类号： H01L29/7848 , H01L21/26586 , H01L29/165 , H01L29/66537 , H01L29/6659 , H01L29/7833
摘要： A method of forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate, wherein the semiconductor substrate and a sidewall of the gate dielectric has a joint point; forming a gate electrode over the gate dielectric; forming a mask layer over the semiconductor substrate and the gate electrode, wherein a first portion of the mask layer adjacent the joint point is at least thinner than a second portion of the mask layer away from the joint point; after the step of forming the mask layer, performing a halo/pocket implantation to introduce a halo/pocket impurity into the semiconductor substrate; and removing the mask layer after the halo/pocket implantation.
摘要翻译：一种形成半导体结构的方法包括：提供半导体衬底; 在所述半导体衬底上形成栅极电介质，其中所述半导体衬底和所述栅极电介质的侧壁具有接合点; 在所述栅极电介质上形成栅电极; 在所述半导体衬底和所述栅极电极上形成掩模层，其中所述掩模层的与所述接合点相邻的第一部分至少比所述掩模层的离开所述接合点的第二部分更薄; 在形成掩模层的步骤之后，进行晕/穴注入以将卤素/杂质杂质引入到半导体衬底中; 并且在光晕/口袋植入之后去除掩模层。

19. 发明授权

US08138076B2 MOSFETs having stacked metal gate electrodes and method 有权
标题翻译：具有层叠金属栅电极的MOSFET和方法
公开(公告)号：US08138076B2
公开(公告)日：2012-03-20
申请号：US12118919
申请日：2008-05-12
申请人： Cheng-Tung Lin , Yung-Sheng Chiu , Hsiang-Yi Wang , Chia-Lin Yu , Chen-Hua Yu
发明人： Cheng-Tung Lin , Yung-Sheng Chiu , Hsiang-Yi Wang , Chia-Lin Yu , Chen-Hua Yu
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/28088 , H01L21/28079 , H01L21/28185 , H01L21/3141 , H01L21/823437 , H01L21/823828 , H01L29/513 , H01L29/517
摘要： MOSFETs having stacked metal gate electrodes and methods of making the same are provided. The MOSFET gate electrode includes a gate metal layer formed atop a high-k gate dielectric layer. The metal gate electrode is formed through a low oxygen content deposition process without charged-ion bombardment to the wafer substrate. Metal gate layer thus formed has low oxygen content and may prevent interfacial oxide layer regrowth. The process of forming the gate metal layer generally avoids plasma damage to the wafer substrate.
摘要翻译：提供具有层叠金属栅电极的MOSFET及其制造方法。 MOSFET栅电极包括形成在高k栅极电介质层顶上的栅极金属层。通过低氧含量沉积工艺形成金属栅电极而不对晶片衬底进行带电离子轰击。如此形成的金属栅极层的氧含量低，并且可以防止界面氧化层再生长。形成栅极金属层的过程通常避免了对晶片衬底的等离子体损伤。

20. 发明授权

US07799628B2 Advanced metal gate method and device 有权
标题翻译：先进的金属门法和器件
公开(公告)号：US07799628B2
公开(公告)日：2010-09-21
申请号：US12354558
申请日：2009-01-15
申请人： Chung-Shi Liu , Hsiang-Yi Wang , Cheng-Tung Lin , Chen-Hua Yu
发明人： Chung-Shi Liu , Hsiang-Yi Wang , Cheng-Tung Lin , Chen-Hua Yu
IPC分类号： H01L21/8238
CPC分类号： H01L21/28088 , H01L21/265 , H01L21/823835 , H01L21/823842 , H01L29/4966 , H01L29/51 , H01L29/78
摘要： The present disclosure provides a method of fabricating a semiconductor device that includes forming a high-k dielectric over a substrate, forming a first metal layer over the high-k dielectric, forming a second metal layer over the first metal layer, forming a first silicon layer over the second metal layer, implanting a plurality of ions into the first silicon layer and the second metal layer overlying a first region of the substrate, forming a second silicon layer over the first silicon layer, patterning a first gate structure over the first region and a second gate structure over a second region, performing an annealing process that causes the second metal layer to react with the first silicon layer to form a silicide layer in the first and second gate structures, respectively, and driving the ions toward an interface of the first metal layer and the high-k dielectric in the first gate structure.
摘要翻译：本公开提供一种制造半导体器件的方法，其包括在衬底上形成高k电介质，在高k电介质上形成第一金属层，在第一金属层上形成第二金属层，形成第一硅在所述第二金属层上方，将多个离子注入到所述第一硅层中，并且所述第二金属层覆盖在所述基板的第一区域上，在所述第一硅层上形成第二硅层，在所述第一区上形成第一栅极结构以及在第二区域上的第二栅极结构，执行使所述第二金属层与所述第一硅层反应以在所述第一和第二栅极结构中分别形成硅化物层的退火处理，并将所述离子驱动到第一栅极结构中的第一金属层和高k电介质。

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