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11. 发明申请

US20120089051A1 Blood Glucose Meter Having Integral Lancet Device And Test Strip Storage Vial For Single Handed Use And Methods For Using Same 有权
标题翻译：具有整体柳叶刀装置的血糖仪和用于单手使用的测试条储存瓶和使用相同的方法
公开(公告)号：US20120089051A1
公开(公告)日：2012-04-12
申请号：US13330330
申请日：2011-12-19
申请人： Gregg R. Draudt , Dirk Ahlgrim , Jan Schminke , Mark Follman , José Colucci, JR. , Raymond Yao , Robert J. McCaffrey , Victor Chan
发明人： Gregg R. Draudt , Dirk Ahlgrim , Jan Schminke , Mark Follman , José Colucci, JR. , Raymond Yao , Robert J. McCaffrey , Victor Chan
IPC分类号： A61B5/151
CPC分类号： A61B5/14532 , A61B5/150022 , A61B5/150175 , A61B5/150259 , A61B5/150358 , A61B5/15087 , A61B5/15113 , A61B5/15115 , A61B5/15186 , A61B5/1519 , A61B5/157 , A61B2562/0295 , G01N33/523 , G01N33/526 , G01N33/66
摘要： A blood glucose meter having a test strip port and an adjustable lancet device disposed at the same end of the device body is disclosed. The device body further includes an enclosure at the proximal end of the device body which houses a test strip storage vial and which facilitates one-handed opening and closing of the vial to simplify access to test strips contained therein. The enclosure is further provided with a window which allows the reading of the lot numbers on the label of the test strip vial therein without necessitating removal of the vial. A data connector is also provided on the device body for communication access, such as to upload data from other devices or to download data to other devices.
摘要翻译：公开了一种具有测试条端口和设置在装置本体的同一端的可调整的柳叶刀装置的血糖仪。装置主体还包括位于装置本体的近端处的壳体，其容纳测试条存储小瓶并且便于单手打开和关闭小瓶以简化对其中包含的测试条的访问。外壳还设置有窗口，其允许读取测试条瓶标签上的批号，而不需要移除小瓶。数据连接器还提供在设备主体上用于通信访问，例如从其他设备上传数据或将数据下载到其他设备。

12. 发明申请

US20080290379A1 DUAL TRENCH ISOLATION FOR CMOS WITH HYBRID ORIENTATIONS 有权
标题翻译： CMOS混合方向的双路隔离
公开(公告)号：US20080290379A1
公开(公告)日：2008-11-27
申请号：US12169991
申请日：2008-07-09
申请人： Victor Chan , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Chun-yung Sung , Min Yang
发明人： Victor Chan , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Chun-yung Sung , Min Yang
IPC分类号： H01L21/8234 , H01L29/04
CPC分类号： H01L21/76229
摘要： The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a first trench isolation region of a first depth isolates devices of different polarity from each other, while second trench isolation regions of a second depth, which is shallower than the first depth, are used to isolate devices of the same polarity from each other. The present invention further provides a dual trench semiconductor structure in which pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane. In accordance with the present invention, the devices of different polarity, i.e., nFETs and pFETs, are bulk-like devices.
摘要翻译：本发明提供了一种半导体结构，其中不同类型的器件位于混合衬底的特定晶体取向上，这增强了每种器件的性能。在本发明的半导体结构中，采用双沟槽隔离方案，由此第一深度的第一沟槽隔离区将彼此不同极性的器件隔离，而第二深度的第二沟槽隔离区比第第一深度用于隔离相同极性的设备。本发明还提供一种双沟槽半导体结构，其中pFET位于（110）结晶平面上，而nFET位于（100）晶面上。根据本发明，不同极性的器件，即nFET和pFETs是大块状器件。

13. 发明申请

US20080173934A1 INTEGRATED CIRCUIT SYSTEM EMPLOYING STRESS-ENGINEERED SPACERS 有权
标题翻译：集成电路系统应用于工程应用的空间
公开(公告)号：US20080173934A1
公开(公告)日：2008-07-24
申请号：US12048994
申请日：2008-03-14
申请人： Jae Gon Lee , Jong Ho Yang , Victor Chan , Jun Jung Kim
发明人： Jae Gon Lee , Jong Ho Yang , Victor Chan , Jun Jung Kim
IPC分类号： H01L27/092
CPC分类号： H01L29/7833 , H01L21/823807 , H01L21/823864 , H01L27/0629 , H01L27/092 , H01L29/165 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： An integrated circuit system that includes: providing a substrate including a first region with a first device and a second device and a second region with a resistance device; configuring the first device, the second device, and the resistance device to include a first spacer and a second spacer; forming a stress inducing layer over the first region and the second region; processing at least a portion of the stress inducing layer formed over the first region to alter the stress within the stress inducing layer; and forming a third spacer adjacent the second spacer of the first device and the second device from the stress inducing layer.
摘要翻译：一种集成电路系统，包括：提供包括具有第一装置的第一区域的基板和具有电阻装置的第二区域; 配置第一装置，第二装置和电阻装置以包括第一间隔件和第二间隔件; 在所述第一区域和所述第二区域上形成应力诱导层; 处理形成在第一区域上的应力诱导层的至少一部分，以改变应力诱导层内的应力; 以及从所述应力诱导层形成邻近所述第一器件和所述第二器件的第二间隔物的第三间隔物。

14. 发明授权

US07401095B2 Method and system for composing a query for a database and traversing the database 有权
标题翻译：用于组合数据库查询并遍历数据库的方法和系统
公开(公告)号：US07401095B2
公开(公告)日：2008-07-15
申请号：US11246341
申请日：2005-10-07
申请人： Victor Chan , Fen Wang , Mark W. Hubbard
发明人： Victor Chan , Fen Wang , Mark W. Hubbard
IPC分类号： G06F17/00
CPC分类号： G06F17/30433 , G06F17/30477 , Y10S706/922 , Y10S707/99933 , Y10S707/99934 , Y10S707/99935 , Y10S707/99936 , Y10S707/99943 , Y10S707/99945
摘要： A system and method of composing a query object for application against a database is provided. The method composes a selection clause for the query. Next, a criteria clause for the query is generated, with the criteria clause comprising input criteria related to the query, additional criteria specified against the query, and generated criteria based on a joint relationship. Next a source clause utilizing elements in the database accessed by the query is generated. A database traversal system and method is provided. The method identifies all tables directly accessible by each table and creates a data structure comprising an entry for each table. The entry comprises an identification field for each table and a link field identifying all tables directly accessible by each table. The data structure is traversed and an optimum path of the traversal paths utilizing data obtained from traversing the data structure is identified.
摘要翻译：提供了一种组合用于数据库应用的查询对象的系统和方法。该方法为查询组成一个选择子句。接下来，生成查询的条件子句，其中条件子句包括与查询相关的输入条件，针对查询指定的附加条件以及基于联合关系生成的条件。接下来，生成一个使用查询访问的数据库中的元素的源子句。提供了数据库遍历系统和方法。该方法识别每个表可以直接访问的所有表，并创建一个包含每个表的条目的数据结构。条目包括每个表的标识字段和标识由每个表可直接访问的所有表的链接字段。遍历数据结构，并且识别遍历数据结构获得的数据的遍历路径的最佳路径。

15. 发明申请

US20080044966A1 ENHANCEMENT OF ELECTRON AND HOLE MOBILITIES IN <110> Si UNDER BIAXIAL COMPRESSIVE STRAIN 有权
公开(公告)号：US20080044966A1
公开(公告)日：2008-02-21
申请号：US11924024
申请日：2007-10-25
申请人： Victor Chan , Massimo Fischetti , John Hergenrother , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Paul Solomon , Chun-yung Sung , Min Yang
发明人： Victor Chan , Massimo Fischetti , John Hergenrother , Meikei Ieong , Rajesh Rengarajan , Alexander Reznicek , Paul Solomon , Chun-yung Sung , Min Yang
IPC分类号： H01L21/8234
CPC分类号： H01L29/7842 , H01L21/823807 , H01L29/045 , H01L29/6659 , H01L29/7833 , H01L29/7843 , H01L29/7846 , H01L29/78684
摘要： The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing layer; and creating a biaxial strain in the silicon-containing layer.

16. 发明申请

US20070174098A1 Business context sensitive attribute override 审中-公开
标题翻译：业务上下文敏感属性覆盖
公开(公告)号：US20070174098A1
公开(公告)日：2007-07-26
申请号：US11336249
申请日：2006-01-20
申请人： Lev Mirtas , Victor Chan , Aalim Lakhani
发明人： Lev Mirtas , Victor Chan , Aalim Lakhani
IPC分类号： G06F17/50
CPC分类号： G06Q10/06 , G06Q20/108
摘要： A context sensitive object attribute override method includes retrieving an object attribute responsive to a request for the object attribute in a transaction in a commerce system, determining whether a context for the transaction is associated with an overridden form of the object attribute, and overriding the object attribute with the overridden form if the context for the transaction is associated with the overridden form of the object attribute.
摘要翻译：上下文敏感对象属性覆盖方法包括响应于在商务系统中的事务中的对象属性的请求来检索对象属性，确定事务的上下文是否与对象属性的重写形式相关联，并且覆盖对象如果事务的上下文与对象属性的覆盖形式相关联，则使用重写形式的属性。

17. 发明申请

US20070158763A1 SEMICONDUCTOR TRANSISTORS WITH EXPANDED TOP PORTIONS OF GATES 有权
标题翻译：具有膨胀的顶部顶部的半导体晶体管
公开(公告)号：US20070158763A1
公开(公告)日：2007-07-12
申请号：US11275514
申请日：2006-01-11
申请人： Brent Anderson , Victor Chan , Edward Nowak
发明人： Brent Anderson , Victor Chan , Edward Nowak
IPC分类号： H01L29/76 , H01L21/3205
CPC分类号： H01L29/66477 , H01L21/26506 , H01L21/28052 , H01L21/28114 , H01L21/28518 , H01L29/1083 , H01L29/42376 , H01L29/66507 , H01L29/6659 , H01L29/66772 , H01L29/66795 , H01L29/785 , H01L29/78654
摘要： A semiconductor transistor with an expanded top portion of a gate and a method for forming the same. The semiconductor transistor with an expanded top portion of a gate includes (a) a semiconductor region which includes a channel region and first and second source/drain regions; the channel region is disposed between the first and second source/drain regions, (b) a gate dielectric region in direct physical contact with the channel region, and (c) a gate electrode region which includes a top portion and a bottom portion. The bottom portion is in direct physical contact with the gate dielectric region. A first width of the top portion is greater than a second width of the bottom portion. The gate electrode region is electrically insulated from the channel region by the gate dielectric region.
摘要翻译：具有扩大的栅极顶部的半导体晶体管及其形成方法。具有扩大的栅极顶部的半导体晶体管包括：（a）包括沟道区和第一和第二源极/漏极区的半导体区; 沟道区域设置在第一和第二源极/漏极区域之间，（b）与沟道区域直接物理接触的栅极电介质区域，以及（c）包括顶部和底部的栅电极区域。底部部分与栅介质区域直接物理接触。顶部的第一宽度大于底部的第二宽度。栅电极区域通过栅极电介质区域与沟道区域电绝缘。

18. 发明申请

US20070122982A1 Method of applying stresses to PFET and NFET transistor channels for improved performance 有权
标题翻译：向PFET和NFET晶体管通道施加应力以提高性能的方法
公开(公告)号：US20070122982A1
公开(公告)日：2007-05-31
申请号：US11657154
申请日：2007-01-24
申请人： Victor Chan , Yong Lee , Haining Yang
发明人： Victor Chan , Yong Lee , Haining Yang
IPC分类号： H01L21/8234
CPC分类号： H01L29/7843 , H01L21/823807 , H01L29/665
摘要： A method is provided for fabricating a semiconductor device structure. In such method a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), each of the NFET and the PFET having a conduction channel disposed in a single-crystal semiconductor region of a substrate. A stressed film having a compressive stress at a first magnitude can be formed to overlie the PFET and the NFET. Desirably, a mask is formed to cover the PFET while exposing the NFET, after which, desirably, a portion of the stressed film overlying the NFET is subjected to ion implantation, while the mask protects another portion of the stressed film overlying the PFET from the ion implantation. The substrate can then be annealed, whereby, desirably, the compressive stress of the implanted portion of the stressed film is much reduced from the first magnitude by the annealing. In such way, the implanted portion of the stressed film overlying the NFET desirably imparts one of a much reduced magnitude compressive stress, a zero stress and a tensile stress to the conduction channel of the NFET. Another portion of the stressed film can continue to impart the compressive stress at the first magnitude to the conduction channel of the PFET.
摘要翻译：提供了制造半导体器件结构的方法。在这种方法中，p型场效应晶体管（PFET）和n型场效应晶体管（NFET），NFET和PFET中的每一个具有设置在基板的单晶半导体区域中的导电沟道。可以形成具有第一大小的压应力的应力膜覆盖在PFET和NFET上。期望地，形成掩模以在暴露NFET的同时覆盖PFET，之后理想地，覆盖NFET的应力膜的一部分经受离子注入，而掩模保护覆盖PFET的应力膜的另一部分与离子注入。然后可以对衬底进行退火，因此期望地，应力膜的注入部分的压缩应力通过退火从第一量级大大降低。以这种方式，覆盖NFET的应力膜的注入部分期望地将大大减小的压缩应力，零应力和拉伸应力中的一个施加到NFET的传导通道。应力膜的另一部分可以继续将第一大小的压应力赋予PFET的传导通道。

19. 发明申请

US20070056380A1 MECHANICAL STRESS CHARACTERIZATION IN SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件中的机械应力特性
公开(公告)号：US20070056380A1
公开(公告)日：2007-03-15
申请号：US11162295
申请日：2005-09-06
申请人： Victor Chan , Khee Lim
发明人： Victor Chan , Khee Lim
IPC分类号： G01B7/16
CPC分类号： G01R31/2648
摘要： Methods of characterizing a mechanical stress level in a stressed layer of a transistor and a mechanical stress characterizing test structure are disclosed. In one embodiment, the test structure includes a first test transistor including a first stress level; and at least one second test transistor having a substantially different second stress level. A testing circuit can then be used to characterize the mechanical stress level by comparing performance of the first test transistor and the at least one second test transistor. The type of test structure depends on the integration scheme used. In one embodiment, at least one second test transistor is provided with a substantially neutral stress level and/or an opposite stress level from the first stress level. The substantially neutral stress level may be provided by either rotating the transistor, removing the stressed layer causing the stress level or de-stressing the stressed layer causing the stress layer.
摘要翻译：公开了在晶体管的应力层中表征机械应力水平的方法和机械应力表征测试结构。在一个实施例中，测试结构包括包括第一应力水平的第一测试晶体管; 以及至少一个具有基本上不同的第二应力水平的第二测试晶体管。然后可以通过比较第一测试晶体管和至少一个第二测试晶体管的性能来测试电路来表征机械应力水平。测试结构的类型取决于所使用的集成方案。在一个实施例中，至少一个第二测试晶体管具有基本上中性的应力水平和/或与第一应力水平相反的应力水平。基本中性的应力水平可以通过旋转晶体管来提供，去除施加应力的应力层，或者使应力层的应力层解除应力层。

20. 发明申请

US20060291866A1 Attenuation and calibration systems and methods for use with a laser detector in an optical communication system 有权
公开(公告)号：US20060291866A1
公开(公告)日：2006-12-28
申请号：US11513874
申请日：2006-08-31
申请人： James Alwan , Paul Binun , Scott Bloom , Victor Chan , Glenn Hoiseth , Hugh O'Brien , Scott Platenberg , Werner Pyka , Raymond Rogers
发明人： James Alwan , Paul Binun , Scott Bloom , Victor Chan , Glenn Hoiseth , Hugh O'Brien , Scott Platenberg , Werner Pyka , Raymond Rogers
IPC分类号： H04B10/00
CPC分类号： H04B10/0799 , H04B10/1123 , H04B10/674
摘要： Systems and methods for use with an optical communication beam are disclosed. The system allows the beam of light to operate at an adequate power level that provides a robust optical link while minimizing any safety risk to humans. The system calibrates and controls the gain for an avalanche photodiode detector (APD). A detector circuit is used to calibrate the APD. Once calibrated, the detector circuit further provides an electrical bias to the APD to process or condition the electrical signal to produce a detector output. The systems and methods disclosed herein attenuate the power level of an incoming communication beam to prevent oversaturation of an APD. The system further provides an alignment signal, which is effective over a wide dynamic range of incoming power levels.

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