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11. 发明专利

JP2012169384A Silicon carbide semiconductor device and method of manufacturing the same 审中-公开
标题翻译：硅碳化硅半导体器件及其制造方法
公开(公告)号：JP2012169384A
公开(公告)日：2012-09-06
申请号：JP2011027995
申请日：2011-02-11
申请人： Denso Corp , Toyota Motor Corp , Toyota Central R&D Labs Inc , トヨタ自動車株式会社 , 株式会社デンソー , 株式会社豊田中央研究所
发明人： YAMAMOTO KENSAKU , NOBORIO MASATO , MATSUKI HIDEO , TAKATANI HIDESHI , SUGIMOTO MASAHIRO , MORIMOTO JUN , SOEJIMA SHIGEMASA , ISHIKAWA TAKESHI , WATANABE YUKIHIKO
IPC分类号： H01L29/78 , H01L21/336 , H01L29/12 , H01L29/739
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/66068 , H01L29/66348 , H01L29/7397
摘要： PROBLEM TO BE SOLVED: To reduce the on-resistance when a deep layer is formed so as to intersect a trench configuring a trench gate structure.SOLUTION: A p-type deep layer 10 has structure where the upper part is narrower than the lower part. For example, the p-type deep layer 10 is constituted by a lower layer region 10a and an upper layer region 10b, and the upper layer region 10b is made narrower than the lower layer region 10a. Consequently, when a channel is formed by applying a gate voltage to a gate electrode 9 during on time on the upper periphery of the p-type deep layer 10, the channel width can be widened. When compared with a case where the width of the p-type deep layer 10 is fixed entirely, i.e. fixed to the same width as that of the lower layer region 10a, a JFET region can be widened and the JFET resistance can be reduced. The on-resistance can thereby be reduced.
摘要翻译：要解决的问题：当形成深层以与构成沟槽栅极结构的沟槽交叉时，降低导通电阻。解决方案：p型深层10具有其上部比下部更窄的结构。例如，p型深层10由下层区域10a和上层区域10b构成，上层区域10b比下层区域10a窄。因此，当在p型深层10的上部周边上的栅极电极9上施加栅极电压而形成沟道时，可以扩大通道宽度。当与p型深层10的宽度完全固定即固定为与下层区域10a的宽度相同的宽度的情况相比，可以加宽JFET区域并且可以减小JFET电阻。因此可以降低导通电阻。版权所有（C）2012，JPO＆INPIT

12. 发明专利

JP2012116732A Method of manufacturing silicon carbide single crystal 有权
标题翻译：制造单晶碳化硅的方法
公开(公告)号：JP2012116732A
公开(公告)日：2012-06-21
申请号：JP2010270295
申请日：2010-12-03
申请人： Denso Corp , Toyota Central R&D Labs Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー , 株式会社豊田中央研究所
发明人： WATANABE HIROKI , KITO YASUO , FURUKAWA TAIJI , YAMAMOTO KENSAKU , TAKATANI HIDESHI , SUGIMOTO MASAHIRO , WATANABE YUKIHIKO , SOEJIMA SHIGEMASA , ISHIKAWA TAKESHI
IPC分类号： C30B29/36 , C30B25/20 , H01L21/205
CPC分类号： H01L21/0262 , C30B25/186 , C30B29/36 , H01L21/02378 , H01L21/0243 , H01L21/02529 , H01L21/02658 , H01L21/046 , H01L21/0475 , H01L29/04
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing an SiC single crystal capable of reducing threading dislocations while suppressing transfer of polymorphism and dislocation without performing sequential lamination of p-layers and n-layers.SOLUTION: A very deep etch pit 1b is formed in the position corresponding to a leak portion by performing molten KOH etching and the like after Al ion implantation and activation annealing, based on findings that a dislocation causing leak such as a drain leak of a vertical MOSFET is a threading screw dislocation. When an SiC growth layer 4 is epitaxially grown on the surface of the etch pit 1b in such a condition that portions grown in the side wall parts of the etch pit 1b are brought into contact mutually, the dislocation is prevented from being transferred to the SiC growth layer 4. In this way, the SiC growth layer 4 having the surface including no threading screw dislocation 1a can be obtained. Therefore, without performing sequential lamination of p-layers and n-layers, the SiC single crystal capable of reducing threading screw dislocations can be produced while suppressing transfer of polymorphism and dislocation.
摘要翻译：要解决的问题：提供一种能够在不进行p层和n层的顺序层压的同时抑制多晶型转移和位错的同时能够减少穿透位错的SiC单晶的制造方法。解决方案：通过在Al离子注入和活化退火之后进行熔融KOH蚀刻等形成在与泄漏部分相对应的位置中的非常深的蚀刻坑1b，基于发现泄漏如泄漏泄漏的位错的垂直MOSFET是螺纹螺钉错位。当在蚀刻凹坑1b的表面上外延生长SiC生长层4，使得在蚀刻坑1b的侧壁部分中生长的部分相互接触的情况下，防止位错转移到SiC 以这种方式，可以获得具有不包括螺纹螺纹位错1a的表面的SiC生长层4。因此，在不进行p层和n层的顺序层叠的情况下，能够抑制多晶型和位错的转移而能够减少螺纹位错的SiC单晶。版权所有（C）2012，JPO＆INPIT

13. 发明专利

JP2012023291A Silicon carbide semiconductor device 有权
标题翻译：硅碳化硅半导体器件
公开(公告)号：JP2012023291A
公开(公告)日：2012-02-02
申请号：JP2010161766
申请日：2010-07-16
申请人： Denso Corp , Toyota Central R&D Labs Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー , 株式会社豊田中央研究所
发明人： MIYAHARA SHINICHIRO , TAKATANI HIDESHI , SUGIMOTO MASAHIRO , MORIMOTO ATSUSHI , WATANABE YUKIHIKO
IPC分类号： H01L29/78 , H01L21/28 , H01L29/12
CPC分类号： H01L29/66068 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/7397 , H01L29/7813 , H01L29/7828
摘要： PROBLEM TO BE SOLVED: To provide a silicon carbide semiconductor device in which contact regions connected to source regions and base regions, can be sufficiently made into contact with a source electrode even when formed finely.SOLUTION: In a silicon carbide semiconductor device, a longitudinal direction of contact holes 12a, that is, a longitudinal direction of contact regions of a source electrode 11 with ntype source regions 4 and ptype body layers 5 is made orthogonal to a longitudinal direction of the ntype source regions 4 and the ptype body layers 5. This allows a contact width of each of the ntype source regions 4 and the ptype body layers 5 to the source electrode 11 to be the same width as the contact holes 12a. This allows the ptype body layers 5 connected to the ntype source regions 4 and ptype base regions 3 to be sufficiently made into contact with the source electrode 11, even when the device is formed finely.
摘要翻译：要解决的问题：为了提供一种碳化硅半导体器件，其中连接到源极区域和基极区域的接触区域即使在精细地形成时也可以充分地与源极电极接触。解决方案：在碳化硅半导体器件中，接触孔12a的纵向方向，即源电极11与n + / SP>型的接触区域的纵向方向源区域4和p + 型体层5与n + 型源区域4的纵向方向正交， p + 类型主体层5.这允许n + 类型源区域4和p中的每一个的联系人宽度将源极电极11的主体层5与接触孔12a的宽度相同的宽度的SP SP =“POST”> + 。这样可以连接到n + 类型源区域4和p + 即使在精细地形成器件时，也可以使“+”/“SP”型基极区域3充分地与源电极11接触。版权所有（C）2012，JPO＆INPIT

14. 发明专利

JP2012004312A Method of manufacturing silicon carbide semiconductor device and silicon carbide semiconductor device 有权
标题翻译：制造碳化硅半导体器件和硅碳化硅半导体器件的方法
公开(公告)号：JP2012004312A
公开(公告)日：2012-01-05
申请号：JP2010137539
申请日：2010-06-16
申请人： Denso Corp , Toyota Central R&D Labs Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー , 株式会社豊田中央研究所
发明人： MATSUKI HIDEO , SUGIMOTO MASAHIRO , TAKATANI HIDESHI , MORIMOTO ATSUSHI , SOEJIMA SHIGEMASA , ISHIKAWA TAKESHI , WATANABE YUKIHIKO
IPC分类号： H01L29/06 , H01L21/336 , H01L29/12 , H01L29/739 , H01L29/78
CPC分类号： H01L29/7813 , H01L29/0615 , H01L29/0619 , H01L29/0638 , H01L29/0661 , H01L29/1608 , H01L29/66068 , H01L29/7811
摘要： PROBLEM TO BE SOLVED: To simplify a manufacturing process by simplifying a step for forming a RESURF layer or an impurity layer constituting an EQR structure.SOLUTION: The surface layer of an n-type drift layer located below a recess 20 in a p-type RESURF layer 21 is connected, by migration of SiC, to a part formed on the surface layer of a p-type base region 3 in the p-type RESURF layer 21. Consequently, the p-type RESURF layer 21 can be connected to the p-type base region 3 without requiring oblique ion implantation even if the side wall of the recess 20 is steep. Since the step for forming the p-type RESURF layer 21 can be simplified, the manufacturing process can be simplified.
摘要翻译：解决的问题：为了简化制造工序，简化形成构成EQR结构的RESURF层或杂质层的工序。解决方案：通过SiC的迁移将位于p型RESURF层21中的凹部20下方的n

15. 发明专利

JP2014135367A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2014135367A
公开(公告)日：2014-07-24
申请号：JP2013002087
申请日：2013-01-09
申请人： Toyota Motor Corp , トヨタ自動車株式会社 , Toyota Central R&D Labs Inc , 株式会社豊田中央研究所
发明人： TAKATANI HIDESHI , NAGAO MASARU , SOEJIMA SHIGEMASA
IPC分类号： H01L29/78
CPC分类号： H01L29/7827 , H01L27/0251 , H01L29/4236 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a technique capable of preventing a gate pad from being damaged when a high voltage is applied to a semiconductor device.SOLUTION: A semiconductor device 10 disclosed herein comprises an element region 12 and a semiconductor substrate 11 having a peripheral region 14 surrounding the element region 12. The element region 12 is provided with an insulated gate type semiconductor element having a gate electrode 16. The peripheral region 14 is provided with a first breakdown voltage holding structure 18 and a second breakdown voltage holding structure 20. The first breakdown voltage holding structure 18 surrounds the element region 12. The second breakdown voltage holding structure 20 is formed at a position which is closer to the first breakdown voltage holding structure 18 than the outer edge of the element region 12 and also closer to the element region 12 than the boundary of the first breakdown voltage holding structure 18 on the side of the element region 12. A gate pad 22 electrically connected to the gate electrode 16 is arranged in a range on the front surface side of the semiconductor substrate 11, where the second breakdown voltage holding structure 20 is formed.
摘要翻译：要解决的问题：提供一种当向半导体器件施加高电压时能够防止栅极焊盘被损坏的技术。解决方案：本文公开的半导体器件10包括元件区域12和具有周边的半导体衬底11 区域14围绕元件区域12.元件区域12设置有具有栅电极16的绝缘栅型半导体元件。外围区域14设置有第一击穿电压保持结构18和第二击穿电压保持结构20。第一击穿电压保持结构18围绕元件区域12.第二击穿电压保持结构20形成在比元件区域12的外边缘更靠近第一击穿电压保持结构18的位置处，并且还更靠近元件区域12比元件reg侧的第一击穿电压保持结构18的边界与栅电极16电连接的栅极焊盘22配置在形成有第二击穿电压保持结构体20的半导体基板11的正面侧的范围内。

16. 发明专利

JP2013069940A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2013069940A
公开(公告)日：2013-04-18
申请号：JP2011208272
申请日：2011-09-24
申请人： Toyota Motor Corp , トヨタ自動車株式会社 , Toyota Central R&D Labs Inc , 株式会社豊田中央研究所 , Denso Corp , 株式会社デンソー
发明人： TAKATANI HIDESHI , MATSUKI HIDEO , MIMURA TOMOHIRO , WATANABE YUKIHIKO , SOEJIMA SHIGEMASA
IPC分类号： H01L29/78 , H01L29/12
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which can inhibit increase in on-resistance of the semiconductor device while maintaining a field relaxation effect by a field buffer layer.SOLUTION: A semiconductor device having a trench gate electrode 13 comprises: a body layer 21 provided in contact with a side wall of the trench gate electrode 13; and a field buffer layer 24 provided in contact with the body layer 21. In this embodiment, a distance between the trench gate electrode 13 and the field buffer layer 24 in a region where a channel formation region is not provided between the trench gate electrode 13 and the field buffer layer 24 is shorter than the distance in a region where a channel formation region is provided between the trench gate electrode 13 and the field buffer layer 24.
摘要翻译：要解决的问题：提供一种可以抑制半导体器件的导通电阻增加同时保持场缓冲层的场弛豫效果的半导体器件。解决方案：具有沟槽栅电极13的半导体器件包括：与沟槽栅电极13的侧壁接触设置的主体层21; 以及设置成与主体层21接触的场缓冲层24.在本实施例中，沟槽栅极电极13和沟道栅极电极13之间的沟道形成区域中没有设置沟道形成区域的区域之间的距离并且场缓冲层24比在沟槽栅电极13和场缓冲层24之间设置沟道形成区域的区域的距离短。（C）2013，JPO和INPIT

17. 发明专利

JP2012216675A Semiconductor device and manufacturing method of the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2012216675A
公开(公告)日：2012-11-08
申请号：JP2011080794
申请日：2011-03-31
申请人： Toyota Motor Corp , Denso Corp , Toyota Central R&D Labs Inc , トヨタ自動車株式会社 , 株式会社デンソー , 株式会社豊田中央研究所
发明人： TAKATANI HIDESHI , MATSUKI HIDEO , SUZUKI MASAHIRO , ISHIKAWA TAKESHI , SOEJIMA SHIGEMASA , WATANABE YUKIHIKO
IPC分类号： H01L29/78 , H01L21/336 , H01L29/12
摘要： PROBLEM TO BE SOLVED: To improve voltage withstanding characteristics of a semiconductor device.SOLUTION: A semiconductor device 100 comprises a semiconductor substrate 102. On the semiconductor substrate, a p-type body region 141 is laminated on a surface of an n-type drift region 112. A trench 113 penetrates a surface of the semiconductor substrate 102 through the body region 141 to reach the drift region 112. A bottom of the trench 113 is coated with an oxide film 171. Lateral walls of the trench 113 are coated with an oxide film 171 and a gate oxide film 172. A top face 171a of the oxide film 171 is located on the lower side than a boundary surface B1 of the drift region 112 and the body region 141. A film thickness of the gate oxide film 172 is assumed to be a first film thickness t1 at least in a partial region on the upper side than the boundary surface B1. The film thickness of the oxide film 171 is made to be thicker than the first film thickness t1 in a region A1 from the top face 171a to the boundary surface B1.
摘要翻译：要解决的问题：提高半导体器件的耐压特性。解决方案：半导体器件100包括半导体衬底102.在半导体衬底上，p型体区141层压在n型漂移区112的表面上。沟槽113穿透半导体衬底102的表面衬底102通过体区141到达漂移区112.沟槽113的底部涂覆有氧化膜171.沟槽113的侧壁涂覆有氧化膜171和栅极氧化膜172。顶部氧化膜171的表面171a位于比漂移区域112和体区141的边界面B1的下侧。栅极氧化膜172的膜厚度假设为至少在在边界面B1上方的局部区域。在从顶面171a到边界面B1的区域A1中，氧化膜171的膜厚比第一膜厚度t1厚。版权所有（C）2013，JPO＆INPIT

18. 发明专利

JP2012169386A Silicon carbide semiconductor device and method of manufacturing the same 有权
标题翻译：硅碳化硅半导体器件及其制造方法
公开(公告)号：JP2012169386A
公开(公告)日：2012-09-06
申请号：JP2011027997
申请日：2011-02-11
申请人： Denso Corp , Toyota Motor Corp , Toyota Central R&D Labs Inc , トヨタ自動車株式会社 , 株式会社デンソー , 株式会社豊田中央研究所
发明人： NOBORIO MASATO , YAMAMOTO KENSAKU , MATSUKI HIDEO , TAKATANI HIDESHI , SUGIMOTO MASAHIRO , SOEJIMA SHIGEMASA , ISHIKAWA TAKESHI , WATANABE YUKIHIKO
IPC分类号： H01L29/78 , H01L21/336 , H01L29/12
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/66068 , H01L29/66348 , H01L29/7397
摘要： PROBLEM TO BE SOLVED: To reduce the on-resistance when a deep layer is formed so as to intersect a trench configuring a trench gate structure.SOLUTION: When a gate voltage is applied to a gate electrode 9 during the on-time while diluting the impurity concentration of a low concentration region 10b in a p-type deep layer 10, an inversion layer is formed at parts located on the side surface and the bottom of a trench 6 in the low concentration region 10b. Consequently, a current flowing through a channel can flow not only a part located between the p-type deep layers 10 out of an n-type drift layer, but also flow through the inversion layer formed in the low concentration region 10b. Consequently, the JFET resistance in a JFET region formed between the adjoining p-type deep layers 10 can be reduced, and thereby the on-resistance can be reduced.
摘要翻译：要解决的问题：当形成深层以与构成沟槽栅极结构的沟槽交叉时，降低导通电阻。解决方案：当在p型深层10中稀释低浓度区域10b的杂质浓度的同时，在导通时间向栅电极9施加栅极电压时，在位于低浓度区域10b中的沟槽6的侧表面和底部。因此，流过通道的电流不仅可以流过位于n - / SP>型漂移层之间的p型深层10之间的部分，而且流过形成在低浓度区域10b中的反型层。因此，可以减小形成在相邻的p型深层10之间的JFET区域中的JFET电阻，从而可以降低导通电阻。版权所有（C）2012，JPO＆INPIT

19. 发明专利

JP2012146921A Silicon carbide semiconductor device 审中-公开
标题翻译：硅碳化硅半导体器件
公开(公告)号：JP2012146921A
公开(公告)日：2012-08-02
申请号：JP2011005970
申请日：2011-01-14
申请人： Denso Corp , Toyota Central R&D Labs Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー , 株式会社豊田中央研究所
发明人： MIYAHARA SHINICHIRO , TAKATANI HIDESHI , SUGIMOTO MASAHIRO , WATANABE YUKIHIKO , SOEJIMA SHIGEMASA , ISHIKAWA TAKESHI
IPC分类号： H01L29/12 , H01L29/78
CPC分类号： H01L21/0475 , H01L29/045 , H01L29/24 , H01L29/42356 , H01L29/66068
摘要： PROBLEM TO BE SOLVED: To prevent the mutual difference in the plane direction of the opposite side walls extending in a direction parallel to the extending direction of a trench.SOLUTION: A trench (2) is extended in the direction in which an interior angle with respect to an off-direction is 30° or -30° in a SiC semiconductor substrate (1) in which an off-angle is provided on a (0001) plane and the off-direction is set to the direction. This prevents the mutual difference in the plane direction of the opposite side walls extending in a direction parallel to the extending direction of the trench (2), so that each of these side walls can substantially be the {11-20} plane.
摘要翻译：要解决的问题：为了防止在与沟槽的延伸方向平行的方向上延伸的相对侧壁的平面方向上的相互差异。解决方案：在提供偏角的SiC半导体衬底（1）中，沟槽（2）沿相对于偏离方向的内角为30°或-30°的方向延伸。在（0001）面上，将偏离方向设定为<11-20>方向。这防止了在与沟槽（2）的延伸方向平行的方向上延伸的相对侧壁的平面方向上的相互差异，使得这些侧壁中的每一个基本上可以是ä11-20}平面。版权所有（C）2012，JPO＆INPIT

20. 发明专利

JP2012064658A Silicon carbide semiconductor device and manufacturing method thereof 有权
标题翻译：硅碳化硅半导体器件及其制造方法
公开(公告)号：JP2012064658A
公开(公告)日：2012-03-29
申请号：JP2010205789
申请日：2010-09-14
申请人： Denso Corp , Toyota Central R&D Labs Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー , 株式会社豊田中央研究所
发明人： YAMAMOTO TOSHIMASA , SUGIMOTO MASAHIRO , TAKATANI HIDESHI , MORIMOTO ATSUSHI , SOEJIMA SHIGEMASA , ISHIKAWA TAKESHI , WATANABE YUKIHIKO
IPC分类号： H01L29/78 , H01L21/28 , H01L21/336 , H01L29/12 , H01L29/739
CPC分类号： H01L29/66068 , H01L29/086 , H01L29/1608 , H01L29/41766 , H01L29/45 , H01L29/7813
摘要： PROBLEM TO BE SOLVED: To suppress increase in contact resistance between a source region and a source electrode when removing a damage in a trench.SOLUTION: In a second region 4b of an ntype source region 4, a place at some depth from a top surface has a relatively low impurity concentration instead of high impurity concentration. With this configuration, even if a portion of relatively low impurity concentration in the second region 4b of the ntype source region 4 remains slightly or disappears through a damage removing step, for enhanced oxidation at the portion of high impurity concentration in the second region 4b, a region which goes through enhanced oxidation decreases because oxidation takes time at the portion of relatively low impurity concentration. Thus, a contact part to a source electrode 9 in the second region 4b of the ntype source region 4 is prevented from disappearing, to suppress increase in contact resistance between the ntype source region 4 and the source electrode 9.
摘要翻译：要解决的问题：为了在消除沟槽中的损坏时抑制源极区域和源极电极之间的接触电阻的增加。解决方案：在n + 型源极区域4的第二区域4b中，距离顶表面某处深度的位置具有相对较低的杂质浓度而不是高杂质浓度。利用这种结构，即使在n + 型源极区域4的第二区域4b中的相对低的杂质浓度的一部分通过损伤去除步骤保持轻微或消失，为了增强在第二区域4b中的高杂质浓度部分处的氧化，经过增强氧化的区域降低，因为在相对低的杂质浓度部分的氧化需要时间。因此，防止在n + 型源极区域4的第二区域4b中的源极电极9的接触部分消失，以抑制n < SP POS =“POST”> + 类型源区域4和源极9.版权所有：（C）2012，JPO＆INPIT

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