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1. 发明专利

JP2015023115A ショットキーダイオードを内蔵するＦＥＴ有权
标题翻译： FET INCORPORATING肖特基二极管
公开(公告)号：JP2015023115A
公开(公告)日：2015-02-02
申请号：JP2013149323
申请日：2013-07-18
申请人：株式会社豊田中央研究所 , Toyota Central R&D Labs Inc , トヨタ自動車株式会社 , Toyota Motor Corp , 株式会社デンソー , Denso Corp
发明人： WATANABE YUKIHIKO , AOI SACHIKO , TAKATANI HIDESHI , AKIBA ATSUYA
IPC分类号： H01L27/04 , H01L21/28 , H01L21/336 , H01L29/12 , H01L29/41 , H01L29/47 , H01L29/78 , H01L29/872
CPC分类号： H01L29/7806 , H01L21/049 , H01L21/0495 , H01L27/0255 , H01L29/0623 , H01L29/0692 , H01L29/1608 , H01L29/42368 , H01L29/66068 , H01L29/66734 , H01L29/7813 , H01L29/872
摘要：【課題】ショットキーダイオードを内蔵しているFETであって、ショットキーダイオードの形成面積とFETの形成面積の比を自由に調整でき、破壊されにくい構造とする。【解決手段】長く延びているトレンチを利用する。トレンチの長さ方向において断続的に出現する位置にショットキー電極を介在させる。SiCに形成される熱酸化膜の成長速度が遅く、ポリシリコンに形成される熱酸化膜の成長速度が速いことを利用すると、ゲート電極とショットキー電極の間、ゲート電極とソース領域の間、ゲート電極とボディ領域の間、ゲート電極とドレイン領域の間には絶縁膜が形成されており、ショットキー電極とドレイン領域の間には絶縁膜が形成されていない構造を得ることができる。【選択図】図1
摘要翻译：要解决的问题：提供一种结合了肖特基二极管并且具有不太可能被破坏的结构的FET，其中肖特基二极管的形成面积与FET的形成面积的比率可以自由调节。解决方案：使用延长沟槽。肖特基电极插入在沟槽的长度方向上间断地出现的位置处。通过使用在SiC上形成的热氧化膜的生长速度慢，并且在多晶硅上形成的热氧化膜的生长速度快的事实，可以在栅电极和肖特基电极，栅电极和源极区之间，栅电极与体区之间以及栅电极和漏区之间的肖特基电极，但是在肖特基电极和漏极区之间不形成绝缘膜。

2. 发明专利

JP2012234908A Silicon carbide semiconductor device 有权
标题翻译：硅碳化硅半导体器件
公开(公告)号：JP2012234908A
公开(公告)日：2012-11-29
申请号：JP2011101207
申请日：2011-04-28
申请人： Denso Corp , 株式会社デンソー , Toyota Motor Corp , トヨタ自動車株式会社 , Toyota Central R&D Labs Inc , 株式会社豊田中央研究所
发明人： WATANABE HIROKI , MIYAHARA SHINICHIRO , TAKATANI HIDESHI , SUGIMOTO MASAHIRO , WATANABE YUKIHIKO , SOEJIMA SHIGEMASA , ISHIKAWA TAKESHI
IPC分类号： H01L29/12 , H01L29/78
CPC分类号： H01L29/7813 , H01L29/045 , H01L29/0634 , H01L29/1095 , H01L29/1608 , H01L29/66068 , H01L29/7397
摘要： PROBLEM TO BE SOLVED: To minimize decline of the isolation voltage and the life of a gate insulating film, by suppressing unevenness of the side surface and the bottom surface of a trench.SOLUTION: A trench 6 is formed so as to have the direction perpendicular to the direction, i.e. the off direction of an SiC semiconductor substrate, as the longitudinal direction. Since a step bunching SB does not traverse the trench 6, formation of unevenness on the side surface and the bottom surface of the trench 6 due to the step bunching SB can be substantially prevented. Consequently, a gate oxide film 8 is formed on the side surface and the bottom surface of the trench 6 having no unevenness, and decline of the isolation voltage and the life of the gate oxide film 8 can be minimized.
摘要翻译：要解决的问题：通过抑制沟槽的侧表面和底表面的不均匀性来最小化隔离电压的下降和栅极绝缘膜的寿命。解决方案：形成沟槽6，使其具有与<11-20>方向垂直的<1-100>方向，即SiC半导体衬底的关闭方向作为纵向方向。由于台阶聚束SB不穿过沟槽6，所以可以基本上防止由于台阶聚束SB而在沟槽6的侧面和底面上形成凹凸。因此，在不具有不均匀性的沟槽6的侧面和底面上形成栅氧化膜8，能够使隔离电压下降和栅极氧化膜8的使用寿命最小化。版权所有（C）2013，JPO＆INPIT

3. 发明专利

JP2012169385A Silicon carbide semiconductor device 审中-公开
标题翻译：硅碳化硅半导体器件
公开(公告)号：JP2012169385A
公开(公告)日：2012-09-06
申请号：JP2011027996
申请日：2011-02-11
申请人： Denso Corp , Toyota Motor Corp , Toyota Central R&D Labs Inc , トヨタ自動車株式会社 , 株式会社デンソー , 株式会社豊田中央研究所
发明人： MATSUKI HIDEO , YAMAMOTO KENSAKU , NOBORIO MASATO , SUZUKI MASAHIRO , TAKATANI HIDESHI , SUGIMOTO MASAHIRO , MORIMOTO JUN , SOEJIMA SHIGEMASA , ISHIKAWA TAKESHI , WATANABE YUKIHIKO
IPC分类号： H01L29/78 , H01L21/336 , H01L29/12 , H01L29/739
CPC分类号： H01L29/66068 , H01L29/0634 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/7397 , H01L29/7813
摘要： PROBLEM TO BE SOLVED: To reduce the on-resistance when a deep layer is formed so as to intersect a trench configuring a trench gate structure.SOLUTION: The structure where a p-type deep layer 10 is separated entirely or partially from the inner wall surface of a trench 6, i.e. a layout where the p-type deep layer 10 is not in contact with any one of the side surface or the bottom face of the trench 6, is employed. For example, the p-type deep layer 10 is formed only in a place separated from a trench gate structure, so as not to come into contact with both the side surface and the bottom face of the trench gate structure. Consequently, the channel width can be widened when a channel is formed by applying a gate voltage to a gate electrode 9 during the on-time. When compared with a case where the p-type deep layer 10 is formed so as to come into contact with the trench 6, width of a JFET region can be widened and since the JFET resistance can be reduced, the on-resistance can be reduced.
摘要翻译：要解决的问题：当形成深层以与构成沟槽栅极结构的沟槽交叉时，降低导通电阻。解决方案：p型深层10完全或部分地从沟槽6的内壁表面分离的结构，即p型深层10不与任何一种使用沟槽6的侧表面或底面。例如，p型深层10仅形成在与沟槽栅极结构分离的位置，以便不与沟槽栅极结构的侧面和底面接触。因此，通过在导通时间对栅电极9施加栅极电压来形成通道时，可以扩大通道宽度。当与形成p型深层10以与沟槽6接触的情况相比较，可以扩大JFET区域的宽度，并且由于可以减小JFET电阻，可以降低导通电阻。版权所有（C）2012，JPO＆INPIT

4. 发明专利

JP2012134376A Silicon carbide semiconductor device and method of manufacturing the same 有权
标题翻译：硅碳化硅半导体器件及其制造方法
公开(公告)号：JP2012134376A
公开(公告)日：2012-07-12
申请号：JP2010286101
申请日：2010-12-22
申请人： Denso Corp , Toyota Central R&D Labs Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー , 株式会社豊田中央研究所
发明人： MIMURA TOMOHIRO , MIYAHARA SHINICHIRO , TAKATANI HIDESHI , SUGIMOTO MASAHIRO , SOEJIMA SHIGEMASA , ISHIKAWA TAKESHI , WATANABE YUKIHIKO
IPC分类号： H01L29/78 , H01L21/336 , H01L29/12 , H01L29/739
CPC分类号： H01L29/66068 , H01L29/045 , H01L29/1608 , H01L29/4236 , H01L29/42368 , H01L29/7397 , H01L29/7813
摘要： PROBLEM TO BE SOLVED: To widen a process window and obtain the reliability of a gate oxide film while ensuring high channel mobility, when forming a trench gate structure.SOLUTION: An n-type substrate 1 having a Si plane as a primary surface is used, and a trench 6 for forming a trench gate structure is formed in a reverse taper shape. For this reason, since the sidewalls of the trench 6 have the same state as that of a trench in a taper shape when a C plane is used as the primary surface, the reduction in channel mobility can be lowered even if variation in the sidewall angle of the trench 6 occurs. Consequently, high channel mobility can be obtained. Besides, because the bottom surface of the trench 6 and surfaces of the outside (an n-type source region 4 and a ptype contact layer 5) of the trench 6 are the Si planes, a gate oxide film 7 becomes a high-reliability film that can suppress degradation.
摘要翻译：要解决的问题：当形成沟槽栅极结构时，拓宽工艺窗口并获得栅极氧化膜的可靠性，同时确保高沟道迁移率。
解决方案：使用具有Si平面作为主表面的n + 型衬底1，并且形成沟槽栅极结构的沟槽6以相反的方式形成锥形。因此，由于当使用C面作为主表面时，由于沟槽6的侧壁具有与锥形形状的沟槽相同的状态，所以即使侧壁角度的变化也能够降低沟道迁移率发生沟槽6。因此，可以获得高通道迁移率。此外，由于沟槽6的底面和外表面（n + 型源区4和ap + SP >型接触层5）是Si平面，栅极氧化膜7成为可以抑制劣化的高可靠性膜。版权所有（C）2012，JPO＆INPIT

5. 发明专利

JP2012009502A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2012009502A
公开(公告)日：2012-01-12
申请号：JP2010141744
申请日：2010-06-22
申请人： Denso Corp , Toyota Central R&D Labs Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー , 株式会社豊田中央研究所
发明人： YAMAMOTO KENSAKU , SUZUKI MASAHIRO , TAKATANI HIDESHI , SUGIMOTO MASAHIRO , MORIMOTO ATSUSHI , SOEJIMA SHIGEMASA , ISHIKAWA TAKESHI , WATANABE YUKIHIKO
IPC分类号： H01L29/78 , H01L29/06 , H01L29/12
CPC分类号： H01L29/7811 , H01L29/0619 , H01L29/0661 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/407 , H01L29/66068 , H01L29/7397 , H01L29/7813 , H01L29/8613
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which enhances breakdown voltage by resolving occurence of discontinuity of material at an area contacting an electric field relaxation layer and omitting bent portions from the electric field relaxation layer.SOLUTION: The semiconductor device includes an electric field relaxation layer 3a for providing a peripheral breakdown voltage structure by using a p-type base layer 3. Accordingly, bent portions can be omitted from the electric field relaxation layer 3a. Since only an n-type drift layer 2a is a semiconductor which the electric field relaxation layer 3a is in contact with, discontinuity of materials does not occur. Consequently, breakdown voltage of an SiC semiconductor device can be enhanced.
摘要翻译：解决的问题：提供一种半导体器件，其通过解决在与电场弛豫层接触的区域处的材料不连续的发生并且从电场弛豫层省略弯曲部分来提高击穿电压。解决方案：半导体器件包括用于通过使用p型基极层3提供外围击穿电压结构的电场弛豫层3a。因此，可以从电场弛豫层3a省略弯曲部分。由于只有n

6. 发明专利

JP2011216783A Semiconductor device and method of manufacturing semiconductor device 有权
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：JP2011216783A
公开(公告)日：2011-10-27
申请号：JP2010085438
申请日：2010-04-01
申请人： Denso Corp , Toyota Central R&D Labs Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー , 株式会社豊田中央研究所
发明人： TAKATANI HIDESHI , MATSUKI HIDEO , SUZUKI MASAHIRO , ISHIKAWA TAKESHI
IPC分类号： H01L29/78 , H01L21/336 , H01L29/12
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having a structure such that a trench gate insulating film is not broken by an applied electric field without increasing the on resistance.SOLUTION: The semiconductor device includes a first semiconductor layer 12a of a first conductivity type formed on a semiconductor substrate 16, a second semiconductor layer 12b of the first conductivity type formed in a partial region on the first semiconductor layer, a third semiconductor layer 13 of a second conductivity type formed on the first semiconductor layer and second semiconductor layer, a trench having a bottom at the second semiconductor layer, a fourth semiconductor layer 17 of a first conductivity type formed on both sides of the trench, a gate insulating film 14 formed in the trench, and a gate electrode 15, wherein the gate insulating film is formed having a thicker film thickness on the bottom of the trench than that on a side face of the trench, and a depth-directional interface between the gate insulating film and gate electrode on the bottom of the trench is formed at a position deeper than a depth-directional interface between the second semiconductor layer and third semiconductor layer.
摘要翻译：要解决的问题：提供一种半导体器件，其具有这样的结构，使得沟槽栅极绝缘膜在不增加导通电阻的情况下不受施加的电场的破坏。解决方案：半导体器件包括第一导电类型的第一半导体层12a 形成在半导体基板16上，形成在第一半导体层上的部分区域中的第一导电类型的第二半导体层12b，形成在第一半导体层和第二半导体层上的第二导电类型的第三半导体层13，在第二半导体层具有底部的沟槽，形成在沟槽的两侧的第一导电类型的第四半导体层17，形成在沟槽中的栅极绝缘膜14和栅极电极15，其中栅极绝缘膜为在沟槽的底部形成的厚度比沟槽的侧面上的膜厚更深，并具有深度方向的相互之间沟槽底部的栅极绝缘膜与栅电极之间的面形成在比第二半导体层与第三半导体层之间的深度方向界面更深的位置。

7. 发明专利

JP2013012590A Silicon carbide semiconductor device 有权
标题翻译：硅碳化硅半导体器件
公开(公告)号：JP2013012590A
公开(公告)日：2013-01-17
申请号：JP2011144320
申请日：2011-06-29
申请人： Denso Corp , 株式会社デンソー , Toyota Motor Corp , トヨタ自動車株式会社 , Toyota Central R&D Labs Inc , 株式会社豊田中央研究所
发明人： MIYAHARA SHINICHIRO , TAKATANI HIDESHI , SUGIMOTO MASAHIRO , WATANABE YUKIHIKO , SOEJIMA SHIGEMASA , ISHIKAWA TAKESHI
IPC分类号： H01L29/78 , H01L21/336 , H01L29/12
CPC分类号： H01L29/7813 , H01L29/045 , H01L29/0865 , H01L29/1095 , H01L29/1608 , H01L29/4236 , H01L29/66068 , H01L29/7825 , H01L29/7827
摘要： PROBLEM TO BE SOLVED: To obtain a high channel mobility by bringing the side surface of a trench, in which a channel is formed, close to the (11-20) plane or the (1-100) plane capable of increasing the channel mobility.SOLUTION: An nsource region 5 is formed so as to come into contact with one side surface out of both side surfaces of a trench 7, i.e. the side surface which forms an angle of 90° or an angle close to it with respect to the (0001) plane, so that a channel is formed in only one of both side surfaces of the trench 7. Since the channel can be formed only in the side surface where a high channel mobility is formed out of both side surfaces of the trench 7, a high channel mobility can be obtained.
摘要翻译：要解决的问题：为了通过使形成沟道的沟槽的侧表面靠近能够增加的（11-20）面或（1-100）面来获得高沟道迁移率渠道流动性。源极区域5形成为与沟槽7的两个侧表面中的一个侧表面接触，即侧表面相对于（0001）面形成90°的角度或与其接近的角度，使得沟槽仅形成在沟槽7的两个侧表面中的一个中。由于沟道仅可以形成在侧表面其中在沟槽7的两个侧表面形成高沟道迁移率，可以获得高沟道迁移率。版权所有（C）2013，JPO＆INPIT

8. 发明专利

JP2012169384A Silicon carbide semiconductor device and method of manufacturing the same 审中-公开
标题翻译：硅碳化硅半导体器件及其制造方法
公开(公告)号：JP2012169384A
公开(公告)日：2012-09-06
申请号：JP2011027995
申请日：2011-02-11
申请人： Denso Corp , Toyota Motor Corp , Toyota Central R&D Labs Inc , トヨタ自動車株式会社 , 株式会社デンソー , 株式会社豊田中央研究所
发明人： YAMAMOTO KENSAKU , NOBORIO MASATO , MATSUKI HIDEO , TAKATANI HIDESHI , SUGIMOTO MASAHIRO , MORIMOTO JUN , SOEJIMA SHIGEMASA , ISHIKAWA TAKESHI , WATANABE YUKIHIKO
IPC分类号： H01L29/78 , H01L21/336 , H01L29/12 , H01L29/739
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/66068 , H01L29/66348 , H01L29/7397
摘要： PROBLEM TO BE SOLVED: To reduce the on-resistance when a deep layer is formed so as to intersect a trench configuring a trench gate structure.SOLUTION: A p-type deep layer 10 has structure where the upper part is narrower than the lower part. For example, the p-type deep layer 10 is constituted by a lower layer region 10a and an upper layer region 10b, and the upper layer region 10b is made narrower than the lower layer region 10a. Consequently, when a channel is formed by applying a gate voltage to a gate electrode 9 during on time on the upper periphery of the p-type deep layer 10, the channel width can be widened. When compared with a case where the width of the p-type deep layer 10 is fixed entirely, i.e. fixed to the same width as that of the lower layer region 10a, a JFET region can be widened and the JFET resistance can be reduced. The on-resistance can thereby be reduced.
摘要翻译：要解决的问题：当形成深层以与构成沟槽栅极结构的沟槽交叉时，降低导通电阻。解决方案：p型深层10具有其上部比下部更窄的结构。例如，p型深层10由下层区域10a和上层区域10b构成，上层区域10b比下层区域10a窄。因此，当在p型深层10的上部周边上的栅极电极9上施加栅极电压而形成沟道时，可以扩大通道宽度。当与p型深层10的宽度完全固定即固定为与下层区域10a的宽度相同的宽度的情况相比，可以加宽JFET区域并且可以减小JFET电阻。因此可以降低导通电阻。版权所有（C）2012，JPO＆INPIT

9. 发明专利

JP2012116732A Method of manufacturing silicon carbide single crystal 有权
标题翻译：制造单晶碳化硅的方法
公开(公告)号：JP2012116732A
公开(公告)日：2012-06-21
申请号：JP2010270295
申请日：2010-12-03
申请人： Denso Corp , Toyota Central R&D Labs Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー , 株式会社豊田中央研究所
发明人： WATANABE HIROKI , KITO YASUO , FURUKAWA TAIJI , YAMAMOTO KENSAKU , TAKATANI HIDESHI , SUGIMOTO MASAHIRO , WATANABE YUKIHIKO , SOEJIMA SHIGEMASA , ISHIKAWA TAKESHI
IPC分类号： C30B29/36 , C30B25/20 , H01L21/205
CPC分类号： H01L21/0262 , C30B25/186 , C30B29/36 , H01L21/02378 , H01L21/0243 , H01L21/02529 , H01L21/02658 , H01L21/046 , H01L21/0475 , H01L29/04
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing an SiC single crystal capable of reducing threading dislocations while suppressing transfer of polymorphism and dislocation without performing sequential lamination of p-layers and n-layers.SOLUTION: A very deep etch pit 1b is formed in the position corresponding to a leak portion by performing molten KOH etching and the like after Al ion implantation and activation annealing, based on findings that a dislocation causing leak such as a drain leak of a vertical MOSFET is a threading screw dislocation. When an SiC growth layer 4 is epitaxially grown on the surface of the etch pit 1b in such a condition that portions grown in the side wall parts of the etch pit 1b are brought into contact mutually, the dislocation is prevented from being transferred to the SiC growth layer 4. In this way, the SiC growth layer 4 having the surface including no threading screw dislocation 1a can be obtained. Therefore, without performing sequential lamination of p-layers and n-layers, the SiC single crystal capable of reducing threading screw dislocations can be produced while suppressing transfer of polymorphism and dislocation.
摘要翻译：要解决的问题：提供一种能够在不进行p层和n层的顺序层压的同时抑制多晶型转移和位错的同时能够减少穿透位错的SiC单晶的制造方法。解决方案：通过在Al离子注入和活化退火之后进行熔融KOH蚀刻等形成在与泄漏部分相对应的位置中的非常深的蚀刻坑1b，基于发现泄漏如泄漏泄漏的位错的垂直MOSFET是螺纹螺钉错位。当在蚀刻凹坑1b的表面上外延生长SiC生长层4，使得在蚀刻坑1b的侧壁部分中生长的部分相互接触的情况下，防止位错转移到SiC 以这种方式，可以获得具有不包括螺纹螺纹位错1a的表面的SiC生长层4。因此，在不进行p层和n层的顺序层叠的情况下，能够抑制多晶型和位错的转移而能够减少螺纹位错的SiC单晶。版权所有（C）2012，JPO＆INPIT

10. 发明专利

JP2012023291A Silicon carbide semiconductor device 有权
标题翻译：硅碳化硅半导体器件
公开(公告)号：JP2012023291A
公开(公告)日：2012-02-02
申请号：JP2010161766
申请日：2010-07-16
申请人： Denso Corp , Toyota Central R&D Labs Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー , 株式会社豊田中央研究所
发明人： MIYAHARA SHINICHIRO , TAKATANI HIDESHI , SUGIMOTO MASAHIRO , MORIMOTO ATSUSHI , WATANABE YUKIHIKO
IPC分类号： H01L29/78 , H01L21/28 , H01L29/12
CPC分类号： H01L29/66068 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/7397 , H01L29/7813 , H01L29/7828
摘要： PROBLEM TO BE SOLVED: To provide a silicon carbide semiconductor device in which contact regions connected to source regions and base regions, can be sufficiently made into contact with a source electrode even when formed finely.SOLUTION: In a silicon carbide semiconductor device, a longitudinal direction of contact holes 12a, that is, a longitudinal direction of contact regions of a source electrode 11 with ntype source regions 4 and ptype body layers 5 is made orthogonal to a longitudinal direction of the ntype source regions 4 and the ptype body layers 5. This allows a contact width of each of the ntype source regions 4 and the ptype body layers 5 to the source electrode 11 to be the same width as the contact holes 12a. This allows the ptype body layers 5 connected to the ntype source regions 4 and ptype base regions 3 to be sufficiently made into contact with the source electrode 11, even when the device is formed finely.
摘要翻译：要解决的问题：为了提供一种碳化硅半导体器件，其中连接到源极区域和基极区域的接触区域即使在精细地形成时也可以充分地与源极电极接触。解决方案：在碳化硅半导体器件中，接触孔12a的纵向方向，即源电极11与n + / SP>型的接触区域的纵向方向源区域4和p + 型体层5与n + 型源区域4的纵向方向正交， p + 类型主体层5.这允许n + 类型源区域4和p中的每一个的联系人宽度将源极电极11的主体层5与接触孔12a的宽度相同的宽度的SP SP =“POST”> + 。这样可以连接到n + 类型源区域4和p + 即使在精细地形成器件时，也可以使“+”/“SP”型基极区域3充分地与源电极11接触。版权所有（C）2012，JPO＆INPIT

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