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1. 发明专利

JP2011113997A Semiconductor device, and method for manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2011113997A
公开(公告)日：2011-06-09
申请号：JP2009266021
申请日：2009-11-24
申请人： Denso Corp , Toyota Central R&D Labs Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー , 株式会社豊田中央研究所
发明人： KATSUNO TAKASHI , WATANABE YUKIHIKO , SOEJIMA SHIGEMASA , YAMAMOTO TAKEO , ENDO TAKESHI , FUJIWARA HIROKAZU , KONISHI MASAKI
IPC分类号： H01L29/41 , H01L21/28 , H01L21/329 , H01L21/336 , H01L29/12 , H01L29/417 , H01L29/47 , H01L29/78 , H01L29/861 , H01L29/872
CPC分类号： H01L29/872
摘要： PROBLEM TO BE SOLVED: To provide a technology for manufacturing a semiconductor element that forms multiple trenches for forming electrodes on a back-surface layer of a silicon carbide substrate inexpensively.
SOLUTION: Multiple etch pits 24 are formed by wet etching in response to parts where displacement exist on a back-surface layer of the silicon carbide substrate 13. A cathode electrode 32 that ohmicly contacts with the silicon carbide substrate is formed by a sputtering method. Multiple p-layers 16 are formed on a front-surface layer of the silicon carbide substrate 13 and then an anode electrode 34 is formed by a sputtering method. Thus, a junction barrier Schottky diode is formed.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：解决的问题：提供一种用于制造半导体元件的技术，该半导体元件形成用于在碳化硅衬底的背表面层上形成电极的多个沟槽。解决方案：响应于在碳化硅衬底13的背面层上存在位移的部分，通过湿蚀刻形成多个蚀刻凹坑24.与碳化硅衬底欧姆接触的阴极32形成为溅射法。在碳化硅衬底13的前表面层上形成多个p层16，然后通过溅射法形成阳极34。因此，形成结屏障肖特基二极管。版权所有（C）2011，JPO＆INPIT

2. 发明专利

JP2012234908A Silicon carbide semiconductor device 有权
标题翻译：硅碳化硅半导体器件
公开(公告)号：JP2012234908A
公开(公告)日：2012-11-29
申请号：JP2011101207
申请日：2011-04-28
申请人： Denso Corp , 株式会社デンソー , Toyota Motor Corp , トヨタ自動車株式会社 , Toyota Central R&D Labs Inc , 株式会社豊田中央研究所
发明人： WATANABE HIROKI , MIYAHARA SHINICHIRO , TAKATANI HIDESHI , SUGIMOTO MASAHIRO , WATANABE YUKIHIKO , SOEJIMA SHIGEMASA , ISHIKAWA TAKESHI
IPC分类号： H01L29/12 , H01L29/78
CPC分类号： H01L29/7813 , H01L29/045 , H01L29/0634 , H01L29/1095 , H01L29/1608 , H01L29/66068 , H01L29/7397
摘要： PROBLEM TO BE SOLVED: To minimize decline of the isolation voltage and the life of a gate insulating film, by suppressing unevenness of the side surface and the bottom surface of a trench.SOLUTION: A trench 6 is formed so as to have the direction perpendicular to the direction, i.e. the off direction of an SiC semiconductor substrate, as the longitudinal direction. Since a step bunching SB does not traverse the trench 6, formation of unevenness on the side surface and the bottom surface of the trench 6 due to the step bunching SB can be substantially prevented. Consequently, a gate oxide film 8 is formed on the side surface and the bottom surface of the trench 6 having no unevenness, and decline of the isolation voltage and the life of the gate oxide film 8 can be minimized.
摘要翻译：要解决的问题：通过抑制沟槽的侧表面和底表面的不均匀性来最小化隔离电压的下降和栅极绝缘膜的寿命。解决方案：形成沟槽6，使其具有与<11-20>方向垂直的<1-100>方向，即SiC半导体衬底的关闭方向作为纵向方向。由于台阶聚束SB不穿过沟槽6，所以可以基本上防止由于台阶聚束SB而在沟槽6的侧面和底面上形成凹凸。因此，在不具有不均匀性的沟槽6的侧面和底面上形成栅氧化膜8，能够使隔离电压下降和栅极氧化膜8的使用寿命最小化。版权所有（C）2013，JPO＆INPIT

3. 发明专利

JP2012069798A Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2012069798A
公开(公告)日：2012-04-05
申请号：JP2010214245
申请日：2010-09-24
申请人： Denso Corp , Toyota Central R&D Labs Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー , 株式会社豊田中央研究所
发明人： FUJIWARA HIROKAZU , KONISHI MASAKI , MORIMOTO ATSUSHI , KATSUNO TAKASHI , WATANABE YUKIHIKO , SOEJIMA SHIGEMASA , KAWAI JUN , ENDO TAKESHI , YAMAMOTO TAKEO
IPC分类号： H01L21/28
CPC分类号： H01L29/872 , H01L23/3192 , H01L2224/05567 , H01L2224/06181 , H01L2924/00014 , H01L2924/12032 , H01L2924/00 , H01L2224/05552
摘要： PROBLEM TO BE SOLVED: To provide a technique capable of forming an excellent ohmic electrode in an atmosphere other than a non-oxidative atmosphere.SOLUTION: A method of manufacturing a semiconductor device having an ohmic electrode comprises the steps of: forming a metal layer 30e on a semiconductor substrate 50; forming a transmission film 30f on the metal layer 30e; heating the metal layer 30e by irradiating the metal layer 30e with an electromagnetic wave through the transmission film 30f; and removing the transmission film 30f.
摘要翻译：解决的问题：提供能够在非氧化性气氛以外的气氛中形成优异的欧姆电极的技术。解决方案：制造具有欧姆电极的半导体器件的方法包括以下步骤：在半导体衬底50上形成金属层30e; 在金属层30e上形成透射膜30f; 通过透过薄膜30f用电磁波照射金属层30e来加热金属层30e; 并移除透射膜30f。版权所有（C）2012，JPO＆INPIT

4. 发明专利

JP2011100948A Semiconductor device, and method for manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2011100948A
公开(公告)日：2011-05-19
申请号：JP2009256438
申请日：2009-11-09
申请人： Denso Corp , Toyota Central R&D Labs Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー , 株式会社豊田中央研究所
发明人： WATANABE YUKIHIKO , KATSUNO TAKASHI , SOEJIMA SHIGEMASA , YAMAMOTO TAKEO , ENDO TAKESHI , FUJIWARA HIROKAZU , KONISHI MASAKI
IPC分类号： H01L29/47 , H01L29/861 , H01L29/872
CPC分类号： H01L29/872
摘要： PROBLEM TO BE SOLVED: To decrease a heat damage caused by annealing when the annealing is performed to a back electrode.
SOLUTION: A semiconductor device includes: a silicon carbide substrate 10 where a vertical short key diode is formed; an anode electrode 20 that is provided on a front surface of the silicon carbide substrate 10; a cathode electrode 50 that is provided on a back surface of the silicon carbide substrate 10; and a conductive adiabatic region 40 that is provided between the silicon carbide substrate 10 and the cathode electrode 50. The adiabatic region 40 has heat conductivity smaller than that of a semiconductor material of the silicon carbide substrate 10.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：当对后电极进行退火时，减少由退火引起的热损伤。解决方案：半导体器件包括：形成垂直短路二极管的碳化硅衬底10; 设置在碳化硅衬底10的前表面上的阳极电极20; 设置在碳化硅衬底10的背面上的阴极50; 以及设置在碳化硅衬底10和阴极电极50之间的导电绝热区域40.绝热区域40的导热系数小于碳化硅衬底10的半导体材料的热导率。（C） 2011年，JPO＆INPIT

5. 发明专利

JP2014053595A Silicon carbide semiconductor device and manufacturing method of the same 有权
标题翻译：硅碳化硅半导体器件及其制造方法
公开(公告)号：JP2014053595A
公开(公告)日：2014-03-20
申请号：JP2013156393
申请日：2013-07-29
申请人： Denso Corp , 株式会社デンソー , Toyota Motor Corp , トヨタ自動車株式会社 , Toyota Central R&D Labs Inc , 株式会社豊田中央研究所
发明人： MIYAHARA SHINICHIRO , YAMAMOTO TOSHIMASA , MORIMOTO JUN , SOEJIMA SHIGEMASA , WATANABE YUKIHIKO
IPC分类号： H01L29/78 , H01L21/316 , H01L21/336 , H01L29/12
CPC分类号： H01L29/66734 , H01L21/049 , H01L21/28158 , H01L21/30604 , H01L29/045 , H01L29/1095 , H01L29/1608 , H01L29/4236 , H01L29/4238 , H01L29/66068 , H01L29/7397 , H01L29/7813
摘要： PROBLEM TO BE SOLVED: To inhibit the occurrence of leakage current to achieve an SiC semiconductor device with a gate oxide film having higher reliability.SOLUTION: In composition of a vertical MOSFET having a trench gate structure 9 by using an ntype substrate 1 and the like having an off angle to a (0001) plane or a (000-1) plane, a gate oxide film 7 is formed after forming a trench 6 without performing a sacrificial oxidation process. By doing this, the vertical MOSFET needs not be influenced by the sacrificial oxidation process and can inhibit the partial occurrence of leakage current in the trench gate structure 9 thereby to enable achievement of an SiC semiconductor device with a gate oxide film 7 having higher reliability.
摘要翻译：要解决的问题：为了抑制漏电流的发生，实现具有较高可靠性的栅极氧化膜的SiC半导体器件。解决方案：通过使用n型衬底1等具有沟槽栅极结构9的垂直MOSFET的组成与（0001）面或（000-1）面成偏角时，在不进行牺牲氧化处理的状态下，在形成沟槽6之后形成栅极氧化膜7。通过这样做，垂直MOSFET不需要受牺牲氧化处理的影响，并且可以抑制沟槽栅极结构9中的部分泄漏电流的发生，从而能够实现具有更高可靠性的栅极氧化膜7的SiC半导体器件。

6. 发明专利

JP2013012590A Silicon carbide semiconductor device 有权
标题翻译：硅碳化硅半导体器件
公开(公告)号：JP2013012590A
公开(公告)日：2013-01-17
申请号：JP2011144320
申请日：2011-06-29
申请人： Denso Corp , 株式会社デンソー , Toyota Motor Corp , トヨタ自動車株式会社 , Toyota Central R&D Labs Inc , 株式会社豊田中央研究所
发明人： MIYAHARA SHINICHIRO , TAKATANI HIDESHI , SUGIMOTO MASAHIRO , WATANABE YUKIHIKO , SOEJIMA SHIGEMASA , ISHIKAWA TAKESHI
IPC分类号： H01L29/78 , H01L21/336 , H01L29/12
CPC分类号： H01L29/7813 , H01L29/045 , H01L29/0865 , H01L29/1095 , H01L29/1608 , H01L29/4236 , H01L29/66068 , H01L29/7825 , H01L29/7827
摘要： PROBLEM TO BE SOLVED: To obtain a high channel mobility by bringing the side surface of a trench, in which a channel is formed, close to the (11-20) plane or the (1-100) plane capable of increasing the channel mobility.SOLUTION: An nsource region 5 is formed so as to come into contact with one side surface out of both side surfaces of a trench 7, i.e. the side surface which forms an angle of 90° or an angle close to it with respect to the (0001) plane, so that a channel is formed in only one of both side surfaces of the trench 7. Since the channel can be formed only in the side surface where a high channel mobility is formed out of both side surfaces of the trench 7, a high channel mobility can be obtained.
摘要翻译：要解决的问题：为了通过使形成沟道的沟槽的侧表面靠近能够增加的（11-20）面或（1-100）面来获得高沟道迁移率渠道流动性。源极区域5形成为与沟槽7的两个侧表面中的一个侧表面接触，即侧表面相对于（0001）面形成90°的角度或与其接近的角度，使得沟槽仅形成在沟槽7的两个侧表面中的一个中。由于沟道仅可以形成在侧表面其中在沟槽7的两个侧表面形成高沟道迁移率，可以获得高沟道迁移率。版权所有（C）2013，JPO＆INPIT

7. 发明专利

JP2012169384A Silicon carbide semiconductor device and method of manufacturing the same 审中-公开
标题翻译：硅碳化硅半导体器件及其制造方法
公开(公告)号：JP2012169384A
公开(公告)日：2012-09-06
申请号：JP2011027995
申请日：2011-02-11
申请人： Denso Corp , Toyota Motor Corp , Toyota Central R&D Labs Inc , トヨタ自動車株式会社 , 株式会社デンソー , 株式会社豊田中央研究所
发明人： YAMAMOTO KENSAKU , NOBORIO MASATO , MATSUKI HIDEO , TAKATANI HIDESHI , SUGIMOTO MASAHIRO , MORIMOTO JUN , SOEJIMA SHIGEMASA , ISHIKAWA TAKESHI , WATANABE YUKIHIKO
IPC分类号： H01L29/78 , H01L21/336 , H01L29/12 , H01L29/739
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/66068 , H01L29/66348 , H01L29/7397
摘要： PROBLEM TO BE SOLVED: To reduce the on-resistance when a deep layer is formed so as to intersect a trench configuring a trench gate structure.SOLUTION: A p-type deep layer 10 has structure where the upper part is narrower than the lower part. For example, the p-type deep layer 10 is constituted by a lower layer region 10a and an upper layer region 10b, and the upper layer region 10b is made narrower than the lower layer region 10a. Consequently, when a channel is formed by applying a gate voltage to a gate electrode 9 during on time on the upper periphery of the p-type deep layer 10, the channel width can be widened. When compared with a case where the width of the p-type deep layer 10 is fixed entirely, i.e. fixed to the same width as that of the lower layer region 10a, a JFET region can be widened and the JFET resistance can be reduced. The on-resistance can thereby be reduced.
摘要翻译：要解决的问题：当形成深层以与构成沟槽栅极结构的沟槽交叉时，降低导通电阻。解决方案：p型深层10具有其上部比下部更窄的结构。例如，p型深层10由下层区域10a和上层区域10b构成，上层区域10b比下层区域10a窄。因此，当在p型深层10的上部周边上的栅极电极9上施加栅极电压而形成沟道时，可以扩大通道宽度。当与p型深层10的宽度完全固定即固定为与下层区域10a的宽度相同的宽度的情况相比，可以加宽JFET区域并且可以减小JFET电阻。因此可以降低导通电阻。版权所有（C）2012，JPO＆INPIT

8. 发明专利

JP2012116732A Method of manufacturing silicon carbide single crystal 有权
标题翻译：制造单晶碳化硅的方法
公开(公告)号：JP2012116732A
公开(公告)日：2012-06-21
申请号：JP2010270295
申请日：2010-12-03
申请人： Denso Corp , Toyota Central R&D Labs Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー , 株式会社豊田中央研究所
发明人： WATANABE HIROKI , KITO YASUO , FURUKAWA TAIJI , YAMAMOTO KENSAKU , TAKATANI HIDESHI , SUGIMOTO MASAHIRO , WATANABE YUKIHIKO , SOEJIMA SHIGEMASA , ISHIKAWA TAKESHI
IPC分类号： C30B29/36 , C30B25/20 , H01L21/205
CPC分类号： H01L21/0262 , C30B25/186 , C30B29/36 , H01L21/02378 , H01L21/0243 , H01L21/02529 , H01L21/02658 , H01L21/046 , H01L21/0475 , H01L29/04
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing an SiC single crystal capable of reducing threading dislocations while suppressing transfer of polymorphism and dislocation without performing sequential lamination of p-layers and n-layers.SOLUTION: A very deep etch pit 1b is formed in the position corresponding to a leak portion by performing molten KOH etching and the like after Al ion implantation and activation annealing, based on findings that a dislocation causing leak such as a drain leak of a vertical MOSFET is a threading screw dislocation. When an SiC growth layer 4 is epitaxially grown on the surface of the etch pit 1b in such a condition that portions grown in the side wall parts of the etch pit 1b are brought into contact mutually, the dislocation is prevented from being transferred to the SiC growth layer 4. In this way, the SiC growth layer 4 having the surface including no threading screw dislocation 1a can be obtained. Therefore, without performing sequential lamination of p-layers and n-layers, the SiC single crystal capable of reducing threading screw dislocations can be produced while suppressing transfer of polymorphism and dislocation.
摘要翻译：要解决的问题：提供一种能够在不进行p层和n层的顺序层压的同时抑制多晶型转移和位错的同时能够减少穿透位错的SiC单晶的制造方法。解决方案：通过在Al离子注入和活化退火之后进行熔融KOH蚀刻等形成在与泄漏部分相对应的位置中的非常深的蚀刻坑1b，基于发现泄漏如泄漏泄漏的位错的垂直MOSFET是螺纹螺钉错位。当在蚀刻凹坑1b的表面上外延生长SiC生长层4，使得在蚀刻坑1b的侧壁部分中生长的部分相互接触的情况下，防止位错转移到SiC 以这种方式，可以获得具有不包括螺纹螺纹位错1a的表面的SiC生长层4。因此，在不进行p层和n层的顺序层叠的情况下，能够抑制多晶型和位错的转移而能够减少螺纹位错的SiC单晶。版权所有（C）2012，JPO＆INPIT

9. 发明专利

JP2012069797A Insulated gate transistor 审中-公开
标题翻译：绝缘栅晶体管
公开(公告)号：JP2012069797A
公开(公告)日：2012-04-05
申请号：JP2010214240
申请日：2010-09-24
申请人： Denso Corp , Toyota Central R&D Labs Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー , 株式会社豊田中央研究所
发明人： SUGIMOTO MASAHIRO , ISHIKAWA TAKESHI , SOEJIMA SHIGEMASA , WATANABE YUKIHIKO , SUZUKI MASAHIRO , MATSUKI HIDEO
IPC分类号： H01L29/78 , H01L29/739
摘要： PROBLEM TO BE SOLVED: To provide an insulated gate transistor, having a trench gate electrode with a high breakdown voltage characteristic, hardly producing a manufacturing error in the breakdown voltage characteristic.SOLUTION: The insulated gate transistor includes: a first region of first conductive type, formed in the range facing the upper surface of a semiconductor layer and connected to a first electrode; a second region of second conductive type, formed on the lower side of the first region; a third region of first conductive type formed on the lower side of the second region; a pair of fourth regions of second conductive type, connected to the first electrode; and a trench gate electrode. Each of the pair of fourth regions is formed on each side of a trench to sandwich the center of the trench. Each of the fourth regions has a vertical region extending to a position deeper than the lower end of an insulating film in the third region, and a horizontal region extending to the center side of the trench from the vertical region in the third region, in the position deeper than the lower end of the insulating film.
摘要翻译：解决的问题：为了提供具有高击穿电压特性的沟槽栅电极的绝缘栅晶体管，几乎不产生击穿电压特性的制造误差。解决方案：绝缘栅晶体管包括：第一导电类型的第一区域，形成在面向半导体层的上表面并连接到第一电极的范围内; 第二导电类型的第二区域，形成在第一区域的下侧; 形成在所述第二区域的下侧的第一导电类型的第三区域; 连接到第一电极的一对第二导电类型的第四区域; 和沟槽栅电极。一对第四区域中的每一个形成在沟槽的每一侧以夹住沟槽的中心。每个第四区域具有延伸到比第三区域中的绝缘膜的下端更深的位置的垂直区域，以及从第三区域中的垂直区域延伸到沟槽的中心侧的水平区域，在位置比绝缘膜的下端深。版权所有（C）2012，JPO＆INPIT

10. 发明专利

JP2012004312A Method of manufacturing silicon carbide semiconductor device and silicon carbide semiconductor device 有权
标题翻译：制造碳化硅半导体器件和硅碳化硅半导体器件的方法
公开(公告)号：JP2012004312A
公开(公告)日：2012-01-05
申请号：JP2010137539
申请日：2010-06-16
申请人： Denso Corp , Toyota Central R&D Labs Inc , Toyota Motor Corp , トヨタ自動車株式会社 , 株式会社デンソー , 株式会社豊田中央研究所
发明人： MATSUKI HIDEO , SUGIMOTO MASAHIRO , TAKATANI HIDESHI , MORIMOTO ATSUSHI , SOEJIMA SHIGEMASA , ISHIKAWA TAKESHI , WATANABE YUKIHIKO
IPC分类号： H01L29/06 , H01L21/336 , H01L29/12 , H01L29/739 , H01L29/78
CPC分类号： H01L29/7813 , H01L29/0615 , H01L29/0619 , H01L29/0638 , H01L29/0661 , H01L29/1608 , H01L29/66068 , H01L29/7811
摘要： PROBLEM TO BE SOLVED: To simplify a manufacturing process by simplifying a step for forming a RESURF layer or an impurity layer constituting an EQR structure.SOLUTION: The surface layer of an n-type drift layer located below a recess 20 in a p-type RESURF layer 21 is connected, by migration of SiC, to a part formed on the surface layer of a p-type base region 3 in the p-type RESURF layer 21. Consequently, the p-type RESURF layer 21 can be connected to the p-type base region 3 without requiring oblique ion implantation even if the side wall of the recess 20 is steep. Since the step for forming the p-type RESURF layer 21 can be simplified, the manufacturing process can be simplified.
摘要翻译：解决的问题：为了简化制造工序，简化形成构成EQR结构的RESURF层或杂质层的工序。解决方案：通过SiC的迁移将位于p型RESURF层21中的凹部20下方的n

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