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11. 发明授权

US08004024B2 Field effect transistor 有权
标题翻译：场效应晶体管
公开(公告)号：US08004024B2
公开(公告)日：2011-08-23
申请号：US12348404
申请日：2009-01-05
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
IPC分类号： H01L29/423 , H01L29/78
CPC分类号： H01L29/4983 , H01L29/4908 , H01L29/6656 , H01L29/6659 , H01L29/66772 , H01L29/7833 , H01L29/78621 , Y10S977/742 , Y10S977/847
摘要： A transistor. The transistor including: a well region in a substrate; a gate dielectric layer on a top surface of the well region; a polysilicon gate electrode on a top surface of the gate dielectric layer; spacers formed on opposite sidewalls of the polysilicon gate electrode; source/drain regions formed on opposite sides of the polysilicon gate electrode in the well region; a first doped region in the polysilicon gate electrode, the first doped region extending into the polysilicon gate electrode from a top surface of the polysilicon gate electrode; and a buried second doped region in the polysilicon gate electrode.
摘要翻译：晶体管。晶体管包括：衬底中的阱区; 在所述阱区的顶表面上的栅介质层; 栅极电介质层的顶表面上的多晶硅栅电极; 间隔物形成在多晶硅栅电极的相对侧壁上; 形成在阱区中的多晶硅栅电极的相对侧上的源/漏区; 所述多晶硅栅电极中的第一掺杂区域，所述第一掺杂区域从所述多晶硅栅电极的顶表面延伸到所述多晶硅栅电极; 以及多晶硅栅电极中的掩埋的第二掺杂区。

12. 发明授权

US07557023B2 Implantation of gate regions in semiconductor device fabrication 失效
标题翻译：在半导体器件制造中植入栅极区域
公开(公告)号：US07557023B2
公开(公告)日：2009-07-07
申请号：US11532189
申请日：2006-09-15
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
IPC分类号： H01L21/425
CPC分类号： H01L29/66545 , H01L21/0273 , H01L21/266 , H01L21/28035 , H01L29/1083 , H01L29/6653 , H01L29/6659
摘要： A semiconductor fabrication method. The method includes providing a semiconductor structure which includes (i) a semiconductor layer, (ii) a gate dielectric layer on the semiconductor layer, and (iii) a gate electrode region on the gate dielectric layer. The gate dielectric layer is sandwiched between and electrically insulates the semiconductor layer and the gate electrode region. The semiconductor layer and the gate dielectric layer share a common interfacing surface which defines a reference direction perpendicular to the common interfacing surface and pointing from the semiconductor layer to the gate dielectric layer. Next, a resist layer is formed on the gate dielectric layer and the gate electrode region. Next, a cap portion of the resist layer directly above the gate electrode region in the reference direction is removed without removing any portion of the resist layer not directly above the gate electrode region in the reference direction.
摘要翻译：半导体制造方法。该方法包括提供半导体结构，其包括（i）半导体层，（ii）半导体层上的栅极电介质层，以及（iii）栅极电介质层上的栅电极区。栅极电介质层被夹在半导体层和栅极电极区域之间并使其电绝缘。半导体层和栅极介电层共享公共接口表面，其界定垂直于公共接口表面的参考方向并且从半导体层指向栅极介电层。接下来，在栅极电介质层和栅极电极区域上形成抗蚀剂层。接下来，去除在参考方向上正好在栅极区域上方的抗蚀剂层的盖部分，而不去除在参考方向上不在栅电极区域正上方的任何部分的抗蚀剂层。

13. 发明授权

US07368712B2 Y-shaped carbon nanotubes as AFM probe for analyzing substrates with angled topography 有权
标题翻译： Y型碳纳米管作为用于分析具有倾斜的地形的基底的AFM探针
公开(公告)号：US07368712B2
公开(公告)日：2008-05-06
申请号：US11164792
申请日：2005-12-06
申请人： Carol A. Boye , Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
发明人： Carol A. Boye , Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
IPC分类号： G01N23/00 , G21K7/00
CPC分类号： G01Q60/42 , G01Q70/12
摘要： A Y-shaped carbon nanotube atomic force microscope probe tip and methods comprise a shaft portion; a pair of angled arms extending from a same end of the shaft portion, wherein the shaft portion and the pair of angled arms comprise a chemically modified carbon nanotube, and wherein the chemically modified carbon nanotube is modified with any of an amine, carboxyl, fluorine, and metallic component. Preferably, each of the pair of angled arms comprises a length of at least 200 nm and a diameter between 10 and 200 nm. Moreover, the chemically modified carbon nanotube is preferably adapted to allow differentiation between substrate materials to be probed. Additionally, the chemically modified carbon nanotube is preferably adapted to allow fluorine gas to flow through the chemically modified carbon nanotube onto a substrate to be characterized. Furthermore, the chemically modified carbon nanotube is preferably adapted to chemically react with a substrate surface to be characterized.
摘要翻译： Y型碳纳米管原子力显微镜探针头和方法包括轴部分; 一对成角度的臂，其从所述轴部的同一端延伸，其中所述轴部和所述一对成角度的臂包括化学改性的碳纳米管，并且其中所述化学改性的碳纳米管用胺，羧基，氟，和金属成分。优选地，一对成角度的臂中的每一个包括至少200nm的长度和10和200nm之间的直径。此外，化学改性的碳纳米管优选适于允许待探测的基底材料之间的分化。此外，化学改性的碳纳米管优选适于使氟气通过化学改性的碳纳米管流动到待表征的基底上。此外，化学改性的碳纳米管优选适于与要表征的基材表面发生化学反应。

14. 发明授权

US07358140B2 Pattern density control using edge printing processes 有权
标题翻译：图案密度控制采用边缘印刷工艺
公开(公告)号：US07358140B2
公开(公告)日：2008-04-15
申请号：US11163968
申请日：2005-11-04
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L27/1052 , Y10S438/95
摘要： A structure fabrication method. The method comprises providing a design structure that includes (i) a design substrate and (ii) M design normal regions on the design substrate, wherein M is a positive integer greater than 1. Next, N design sacrificial regions are added between two adjacent design normal regions of the M design normal regions, wherein N is a positive integer. Next, an actual structure is provided that includes (i) an actual substrate corresponding to the design substrate, (ii) a to-be-etched layer on the actual substrate, and (iii) a memory layer on the to-be-etched layer. Next, an edge printing process is performed on the memory layer so as to form (a) M normal memory portions aligned with the M design normal regions and (b) N sacrificial memory portions aligned with the N design sacrificial regions.
摘要翻译：一种结构制造方法。该方法包括提供一种设计结构，其包括（i）设计基板和（ii）设计基板上的M设计法线区域，其中M是大于1的正整数。接下来，在两个相邻设计之间添加N个设计牺牲区域 M正常区域的正常区域，其中N是正整数。接下来，提供实际结构，其包括（i）与设计基板对应的实际基板，（ii）实际基板上的待蚀刻层，以及（iii）待蚀刻的存储层层。接下来，对存储层执行边缘打印处理，以便形成（a）与M设计法线区域对准的M个正常存储器部分和（b）与N个设计牺牲区域对准的N个牺牲存储器部分。

15. 发明授权

US07345370B2 Wiring patterns formed by selective metal plating 有权
标题翻译：通过选择性金属电镀形成的布线图案
公开(公告)号：US07345370B2
公开(公告)日：2008-03-18
申请号：US10905590
申请日：2005-01-12
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
IPC分类号： H01L23/48
CPC分类号： H01L21/76885 , H01L21/76816 , H01L21/7682 , H01L21/76837 , H01L21/76852 , H01L21/76862 , H01L21/76871 , H01L21/76874 , H01L23/5283 , H01L23/53209 , H01L2221/1089 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： Conductive sidewall spacer structures are formed using a method that patterns structures (mandrels) and activates the sidewalls of the structures. Metal ions are attached to the sidewalls of the structures and these metal ions are reduced to form seed material. The structures are then trimmed and the seed material is plated to form wiring on the sidewalls of the structures.
摘要翻译：使用图案结构（心轴）并激活结构的侧壁的方法形成导电侧壁间隔结构。金属离子附着在结构的侧壁上，这些金属离子被还原成晶种。然后对结构进行修整，并且种子材料被电镀以在结构的侧壁上形成布线。

16. 发明授权

US07265013B2 Sidewall image transfer (SIT) technologies 失效
标题翻译：侧墙图像传输（SIT）技术
公开(公告)号：US07265013B2
公开(公告)日：2007-09-04
申请号：US11162662
申请日：2005-09-19
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Kirk D. Peterson
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Kirk D. Peterson
IPC分类号： H01L21/8242 , H01L21/336
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/28132
摘要： A structure fabrication method. The method comprises providing a structure which comprises (a) a to-be-etched layer, (b) a memory region, (c) a positioning region, (d) and a capping region on top of one another. Then, the positioning region is indented. Then, a conformal protective layer is formed on exposed-to-ambient surfaces of the structure. Then, portions of the conformal protective layer are removed so as to expose the capping region to the surrounding ambient without exposing the memory region to the surrounding ambient. Then, the capping region is removed so as to expose the positioning region to the surrounding ambient. Then, the positioning region is removed so as to expose the memory region to the surrounding ambient. Then, the memory region is directionally etched with remaining portions of the conformal protection layer serving as a blocking mask.
摘要翻译：一种结构制造方法。该方法包括提供一种结构，该结构包括：（a）待蚀刻层，（b）存储区域，（c）位于彼此顶部的定位区域（d）和封盖区域。然后，定位区域缩进。然后，在结构的暴露于环境的表面上形成保形层。然后，去除保形层的一部分，以将覆盖区域暴露于周围环境，而不会使存储区域暴露于周围环境。然后，去除封盖区域，以将定位区域暴露于周围环境。然后，移除定位区域，以将存储区域暴露于周围环境。然后，存储区域被定向蚀刻，保形层的剩余部分用作阻挡掩模。

17. 发明授权

US08541823B2 Field effect transistor 有权
标题翻译：场效应晶体管
公开(公告)号：US08541823B2
公开(公告)日：2013-09-24
申请号：US13179635
申请日：2011-07-11
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
IPC分类号： H01L29/423 , H01L29/78
CPC分类号： H01L29/4983 , H01L29/4908 , H01L29/6656 , H01L29/6659 , H01L29/66772 , H01L29/7833 , H01L29/78621 , Y10S977/742 , Y10S977/847
摘要： A transistor. The transistor including: a well region in a substrate; a gate dielectric layer on a top surface of the well region; a polysilicon gate electrode on a top surface of the gate dielectric layer; spacers formed on opposite sidewalls of the polysilicon gate electrode; source/drain regions formed on opposite sides of the polysilicon gate electrode in the well region; a first doped region in the polysilicon gate electrode, the first doped region extending into the polysilicon gate electrode from a top surface of the polysilicon gate electrode; and a buried second doped region in the polysilicon gate electrode.
摘要翻译：晶体管。晶体管包括：衬底中的阱区; 在所述阱区的顶表面上的栅介质层; 栅极电介质层的顶表面上的多晶硅栅电极; 间隔物形成在多晶硅栅电极的相对侧壁上; 形成在阱区中的多晶硅栅电极的相对侧上的源/漏区; 所述多晶硅栅电极中的第一掺杂区域，所述第一掺杂区域从所述多晶硅栅电极的顶表面延伸到所述多晶硅栅电极; 以及多晶硅栅电极中的掩埋的第二掺杂区。

18. 发明申请

US20110266621A1 FIELD EFFECT TRANSISTOR 有权
标题翻译：场效应晶体管
公开(公告)号：US20110266621A1
公开(公告)日：2011-11-03
申请号：US13179635
申请日：2011-07-11
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
IPC分类号： H01L29/78 , H01L29/786
CPC分类号： H01L29/4983 , H01L29/4908 , H01L29/6656 , H01L29/6659 , H01L29/66772 , H01L29/7833 , H01L29/78621 , Y10S977/742 , Y10S977/847
摘要： A transistor. The transistor including: a well region in a substrate; a gate dielectric layer on a top surface of the well region; a polysilicon gate electrode on a top surface of the gate dielectric layer; spacers formed on opposite sidewalls of the polysilicon gate electrode; source/drain regions formed on opposite sides of the polysilicon gate electrode in the well region; a first doped region in the polysilicon gate electrode, the first doped region extending into the polysilicon gate electrode from a top surface of the polysilicon gate electrode; and a buried second doped region in the polysilicon gate electrode.
摘要翻译：晶体管。晶体管包括：衬底中的阱区; 在所述阱区的顶表面上的栅介质层; 栅极电介质层的顶表面上的多晶硅栅电极; 间隔物形成在多晶硅栅电极的相对侧壁上; 形成在阱区中的多晶硅栅电极的相对侧上的源/漏区; 所述多晶硅栅电极中的第一掺杂区域，所述第一掺杂区域从所述多晶硅栅电极的顶表面延伸到所述多晶硅栅电极; 以及多晶硅栅电极中的掩埋的第二掺杂区。

19. 发明申请

US20110027951A1 SHARED GATE FOR CONVENTIONAL PLANAR DEVICE AND HORIZONTAL CNT 有权
标题翻译：常规平面设备和水平CNT的共享门
公开(公告)号：US20110027951A1
公开(公告)日：2011-02-03
申请号：US12902944
申请日：2010-10-12
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Mark E. Masters
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Mark E. Masters
IPC分类号： H01L21/8234
CPC分类号： H01L21/823412 , B01J23/74 , B01J37/0238 , B82Y10/00 , H01L21/7624 , H01L21/823437 , H01L27/286 , H01L51/0048 , H01L51/0545 , H01L51/055 , Y10S977/742 , Y10S977/762 , Y10S977/763
摘要： A semiconductor structure in which a planar semiconductor device and a horizontal carbon nanotube transistor have a shared gate and a method of fabricating the same are provided in the present application. The hybrid semiconductor structure includes at least one horizontal carbon nanotube transistor and at least one planar semiconductor device, in which the at least one horizontal carbon nanotube transistor and the at least one planar semiconductor device have a shared gate and the at least one horizontal carbon nanotube transistor is located above a gate of the at least one planar semiconductor device.
摘要翻译：在本申请中提供了其中平面半导体器件和水平碳纳米管晶体管具有共享栅极的半导体结构及其制造方法。所述混合半导体结构包括至少一个水平碳纳米管晶体管和至少一个平面半导体器件，其中所述至少一个水平碳纳米管晶体管和所述至少一个平面半导体器件具有共享栅极，并且所述至少一个水平碳纳米管晶体管位于至少一个平面半导体器件的栅极之上。

20. 发明授权

US07652334B2 Shallow trench isolation formation 有权
标题翻译：浅沟隔离形成
公开(公告)号：US07652334B2
公开(公告)日：2010-01-26
申请号：US11866471
申请日：2007-10-03
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
IPC分类号： H01L29/72
CPC分类号： H01L21/02164 , H01L21/0214 , H01L21/02282 , H01L21/3143 , H01L21/3147 , H01L21/316 , H01L21/76224 , H01L21/823878
摘要： A method and structure for forming a semiconductor structure. A semiconductor substrate is provided. A trench is formed within the semiconductor substrate. A first layer of electrically insulative material is formed within the trench. A first portion and a second portion of the first layer of electrically insulative material is removed. A second layer of electrically insulative material is selectively grown on the first layer comprising the removed first portion and the removed second portion.
摘要翻译：一种用于形成半导体结构的方法和结构。提供半导体衬底。在半导体衬底内形成沟槽。第一层电绝缘材料形成在沟槽内。去除第一层电绝缘材料的第一部分和第二部分。选择性地在第一层上生长第二层电绝缘材料，该第一层包括去除的第一部分和被去除的第二部分。

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