专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明专利

JP2008078395A Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：JP2008078395A
公开(公告)日：2008-04-03
申请号：JP2006256012
申请日：2006-09-21
申请人： Toshiba Corp , 株式会社東芝
发明人： KATO TOUSHI , NOGUCHI MITSUHIRO
IPC分类号： H01L27/10 , H01L21/3205 , H01L21/82 , H01L21/8247 , H01L23/52 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/0207 , H01L27/105 , H01L27/11517 , H01L27/11519 , H01L27/11526
摘要： PROBLEM TO BE SOLVED: To achieve a reduction in chip size, while preventing the occurrence of short-circuitings in a conductive line that has a line and space pattern.
SOLUTION: A nonvolatile semiconductor memory is provided with a cell array 1, a plurality of the conductive lines WL11-WL1n extending in a lead-out area 2 from on the cell array 1, and a plurality of contact holes CS11-CS1n arranged inside the lead-out area, so as to be successively separated from the end part of the cell array 1, as going from one of a plurality of the conductive lines WL11-WL1n to another. Each of a plurality of the conductive lines WL11-WL1n has a first conductive-line part 6 having a first conductive-line width W1; a second conductive-line part 8 connected to each contact hole CS11-CS1n, while having a second conductive-line width W2 that is narrower than the first conductive-line width W1; and a third conductive-line part 7, that electrically connects between the first conductive-line part 6 and the second conductive-line part 8.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了实现芯片尺寸的减小，同时防止在具有线和空间图案的导线中发生短路。解决方案：非易失性半导体存储器设置有单元阵列1，在单元阵列1上的引出区域2中延伸的多条导线WL11-WL1n和多个接触孔CS11-CS1n 布置在引出区域的内部，以便从多个导线WL11-WL1n中的一个到另一个从电池阵列1的端部连续分离。多个导线WL11〜WL1n中的每一个具有具有第一导线宽度W1的第一导电线部分6; 连接到每个接触孔CS11-CS1n的第二导电线部分8，同时具有比第一导电线宽度W1窄的第二导电线宽度W2; 以及第三导电线部分7，其电连接在第一导电线部分6和第二导电线部分8之间。版权所有（C）2008，JPO＆INPIT

12. 发明专利

JP2007103472A Semiconductor integrated circuit device and its manufacturing method 有权
标题翻译：半导体集成电路设备及其制造方法
公开(公告)号：JP2007103472A
公开(公告)日：2007-04-19
申请号：JP2005288567
申请日：2005-09-30
申请人： Toshiba Corp , 株式会社東芝
发明人： KOYAMA HARUHIKO , NOGUCHI MITSUHIRO , KAJIMOTO SANETOSHI
IPC分类号： H01L27/08 , H01L21/027 , H01L21/82 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524 , Y10S438/942 , Y10S438/975
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device which can be suppressed in the increase of manufacturing cost, and also to provide its manufacturing method.
SOLUTION: On a semiconductor substrate 1, a first film 18 is formed which includes a first opening 27 and a second opening corresponding to a first well formation region 3. A dopant 20 for the first well is introduced into the substrate 1 via the first opening 27 and the second opening. With the first opening 27 as an alignment mark, at least a third opening 102 corresponding to a second well formation region 4 is formed in the first film 18. Then, a dopant 22 for the second well is introduced into the substrate 1 at least via the third opening 102.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供可以在制造成本的增加中抑制的半导体集成电路器件，以及提供其制造方法。解决方案：在半导体衬底1上，形成第一膜18，其包括对应于第一阱形成区域3的第一开口27和第二开口。用于第一阱的掺杂剂20通过第一开口27和第二开口。利用第一开口27作为对准标记，在第一膜18中形成有至少第二开孔102对应于第二阱形成区域4.然后，将第二阱的掺杂剂22至少通过第三次开幕102.版权所有（C）2007，JPO＆INPIT

13. 发明专利

JP2005276428A Nonvolatile semiconductor storage device 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2005276428A
公开(公告)日：2005-10-06
申请号：JP2005113832
申请日：2005-04-11
申请人： Toshiba Corp , 株式会社東芝
发明人： AIDA AKIRA , NOGUCHI MITSUHIRO
IPC分类号： G11C16/02 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory using a step-up write-in system that attains both high-speed writing and high reliability. SOLUTION: This nonvolatile semiconductor memory includes a semiconductor board, a cell array configured by arraying nonvolatile memory cells capable of electrically writing and erasure, wherein a charge storage layer is formed over the semiconductor board through a first gate insulating film and a gate electrode is formed over the charge storage layer through a second gate insulating film, and a control circuit for performing sequence control of data writing and erasure of a selected memory cell of the cell array. The nonvolatile semiconductor memory has a write operation mode in which a first write-in operation for applying a write-in pulse voltage between the gate electrode and the semiconductor board about data write-in of the memory cell is performed by a first step-up voltage and successively, a second write-in operation for applying a write-in pulse voltage is performed by a second step-up voltage smaller than the first step-up voltage. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种使得能够实现高速写入和高可靠性的升压写入系统的非易失性半导体存储器。解决方案：该非易失性半导体存储器包括半导体板，通过排列能够进行电写入和擦除的非易失性存储单元配置的单元阵列，其中电荷存储层通过第一栅极绝缘膜和栅极形成在半导体板上电极通过第二栅极绝缘膜形成在电荷存储层上，以及控制电路，用于执行数据写入和擦除单元阵列的选定存储单元的序列控制。非易失性半导体存储器具有写入操作模式，其中，关于存储器单元的数据写入，在栅电极和半导体板之间施加写入脉冲电压的第一写入操作通过第一升压并且依次执行用于施加写入脉冲电压的第二写入操作，该第二写入操作是通过小于第一升压电压的第二升压电压。版权所有（C）2006，JPO＆NCIPI

14. 发明专利

JP2005044844A Nonvolatile semiconductor memory device and its manufacturing method 审中-公开
标题翻译：非线性半导体存储器件及其制造方法
公开(公告)号：JP2005044844A
公开(公告)日：2005-02-17
申请号：JP2003200343
申请日：2003-07-23
申请人： Toshiba Corp , 株式会社東芝
发明人： KURITA KOICHI , NOGUCHI MITSUHIRO , AIDA AKIRA
IPC分类号： G11C17/00 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524 , H01L29/42324
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device which is low enough in resistance, capable of ensuring a high intergate withstand voltage, and highly reliable even when a control gate resistance lowering metal film is formed of WSi having an Si/W composition ratio of 2.4 or below to 1 or W. SOLUTION: The side wall of a control gate resistance lowering metal film 25 formed of WSi having an Si/W composition ratio of 2.4 or below to 1 or W is covered with a side wall insulating film 31. Therefore, abnormal oxidation hardly occurs in the control gate resistance lowering metal film 25 in a gate side wall oxidation process, and a gate electrode can be kept normal in shape and dimensions. W contained in the control gate resistance lowering metal film 25 is restrained from diffusing in an oxidizing furnace and causing metal contamination, voids are never produced in an interlayer insulating film, and superior embedding characteristics can be realized. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：解决的问题：为了提供一种能够确保高的隔间耐受电压的低电阻的非易失性半导体存储器件，即使当由具有Si的WSi形成控制栅极电阻降低金属膜时也是高可靠性的 / W组成比为2.4以下至1或W.解决方案：覆盖由Si / W组成比为2.4或更低至1或W的WSi形成的控制栅极电阻降低金属膜25的侧壁具有侧壁绝缘膜31.因此，在栅极侧壁氧化工艺中，控制栅极电阻降低金属膜25中几乎不发生异常氧化，并且可以使栅极保持正常的形状和尺寸。控制栅极电阻降低金属膜25中包含的W被抑制在氧化炉中扩散并引起金属污染，在层间绝缘膜中不会产生空隙，并且可以实现优异的嵌入特性。版权所有（C）2005，JPO＆NCIPI

15. 发明专利

JP2004326867A Data storage system 有权
公开(公告)号：JP2004326867A
公开(公告)日：2004-11-18
申请号：JP2003117453
申请日：2003-04-22
申请人： Toshiba Corp , 株式会社東芝
发明人： NOGUCHI MITSUHIRO , AIDA AKIRA
IPC分类号： G11C16/02 , G06F11/10 , G06K19/073 , G11C16/04 , G11C16/06 , G11C29/00 , G11C29/42 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G06F11/1008 , G11C16/0483
摘要： PROBLEM TO BE SOLVED: To provide a data storage system capable of preventing the falure due to read-disturbance. SOLUTION: This system comprises a memory-macro 7 including a memory cell array 1, an error bit detecting circuit 5 and an error bit discriminating circuit 6 connected mutually with a first internal wiring 92, and is provided with an error correction code circuit part 100 connected to the memory-macro 7 through a second internal wiring 91, and temporary memories 101, 102 used temporarily in error correction of the memory cell array 1. The temporary memory may be formed in the memory-macro 7. or/and it may be formed in the outside of the memory-macro and the error correction code circuit part 100 and may be connected to the error bit discriminating circuit 6 through an internal I/O line 94. Read-disturbance is detected before causing of data destruction using a data error code correcting circuit (ECC), and refresh is performed. COPYRIGHT: (C)2005,JPO&NCIPI

16. 发明专利

JPH11273338A Magnetic storage device and its driving method 失效
标题翻译：磁性存储器件及其驱动方法
公开(公告)号：JPH11273338A
公开(公告)日：1999-10-08
申请号：JP7457798
申请日：1998-03-23
申请人： Toshiba Corp , 株式会社東芝
发明人： NOGUCHI MITSUHIRO
IPC分类号： G11C11/15 , H01F10/06 , H01F10/16 , H01L21/8246 , H01L27/105
摘要： PROBLEM TO BE SOLVED: To fix the direction of a current flowing to a data select line when data are written and read in. SOLUTION: On a ferromagnetic material film 11, a soft magnetic material film 13 which has a smaller coercive force than the ferromagnetic material film 11 is formed across a conductive nonmagnetic material film 12. On the soft magnetic material film 13, a bimetal layer 14 which has projection parts is formed. Metal conductive layers 15 are formed on the tops of the projection parts of the bimetal layer 14. Then an inter-layer insulating film 21 is formed over the entire surface. The data select line 22 is formed centering on an area where the metal conductive layer 15 is not formed.
摘要翻译：要解决的问题：当数据被写入和读入时，固定流向数据选择线的电流的方向。解决方案：在铁磁材料膜11上，具有比铁磁性材料更小的矫顽力的软磁性材料膜13 材料膜11跨越导电非磁性材料膜12形成。在软磁材料膜13上形成具有突出部分的双金属层14。金属导电层15形成在双金属层14的突出部分的顶部上。然后在整个表面上形成层间绝缘膜21。数据选择线22以不形成金属导电层15的区域为中心而形成。

17. 发明专利

JP2014022394A Nonvolatile semiconductor memory device 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2014022394A
公开(公告)日：2014-02-03
申请号：JP2012156504
申请日：2012-07-12
申请人： Toshiba Corp , 株式会社東芝
发明人： GOYO AKIMICHI , NOGUCHI MITSUHIRO , KUTSUKAKE HIROYUKI
IPC分类号： H01L21/8247 , H01L21/336 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a NAND-type nonvolatile semiconductor memory device capable of reducing a manufacturing cost, and a method for manufacturing the same.SOLUTION: A nonvolatile semiconductor memory device includes a memory cell transistor MT having a floating gate electrode 4 and a control gate electrode CG and a field effect transistor Tr having a gate electrode composed of a lower electrode layer 3 and an upper electrode layer GC. The floating gate electrode 4 of the memory cell transistor MT is composed of p-type polysilicon. A p-type polysilicon film 82 in the control gate electrode CG is laminated on the floating gate electrode 4 via an inter-poly insulating film 5. The lower electrode layer 3 of the field effect transistor Tr is composed of n-type polysilicon. The p-type polysilicon film 82 included in the upper electrode layer GC is connected to the lower electrode layer 3 via an opening in the inter-poly insulating film 5.
摘要翻译：要解决的问题：提供能够降低制造成本的NAND型非易失性半导体存储器件及其制造方法。解决方案：非易失性半导体存储器件包括具有浮置栅电极4的存储单元晶体管MT和控制栅电极CG和具有由下电极层3和上电极层GC构成的栅电极的场效应晶体管Tr。存储单元晶体管MT的浮栅电极4由p型多晶硅构成。控制栅电极CG中的p型多晶硅膜82通过多晶硅绝缘膜5层叠在浮栅电极4上。场效应晶体管Tr的下电极层3由n型多晶硅构成。包含在上电极层GC中的p型多晶硅膜82通过多晶硅绝缘膜5中的开口连接到下电极层3。

18. 发明专利

JP2013225617A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2013225617A
公开(公告)日：2013-10-31
申请号：JP2012097783
申请日：2012-04-23
申请人： Toshiba Corp , 株式会社東芝
发明人： TOBA TAKAYUKI , NOGUCHI MITSUHIRO
IPC分类号： H01L21/8247 , H01L21/336 , H01L21/768 , H01L23/532 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having high operating speed and to provide a method of manufacturing the same.SOLUTION: A semiconductor device includes: a substrate; a first conductive material provided above the substrate; a carbon-containing film provided above the first conductive material, being spaced apart from the first conductive material, and containing carbon; and a second conductive material provided above the carbon-containing film and being spaced apart from the carbon-containing film.
摘要翻译：要解决的问题：提供一种具有高操作速度的半导体器件，并提供其制造方法。解决方案：一种半导体器件，包括：衬底; 设置在所述基板上方的第一导电材料; 设置在所述第一导电材料上方的与所述第一导电材料间隔开并含有碳的含碳膜; 以及设置在含碳膜上方并与含碳膜隔开的第二导电材料。

19. 发明专利

JP2013225584A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2013225584A
公开(公告)日：2013-10-31
申请号：JP2012096879
申请日：2012-04-20
申请人： Toshiba Corp , 株式会社東芝
发明人： NODA MITSUHIKO , NOGUCHI MITSUHIRO
IPC分类号： H01L21/8247 , H01L21/336 , H01L21/768 , H01L23/522 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of being downsized.SOLUTION: A semiconductor device includes a semiconductor substrate in which active regions are sectioned on its upper layer portion, three lower vias provided directly above the active regions, and three upper vias having lower end portions each being in contact with upper end portions of the lower vias.
摘要翻译：要解决的问题：提供能够减小尺寸的半导体器件。解决方案：一种半导体器件包括半导体衬底，其中有源区在其上层部分上被分割，三个下部通孔直接设置在有源区上方，以及三个上部通孔具有各个下端部与下部通孔的上端部接触。

20. 发明专利

JP2013179193A Storage device and manufacturing method thereof 审中-公开
标题翻译：存储器件及其制造方法
公开(公告)号：JP2013179193A
公开(公告)日：2013-09-09
申请号：JP2012042445
申请日：2012-02-28
申请人： Toshiba Corp , 株式会社東芝
发明人： NODA MITSUHIKO , KUTSUKAKE HIROYUKI , OUCHI KAZUYA , NOGUCHI MITSUHIRO
IPC分类号： H01L21/8247 , H01L21/336 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/66825 , H01L27/11543 , H01L29/401 , H01L29/788
摘要： PROBLEM TO BE SOLVED: To provide a storage device at low costs, and a manufacturing method thereof.SOLUTION: A storage device according to an embodiment comprises: a floating gate electrode film provided in a memory cell region; a first inter-electrode insulation film provided on the floating gate electrode film; a control gate electrode film provided on the first inter-electrode insulation film; a lower conductive film provided in a peripheral circuit region; a second inter-electrode insulation film provided on the lower conductive film; an upper conductive film provided on the second inter-electrode insulation film; and a pair of contacts isolated from each other, connected from the lower conductive film from above, and not connected to the upper conductive film. A material of the lower conductive film is same as a material of the floating gate electrode film. A material of the second inter-electrode insulation film is same as a material of the first inter-electrode insulation film. A material of the upper conductive film is same as a material of the control gate electrode film.
摘要翻译：要解决的问题：提供一种低成本的存储装置及其制造方法。根据实施例的存储装置包括：设置在存储单元区域中的浮栅电极膜; 设置在所述浮栅电极膜上的第一电极间绝缘膜; 设置在所述第一电极间绝缘膜上的控制栅极电极膜; 设置在外围电路区域中的下导电膜; 设置在下导电膜上的第二电极间绝缘膜; 设置在所述第二电极间绝缘膜上的上导电膜; 以及彼此隔离的一对触点，从上方与下导电膜连接，并且不连接到上导电膜。下导电膜的材料与浮栅电极膜的材料相同。第二电极间绝缘膜的材料与第一电极间绝缘膜的材料相同。上导电膜的材料与控制栅电极膜的材料相同。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式