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11. 发明申请

US20110103152A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20110103152A1
公开(公告)日：2011-05-05
申请号：US13004926
申请日：2011-01-12
申请人： Masahiro YOSHIHARA , Toshiaki Edahiro , Koji Hosono
发明人： Masahiro YOSHIHARA , Toshiaki Edahiro , Koji Hosono
IPC分类号： G11C16/28
CPC分类号： G11C16/0483 , G11C7/065 , G11C7/067 , G11C16/24 , G11C16/26 , G11C2207/063 , G11C2207/068
摘要： A semiconductor memory device comprises a plurality of memory cells connected to a bit line; and a sense amplifier operative to sense the magnitude of cell current flowing via the bit line in a selected memory cell connected to the bit line to determine the value of data stored in the memory cell. The sense amplifier includes a first transistor for precharge operative to supply current in the bit line via a first and a second sense node, a second transistor for charge transfer interposed between the first and second sense nodes, and a third transistor for continuous current supply operative to supply current in the bit line not via the first and second sense nodes.
摘要翻译：半导体存储器件包括连接到位线的多个存储器单元; 以及读出放大器，用于感测在连接到位线的所选择的存储器单元中经由位线流动的单元电流的大小，以确定存储在存储单元中的数据的值。感测放大器包括用于预充电的第一晶体管，用于经由第一和第二感测节点在位线中提供电流，插入在第一和第二感测节点之间的用于电荷转移的第二晶体管和用于连续电流供应的第三晶体管以不通过第一和第二感测节点在位线中提供电流。

12. 发明授权

US07907463B2 Non-volatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US07907463B2
公开(公告)日：2011-03-15
申请号：US12478181
申请日：2009-06-04
申请人： Toshiaki Edahiro , Fumitaka Arai
发明人： Toshiaki Edahiro , Fumitaka Arai
IPC分类号： G11C7/00
CPC分类号： G11C16/16 , G11C16/0483
摘要： A controller repeats an erase operation, an erase verify operation, and a step-up operation. A first storage unit stores a value of an erase start voltage applied first as an erase voltage when a series of erase operations are executed. A second storage unit stores a value of an erase completion voltage which is an erase voltage when erasure of data is finished in the erase operation and the erase verify operation. A first comparator compares the erase completion voltage with the erase start voltage each time the erase operation is executed. When the first comparator determines that the erase completion voltage is larger than the erase start voltage, a counter counts up a count value. When the count value becomes larger than a predetermined value, a second comparator updates a value of the erase start voltage stored in the first storage unit.
摘要翻译：控制器重复擦除操作，擦除验证操作和升压操作。当执行一系列擦除操作时，第一存储单元存储首先施加的擦除开始电压作为擦除电压的值。第二存储单元存储在擦除操作和擦除验证操作中擦除数据结束时作为擦除电压的擦除完成电压的值。每次执行擦除操作时，第一比较器将擦除完成电压与擦除开始电压进行比较。当第一比较器确定擦除完成电压大于擦除开始电压时，计数器对计数值进行计数。当计数值变得大于预定值时，第二比较器更新存储在第一存储单元中的擦除开始电压的值。

13. 发明授权

US07907446B2 Nonvolatile semiconductor memory device and method of driving the same 有权
标题翻译：非易失性半导体存储器件及其驱动方法
公开(公告)号：US07907446B2
公开(公告)日：2011-03-15
申请号：US12266734
申请日：2008-11-07
申请人： Yuui Shimizu , Toshiaki Edahiro
发明人： Yuui Shimizu , Toshiaki Edahiro
IPC分类号： G11C16/04 , G11C8/00 , G11C11/34 , G11C16/06
CPC分类号： G11C8/08 , G11C8/12 , G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C16/3454 , G11C2211/5621
摘要： This disclosure concerns a memory including cell blocks, wherein in a first write sequence for writing data to a first cell block, drivers write the data only to memory cells arranged in a form of a checkered flag among the memory cells included in the first cell block, in a second write sequence for writing the data from the first cell block to a second cell block, the drivers write the data to all memory cells connected to a word line selected in the second cell block, and when the data is read from the first cell block or at a time of data verification when data is written to the first cell block, the word line drivers simultaneously apply a read voltage to two adjacent word lines, and the sense amplifiers detects the data in the memory cells connected to the two word lines.
摘要翻译：本公开涉及包括单元块的存储器，其中在用于将数据写入第一单元块的第一写入序列中，驱动器将数据仅写入到以包括在第一单元块中的存储单元中的格状标志形式布置的存储单元在用于将数据从第一单元块写入第二单元块的第二写入序列中，驱动器将数据写入连接到在第二单元块中选择的字线的所有存储器单元，并且当数据从第一单元块，或者当数据被写入第一单元块时的数据验证时，字线驱动器同时向两个相邻的字线施加读取电压，并且读出放大器检测连接到两个单元的存储单元中的数据字线。

14. 发明授权

US07764542B2 Method for programming a semiconductor memory device 有权
标题翻译：半导体存储器件编程方法
公开(公告)号：US07764542B2
公开(公告)日：2010-07-27
申请号：US12061105
申请日：2008-04-02
申请人： Toshiaki Edahiro , Takuya Futatsuyama , Toshiyuki Enda
发明人： Toshiaki Edahiro , Takuya Futatsuyama , Toshiyuki Enda
IPC分类号： G11C16/04
CPC分类号： G11C16/3418 , G11C16/3427
摘要： A method for programming a semiconductor memory device including such a program sequence as to program target threshold levels constituting multi-level data into multiple memory cells, which are simultaneously selected, wherein the program sequence is controlled to finish programming the multiple memory cells in order of height of the target threshold levels.
摘要翻译：一种用于将包括这样的程序序列的半导体存储器件编程的方法，所述程序序列用于将构成多级数据的程序目标阈值水平同时选择为多个存储器单元，其中控制程序序列以完成多个存储器单元的编程，目标阈值水平的高度。

15. 发明授权

US08711635B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08711635B2
公开(公告)日：2014-04-29
申请号：US13618537
申请日：2012-09-14
申请人： Takuya Futatsuyama , Toshiaki Edahiro , Norihiro Fujita , Fumitaka Arai , Tohru Maruyama , Masaki Kondo
发明人： Takuya Futatsuyama , Toshiaki Edahiro , Norihiro Fujita , Fumitaka Arai , Tohru Maruyama , Masaki Kondo
IPC分类号： G11C11/34
CPC分类号： G11C16/3454 , G11C16/0483
摘要： A nonvolatile semiconductor memory device includes a memory cell which stores data and which is capable of being rewritten electrically, a bit line which is connected electrically to one end of a current path of the memory cell, a control circuit which carries out a verify operation to check a write result after data is written to the memory cell, and a voltage setting circuit which sets a charging voltage for the bit line in a verify operation and a read operation and makes a charging voltage in a read operation higher than a charging voltage in a verify operation.
摘要翻译：非易失性半导体存储器件包括：存储单元，其存储数据并且能够被电气重写;电位地连接到存储单元的电流路径的一端的位线;控制电路，其执行验证操作在将数据写入存储单元之后检查写入结果;以及电压设置电路，其在验证操作和读取操作中设置位线的充电电压，并使读取操作中的充电电压高于充电电压验证操作。

16. 发明授权

US08559226B2 Threshold detecting method and verify method of memory cells 有权
标题翻译：存储单元的阈值检测方法和验证方法
公开(公告)号：US08559226B2
公开(公告)日：2013-10-15
申请号：US13052148
申请日：2011-03-21
申请人： Katsumi Abe , Masahiro Yoshihara , Toshiaki Edahiro
发明人： Katsumi Abe , Masahiro Yoshihara , Toshiaki Edahiro
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/12 , G11C16/32 , G11C16/3468
摘要： According to one embodiment, a threshold detecting method for detecting threshold values of nonvolatile semiconductor memory cells comprises applying a preset voltage to a word line connected to the memory cells, and performing bit-line sense at two different timings during discharging of one of a bit line connected to the memory cells and a node corresponding to the bit line, while a potential of the word line is kept constant.
摘要翻译：根据一个实施例，用于检测非易失性半导体存储单元的阈值的阈值检测方法包括：将预设电压施加到连接到存储单元的字线，以及在放电期间的两个不同定时执行位线检测线连接到存储器单元和对应于位线的节点，而字线的电位保持恒定。

17. 发明授权

US08482985B2 Nonvolatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08482985B2
公开(公告)日：2013-07-09
申请号：US13315516
申请日：2011-12-09
申请人： Ayako Yamano , Osamu Nagao , Toshiaki Edahiro
发明人： Ayako Yamano , Osamu Nagao , Toshiaki Edahiro
IPC分类号： G11C16/06
CPC分类号： G11C16/14 , G11C11/5635 , G11C16/0483 , G11C16/3409 , G11C16/344
摘要： A nonvolatile semiconductor storage device according to an embodiment includes an erase circuit executing an erase sequence, wherein in the erase sequence, the erase circuit executes: an erase operation to change a selection memory cell group to an erased state, after the erase operation, a soft program operation on the selection memory cell group to solve over-erased state, and after the soft program operation, a first soft program verification operation performed on at least one partial selection memory cell group of a first partial selection memory cell group and a second partial selection memory cell group so as to confirm whether the partial selection memory cell group includes a predetermined number of memory cells or more that have threshold values equal to or more than a predetermined first threshold value, and after the first soft program verification operation.
摘要翻译：根据实施例的非易失性半导体存储装置包括执行擦除序列的擦除电路，其中在擦除序列中，擦除电路执行：在擦除操作之后将选择存储单元组改变为擦除状态的擦除操作，对选择存储单元组进行软编程操作以解决过擦除状态，并且在软编程操作之后，对第一部分选择存储单元组和第二部分选择存储单元组的至少一个部分选择存储单元组执行第一软程序验证操作部分选择存储单元组，以确认部分选择存储单元组是否包括具有等于或大于预定第一阈值的阈值的预定数量的存储单元或更多个，以及在第一软程序验证操作之后。

18. 发明申请

US20130010541A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
公开(公告)号：US20130010541A1
公开(公告)日：2013-01-10
申请号：US13618537
申请日：2012-09-14
申请人： Takuya Futatsuyama , Toshiaki Edahiro , Norihiro Fujita , Fumitaka Arai , Tohru Maruyama , Masaki Kondo
发明人： Takuya Futatsuyama , Toshiaki Edahiro , Norihiro Fujita , Fumitaka Arai , Tohru Maruyama , Masaki Kondo
IPC分类号： G11C16/06
CPC分类号： G11C16/3454 , G11C16/0483
摘要： A nonvolatile semiconductor memory device includes a memory cell which stores data and which is capable of being rewritten electrically, a bit line which is connected electrically to one end of a current path of the memory cell, a control circuit which carries out a verify operation to check a write result after data is written to the memory cell, and a voltage setting circuit which sets a charging voltage for the bit line in a verify operation and a read operation and makes a charging voltage in a read operation higher than a charging voltage in a verify operation.

19. 发明申请

US20110305089A1 THRESHOLD DETECTING METHOD AND VERIFY METHOD OF MEMORY CELLS 有权
标题翻译：记忆细胞的阈值检测方法和验证方法
公开(公告)号：US20110305089A1
公开(公告)日：2011-12-15
申请号：US13052148
申请日：2011-03-21
申请人： Katsumi Abe , Masahiro Yoshihara , Toshiaki Edahiro
发明人： Katsumi Abe , Masahiro Yoshihara , Toshiaki Edahiro
IPC分类号： G11C16/34 , G11C16/26 , G11C16/12 , G11C16/04
CPC分类号： G11C16/26 , G11C11/5642 , G11C16/12 , G11C16/32 , G11C16/3468
摘要： According to one embodiment, a threshold detecting method for detecting threshold values of nonvolatile semiconductor memory cells comprises applying a preset voltage to a word line connected to the memory cells, and performing bit-line sense at two different timings during discharging of one of a bit line connected to the memory cells and a node corresponding to the bit line, while a potential of the word line is kept constant.
摘要翻译：根据一个实施例，用于检测非易失性半导体存储单元的阈值的阈值检测方法包括：将预设电压施加到连接到存储单元的字线，以及在放电期间的两个不同定时执行位线检测线连接到存储器单元和对应于位线的节点，而字线的电位保持恒定。

20. 发明授权

US08000155B2 Non-volatile memory device and method for writing data thereto 有权
公开(公告)号：US08000155B2
公开(公告)日：2011-08-16
申请号：US13005582
申请日：2011-01-13
申请人： Toshiaki Edahiro , Kazushige Kanda , Naoya Tokiwa , Takuya Futatsuyama , Koji Hosono , Shigeo Ohshima
发明人： Toshiaki Edahiro , Kazushige Kanda , Naoya Tokiwa , Takuya Futatsuyama , Koji Hosono , Shigeo Ohshima
IPC分类号： G11C7/22 , G11C7/06 , G11C11/00 , G11C17/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2013/009 , G11C2213/32 , G11C2213/72
摘要： The present invention provides a method for writing data to a non-volatile memory device having first wirings and second wirings intersecting one another and memory cells arranged at each intersection therebetween, each of the memory cells having a variable resistive element and a rectifying element connected in series. According to the method, the second wirings are charged to a certain voltage not less than a rectifying-element threshold value, prior to a rise in a selected first wiring. Then, a selected first wiring is charged to a voltage required for writing or erasing, after which a selected second wiring is discharged.

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