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11. 发明授权

US5536388A Vertical electroetch tool nozzle and method 失效
标题翻译：立式电镀工具喷嘴及方法
公开(公告)号：US5536388A
公开(公告)日：1996-07-16
申请号：US460439
申请日：1995-06-02
申请人： Thomas E. Dinan , Kirk G. Berridge , Madhav Datta , Thomas S. Kanarsky , Michael B. Pike , Ravindra V. Shenoy
发明人： Thomas E. Dinan , Kirk G. Berridge , Madhav Datta , Thomas S. Kanarsky , Michael B. Pike , Ravindra V. Shenoy
IPC分类号： C25F7/00 , C25F3/14
CPC分类号： C25F7/00
摘要： A nozzle is provided for use in electroetching a vertically oriented workpiece, comprising a housing having a top, sides, and bottom for creating a flow of etching solution on the workpiece, and means for shaping the flow of etching solution into a moving channel to improve etch uniformity of the workpiece.
摘要翻译：提供一种用于对垂直取向的工件进行电蚀刻的喷嘴，包括具有顶部，侧面和底部的壳体，用于在工件上产生蚀刻溶液流，以及用于使蚀刻溶液流动成移动通道以改善蚀刻工件的均匀性。

12. 发明授权

US07989298B1 Transistor having V-shaped embedded stressor 有权
标题翻译：具有V形嵌入应力的晶体管
公开(公告)号：US07989298B1
公开(公告)日：2011-08-02
申请号：US12692859
申请日：2010-01-25
申请人： Kevin K. Chan , Brian J. Greene , Judson R. Holt , Jeffrey B. Johnson , Thomas S. Kanarsky , Jophy S. Koshy , Kevin McStay , Dae-Gyu Park , Johan W. Weijtmans , Frank B. Yang
发明人： Kevin K. Chan , Brian J. Greene , Judson R. Holt , Jeffrey B. Johnson , Thomas S. Kanarsky , Jophy S. Koshy , Kevin McStay , Dae-Gyu Park , Johan W. Weijtmans , Frank B. Yang
IPC分类号： H01L21/336 , H01L21/76
CPC分类号： H01L29/165 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A semiconductor device and a method of making the device are provided. The method can include forming a gate conductor overlying a major surface of a monocrystalline semiconductor region and forming first spacers on exposed walls of the gate conductor. Using the gate conductor and the first spacers as a mask, at least extension regions are implanted in the semiconductor region and dummy spacers are formed extending outward from the first spacers. Using the dummy spacers as a mask, the semiconductor region is etched to form recesses having at least substantially straight walls extending downward from the major surface to a bottom surface, such that a substantial angle is defined between the bottom surface and the walls. Subsequently, the process is continued by epitaxially growing regions of stressed monocrystalline semiconductor material within the recesses. Then the dummy spacers are removed and the transistor can be completed by forming source/drain regions of the transistor that are at least partially disposed in the stressed semiconductor material regions.
摘要翻译：提供半导体器件和制造该器件的方法。该方法可以包括形成覆盖在单晶半导体区域的主表面上的栅极导体并且在栅极导体的暴露的壁上形成第一间隔物。使用栅极导体和第一间隔物作为掩模，至少延伸区域注入到半导体区域中，并且形成从第一间隔物向外延伸的虚设间隔物。使用虚拟间隔件作为掩模，半导体区域被蚀刻以形成具有从主表面向底表面向下延伸的至少基本上直的壁的凹槽，使得在底表面和壁之间限定大的角度。随后，通过在凹槽内外延生长应力单晶半导体材料的区域来继续该过程。然后去除虚拟间隔物，并且可以通过形成至少部分地设置在受应力的半导体材料区域中的晶体管的源极/漏极区域来完成晶体管。

13. 发明申请

US20110183486A1 TRANSISTOR HAVING V-SHAPED EMBEDDED STRESSOR 有权
标题翻译：具有V形嵌入式应力的晶体管
公开(公告)号：US20110183486A1
公开(公告)日：2011-07-28
申请号：US12692859
申请日：2010-01-25
申请人： Kevin K. Chan , Brian J. Greene , Judson R. Holt , Jeffrey B. Johnson , Thomas S. Kanarsky , Jophy S. Koshy , Kevin McStay , Dae-Gyu Park , Johan W. Weijtmans , Frank B. Yang
发明人： Kevin K. Chan , Brian J. Greene , Judson R. Holt , Jeffrey B. Johnson , Thomas S. Kanarsky , Jophy S. Koshy , Kevin McStay , Dae-Gyu Park , Johan W. Weijtmans , Frank B. Yang
IPC分类号： H01L21/336
CPC分类号： H01L29/165 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A semiconductor device and a method of making the device are provided. The method can include forming a gate conductor overlying a major surface of a monocrystalline semiconductor region and forming first spacers on exposed walls of the gate conductor. Using the gate conductor and the first spacers as a mask, at least extension regions are implanted in the semiconductor region and dummy spacers are formed extending outward from the first spacers. Using the dummy spacers as a mask, the semiconductor region is etched to form recesses having at least substantially straight walls extending downward from the major surface to a bottom surface, such that a substantial angle is defined between the bottom surface and the walls. Subsequently, the process is continued by epitaxially growing regions of stressed monocrystalline semiconductor material within the recesses. Then the dummy spacers are removed and the transistor can be completed by forming source/drain regions of the transistor that are at least partially disposed in the stressed semiconductor material regions.
摘要翻译：提供半导体器件和制造该器件的方法。该方法可以包括形成覆盖在单晶半导体区域的主表面上的栅极导体并且在栅极导体的暴露的壁上形成第一间隔物。使用栅极导体和第一间隔物作为掩模，至少延伸区域注入到半导体区域中，并且形成从第一间隔物向外延伸的虚设间隔物。使用虚拟间隔件作为掩模，半导体区域被蚀刻以形成具有从主表面向底表面向下延伸的至少基本上直的壁的凹槽，使得在底表面和壁之间限定大的角度。随后，通过在凹槽内外延生长应力单晶半导体材料的区域来继续该过程。然后去除虚拟间隔物，并且可以通过形成至少部分地设置在受应力的半导体材料区域中的晶体管的源极/漏极区域来完成晶体管。

14. 发明授权

US07871893B2 Method for non-selective shallow trench isolation reactive ion etch for patterning hybrid-oriented devices compatible with high-performance highly-integrated logic devices 失效
标题翻译：用于非选择性浅沟槽隔离反应离子蚀刻的方法，用于图案化与高性能高度集成逻辑器件兼容的混合取向器件
公开(公告)号：US07871893B2
公开(公告)日：2011-01-18
申请号：US12020887
申请日：2008-01-28
申请人： Gregory Costrini , David M. Dobuzinsky , Thomas S. Kanarsky , Munir D. Naeem , Christopher D. Sheraw , Richard Wise
发明人： Gregory Costrini , David M. Dobuzinsky , Thomas S. Kanarsky , Munir D. Naeem , Christopher D. Sheraw , Richard Wise
IPC分类号： H01L21/76 , H01L21/763
CPC分类号： H01L29/045 , H01L21/76224
摘要： Disclosed are embodiments of a hybrid-orientation technology (HOT) wafer and a method of forming the HOT wafer with improved shallow trench isolation (STI) structures for patterning devices in both silicon-on-insulator (SOI) regions, having a first crystallographic orientation, and bulk regions, having a second crystallographic orientation. The improved STI structures are formed using a non-selective etch process to ensure that all of the STI structures and, particularly, the STI structures at the SOI-bulk interfaces, each extend to the semiconductor substrate and have an essentially homogeneous (i.e., single material) and planar (i.e., divot-free) bottom surface that is approximately parallel to the top surface of the substrate. Optionally, an additional selective etch process can be used to extend the STI structures a predetermined depth into the substrate.
摘要翻译：公开了混合取向技术（HOT）晶片的实施例以及形成具有改进的浅沟槽隔离（STI）结构的HOT晶片的方法，用于在绝缘体上硅（SOI）区域中图案化器件，具有第一晶体取向和具有第二结晶取向的体区。使用非选择性蚀刻工艺形成改进的STI结构，以确保所有STI结构，特别是SOI-体界面处的STI结构各自延伸到半导体衬底并且具有基本均匀的（即，单个材料）和大致平行于衬底的顶表面的平面（即，无自由）底表面。可选地，可以使用附加的选择性蚀刻工艺来将STI结构延伸到衬底中的预定深度。

15. 发明授权

US07250658B2 Hybrid planar and FinFET CMOS devices 有权
标题翻译：混合平面和FinFET CMOS器件
公开(公告)号：US07250658B2
公开(公告)日：2007-07-31
申请号：US11122193
申请日：2005-05-04
申请人： Bruce B. Doris , Diane C. Boyd , Meikei Leong , Thomas S. Kanarsky , Jakub T. Kedzierski , Min Yang
发明人： Bruce B. Doris , Diane C. Boyd , Meikei Leong , Thomas S. Kanarsky , Jakub T. Kedzierski , Min Yang
IPC分类号： H01L29/772
CPC分类号： H01L27/1211 , H01L21/845 , H01L29/66795 , H01L29/785
摘要： The present invention provides an integrated semiconductor circuit containing a planar single gated FET and a FinFET located on the same SOI substrate. Specifically, the integrated semiconductor circuit includes a FinFET and a planar single gated FET located atop a buried insulating layer of an silicon-on-insulator substrate, the planar single gated FET is located on a surface of a patterned top semiconductor layer of the silicon-on-insulator substrate and the FinFET has a vertical channel that is perpendicular to the planar single gated FET. A method of forming a method such an integrated circuit is also provided. In the method, resist imaging and a patterned hard mask are used in trimming the width of the FinFET active device region and subsequent resist imaging and etching are used in thinning the thickness of the FET device area. The trimmed active FinFET device region is formed such that it lies perpendicular to the thinned planar single gated FET device region.
摘要翻译：本发明提供一种集成半导体电路，其包含位于同一SOI衬底上的平面单栅极FET和FinFET。具体地，集成半导体电路包括FinFET和位于绝缘体上硅衬底的掩埋绝缘层顶上的平面单栅极FET，平面单门控FET位于硅 - 硅绝缘体的图案化顶部半导体层的表面上，绝缘体上的衬底和FinFET具有垂直于平面单门控FET的垂直沟道。还提供了一种形成集成电路的方法。在该方法中，抗蚀剂成像和图案化的硬掩模用于修整FinFET有源器件区域的宽度，并且随后的抗蚀剂成像和蚀刻用于减薄FET器件区域的厚度。经修整的有源FinFET器件区域形成为垂直于薄化的平面单栅极FET器件区域。

16. 发明授权

US07018891B2 Ultra-thin Si channel CMOS with improved series resistance 有权
标题翻译：超薄Si沟道CMOS，具有改善的串联电阻
公开(公告)号：US07018891B2
公开(公告)日：2006-03-28
申请号：US10735736
申请日：2003-12-16
申请人： Bruce B. Doris , MeiKei Ieong , Thomas S. Kanarsky
发明人： Bruce B. Doris , MeiKei Ieong , Thomas S. Kanarsky
IPC分类号： H01L21/00
CPC分类号： H01L27/1203 , H01L21/823814 , H01L21/84
摘要： Thin silicon channel SOI devices provide the advantage of sharper sub-threshold slope, high mobility, and better short-channel effect control but exhibit a typical disadvantage of increased series resistance. This high series resistance is avoided by using a raised source-drain (RSD), and expanding the source drain on the pFET transistor in the CMOS pair using selective epitaxial Si growth which is decoupled between nFETs and pFETs. By doing so, the series resistance is improved, the extensions are implanted after RSD formation and thus not exposed to the high thermal budget of the RSD process while the pFET and nFET can achieve independent effective offsets.
摘要翻译：薄硅沟道SOI器件具有更清晰的子阈值斜率，高迁移率和更好的短沟道效应控制的优点，但呈现增加串联电阻的典型缺点。通过使用升高的源极 - 漏极（RSD）和使用在nFET和pFET之间去耦合的选择性外延Si生长来扩展CMOS对中的pFET晶体管上的源极漏极来避免该高串联电阻。通过这样做，串联电阻得到改善，扩展在RSD形成后植入，因此不暴露于RSD工艺的高热预算，而pFET和nFET可以实现独立的有效偏移。

17. 发明授权

US06914303B2 Ultra thin channel MOSFET 有权
公开(公告)号：US06914303B2
公开(公告)日：2005-07-05
申请号：US10650229
申请日：2003-08-28
申请人： Bruce B. Doris , Thomas S. Kanarsky , Ying Zhang , Huilong Zhu , Meikei Ieong , Omer Dokumaci
发明人： Bruce B. Doris , Thomas S. Kanarsky , Ying Zhang , Huilong Zhu , Meikei Ieong , Omer Dokumaci
IPC分类号： H01L21/336 , H01L21/84 , H01L27/12 , H01L29/786 , H01L27/01
CPC分类号： H01L29/66772 , H01L21/84 , H01L27/1203 , H01L29/6656 , H01L29/78612 , H01L29/78621
摘要： Described is a method for making thin channel silicon-on-insulator structures. The inventive method comprises forming a set of thin spacer abutting a gate region in a first device and a second device region; forming a raised source/drain region on either side of the gate region in the first device region and the second device region, implanting dopants of a first conductivity type into the raised source drain region in the first device region to form a first dopant impurity region, where the second device region is protected by a second device region block mask; implanting dopants of a second conductivity type into the raised source/drain region in the second device region to form a second dopant impurity region, where the first device region is protected by a first device region block mask; and activating the first dopant impurity region and the second dopant impurity region to provide a thin channel MOSFET.

18. 发明授权

US06846734B2 Method and process to make multiple-threshold metal gates CMOS technology 有权
标题翻译：制造多阈值金属门CMOS技术的方法与工艺
公开(公告)号：US06846734B2
公开(公告)日：2005-01-25
申请号：US10300165
申请日：2002-11-20
申请人： Ricky Amos , Katayun Barmak , Diane C. Boyd , Cyril Cabral, Jr. , Meikei Leong , Thomas S. Kanarsky , Jakub Tadeusz Kedzierski
发明人： Ricky Amos , Katayun Barmak , Diane C. Boyd , Cyril Cabral, Jr. , Meikei Leong , Thomas S. Kanarsky , Jakub Tadeusz Kedzierski
IPC分类号： H01L27/092 , H01L21/28 , H01L21/336 , H01L21/8238 , H01L21/84 , H01L21/3205 , H01L21/44 , H01L21/4763
CPC分类号： H01L21/823835 , H01L21/28097 , H01L21/823842 , H01L21/84 , H01L29/66545
摘要： Methods of forming complementary metal oxide semiconductor (CMOS) devices having multiple-threshold voltages which are easily tunable are provided. Total salicidation with a metal bilayer (representative of the first method of the present invention) or metal alloy (representative of the second method of the present invention) is provided. CMOS devices having multiple-threshold voltages provided by the present methods are also described.
摘要翻译：提供了形成具有易于调节的多阈值电压的互补金属氧化物半导体（CMOS）器件的方法。提供了用金属双层（代表本发明的第一种方法）或金属合金（代表本发明的第二种方法）的总的水杨酸化。还描述了通过本方法提供的具有多阈值电压的CMOS器件。

19. 发明授权

US06207493B1 Formation of out-diffused bitline by laser anneal 失效
公开(公告)号：US06207493B1
公开(公告)日：2001-03-27
申请号：US09136586
申请日：1998-08-19
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Thomas S. Kanarsky
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Thomas S. Kanarsky
IPC分类号： H01L218242
CPC分类号： H01L27/10885 , H01L21/2254 , H01L21/2257 , H01L21/268 , H01L21/743 , H01L27/10876
摘要： The present invention provides methods of forming an out-diffused bitline in a semiconductor substrate by utilizing a laser annealing step wherein the dopant material in the trench region is out-diffused into the semiconductor substrate. The out-diffused bitline can also be formed utilizing an ion implantation step.

20. 发明授权

US07211490B2 Ultra thin channel MOSFET 失效
标题翻译：超薄通道MOSFET
公开(公告)号：US07211490B2
公开(公告)日：2007-05-01
申请号：US11083743
申请日：2005-03-18
申请人： Bruce B. Doris , Thomas S. Kanarsky , Ying Zhang , Huilong Zhu , Meikei Ieong , Omer Dokumaci
发明人： Bruce B. Doris , Thomas S. Kanarsky , Ying Zhang , Huilong Zhu , Meikei Ieong , Omer Dokumaci
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L29/66772 , H01L21/84 , H01L27/1203 , H01L29/6656 , H01L29/78612 , H01L29/78621
摘要： Described is a method for making thin channel silicon-on-insulator structures. The inventive method comprises forming a set of thin spacer abutting a gate region in a first device and a second device region; forming a raised source/drain region on either side of the gate region in the first device region and the second device region, implanting dopants of a first conductivity type into the raised source drain region in the first device region to form a first dopant impurity region, where the second device region is protected by a second device region block mask; implanting dopants of a second conductivity type into the raised source/drain region in the second device region to form a second dopant impurity region, where the first device region is protected by a first device region block mask; and activating the first dopant impurity region and the second dopant impurity region to provide a thin channel MOSFET.
摘要翻译：描述了制造薄沟道硅绝缘体上结构的方法。本发明的方法包括在第一装置和第二装置区域中形成邻接栅极区的一组薄间隔件; 在第一器件区域和第二器件区域中的栅极区域的任一侧上形成凸起的源极/漏极区域，将第一导电类型的掺杂剂注入到第一器件区域中的凸起的源极漏极区域中以形成第一掺杂剂杂质区域，其中所述第二设备区域被第二设备区域块掩码保护; 将第二导电类型的掺杂剂注入所述第二器件区域中的所述升高的源极/漏极区域中以形成第二掺杂剂杂质区域，其中所述第一器件区域被第一器件区域阻挡掩模保护; 以及激活第一掺杂杂质区和第二掺杂杂质区，以提供薄沟道MOSFET。

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