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    • 13. 发明授权
    • Motor and it's manufacturing method
    • 电机及其制造方法
    • US08350421B2
    • 2013-01-08
    • US12352329
    • 2009-01-12
    • Takeshi Shimoyama
    • Takeshi Shimoyama
    • H02K37/00
    • H02K15/022H02K5/15H02K5/161Y10T29/49009
    • A motor may include a stator formed with a rotor arrangement hole, a rotor disposed in the rotor arrangement hole, and a plate-like member disposed on at least one end side in an axial direction of the stator. The plate-like member is joined with an end face of the stator structured such that a peripheral edge part of the plate-like member is melted. In this case, it is preferable that the peripheral edge part of the plate-like member is joined with the end face of the stator structured such that an edge part on an opposite side to a face contacting with the end face of the stator is melted by irradiation of a laser beam.
    • 电动机可以包括形成有转子布置孔的定子,设置在转子布置孔中的转子和设置在定子的轴向方向上的至少一个端侧的板状构件。 板状构件与定子的端面结合,使得板状构件的周缘部分熔化。 在这种情况下,优选的是,板状构件的周边部分与定子的端面结合,使得与与定子的端面接触的面相反侧的边缘部分熔化 通过照射激光束。
    • 15. 发明授权
    • Information processing device, method, and program
    • 信息处理装置,方法和程序
    • US07493508B2
    • 2009-02-17
    • US10527063
    • 2003-07-30
    • Takeshi Shimoyama
    • Takeshi Shimoyama
    • G06F13/00
    • G06F9/3869G06F7/00G06F2207/3884
    • This invention relates to an information processing apparatus as well as to an information processing method and a program for use therewith, the apparatus being arranged to prevent a drop in its processing performance while minimizing power dissipation when a frequency-variable synchronizing clock signal CLK of the apparatus is lowered in frequency. Illustratively, if a selector block 31-2 receives a selection command “select B” which is set depending on the frequency of the synchronizing clock signal CLK and which specifies the bypassing of a holding block 12-2, then data input to and held by a holding block 12-1 on a first clock pulse of the clock signal CLK is arranged, on a second clock pulse, to pass through a selector block 31-1 and a signal processing block 13-1, bypass the holding block 12-2, pass through the selector block 31-2 and a signal processing block 13-2, and be input to and held by a holding block 12-3. This invention applies to data processing apparatuses such as CPUs, DSPs and filters as well as to buses.
    • 本发明涉及一种信息处理设备以及信息处理方法和与其一起使用的程序,该设备被布置为在最小化功率耗散的同时防止其处理性能的下降,当该频率可变同步时钟信号CLK 设备的频率降低。 说明性地,如果选择器块31-2接收到根据同步时钟信号CLK的频率设定并且指定保持块12-2的旁路设置的选择命令“选择B”,则输入到和保持的数据 时钟信号CLK的第一时钟脉冲上的保持块12-1在第二时钟脉冲上被布置成通过选择器块31-1和信号处理块13-1,绕过保持块12-2 通过选择器块31-2和信号处理块13-2,并被保持块12-3输入并保持。 本发明适用于诸如CPU,DSP和滤波器以及总线的数据处理设备。
    • 16. 发明申请
    • INFORMATION PROCESSING APPARATUS WORKING AT VARIABLE OPERATING FREQUENCY
    • 信息处理设备在可变操作频率下工作
    • US20080075214A1
    • 2008-03-27
    • US11943092
    • 2007-11-20
    • Takeshi Shimoyama
    • Takeshi Shimoyama
    • G06F1/04G06F1/12G06F5/06
    • G06F13/4243
    • An information processing apparatus and an information processing method for use therewith are provided so as to implement optimal signal processing without deterioration of performance when using variable operating frequencies. A frequency information operating section (12) of the apparatus adds a corresponding signal cycle to frequency information Inf about a synchronizing clock signal CLKv having a variable frequency. An information processing section of the apparatus is supplied with the synchronizing clock signal as an operating clock signal, and processes information when results of the addition by the frequency information operating section (12) meet a predetermined condition. Optimized processing is thus accomplished in a manner eliminating wasteful latency times.
    • 提供一种使用它的信息处理装置和信息处理方法,以便在使用可变工作频率时实现最佳信号处理而不会降低性能。 设备的频率信息操作部分(12)将相应的信号周期添加到具有可变频率的同步时钟信号CLKv的频率信息Inf。 该装置的信息处理部分被提供有作为操作时钟信号的同步时钟信号,并且当频率信息操作部分(12)的相加结果达到预定条件时处理信息。 因此,以一种消除浪费的延迟时间的方式来实现优化的处理。
    • 17. 发明申请
    • Data transfer device and data transfer system
    • 数据传输设备和数据传输系统
    • US20070233921A1
    • 2007-10-04
    • US11724056
    • 2007-03-14
    • Shigetoshi SugiyamaTakeshi Shimoyama
    • Shigetoshi SugiyamaTakeshi Shimoyama
    • G06F13/00
    • G06F13/1605G06F13/362
    • Disclosed herein is a data transfer device to which a master device that issues transfer requests and slave devices each having a function of responding to the transfer request may be connected. The device may include a transfer request counter that counts up or down each time a response signal is inputted thereto from any slave device, and counts down or up each time a data transfer completion signal is inputted thereto; a transfer destination selector that, based on a count value of the counter and information concerning a transfer-target slave device, determines and selects one of the slave devices as a destination of the transfer request, and connects the master device with the selected slave device; and a data transfer monitoring section that monitors completion of data transfer corresponding to the transfer request and, upon recognizing the completion, outputs the data transfer completion signal to the counter.
    • 这里公开了一种数据传送装置,可以连接发出传送请求的主设备和各自具有响应于传送请求的功能的从设备。 该设备可以包括每次从任何从设备向其输入响应信号时向上或向下进行计数的传送请求计数器,并且每次输入数据传送完成信号时都向下或向上计数; 转移目的地选择器,其基于计数器的计数值和关于转移对象从设备的信息,确定并选择一个从设备作为传送请求的目的地,并将主设备与所选择的从设备 ; 以及数据传送监视部分,其监视与传送请求相对应的数据传输的完成,并且在识别完成时,将数据传送完成信号输出到计数器。
    • 18. 发明申请
    • Frequency control apparatus, information processing apparatus and program
    • 频率控制装置,信息处理装置及程序
    • US20060212247A1
    • 2006-09-21
    • US10552897
    • 2004-05-07
    • Takeshi ShimoyamaTetsumasa MeguroTsutomu TeranishiYasuo NakanoHirokazu Kawahara
    • Takeshi ShimoyamaTetsumasa MeguroTsutomu TeranishiYasuo NakanoHirokazu Kawahara
    • G01R35/00
    • G06F1/324G06F1/3203H03L7/06H03L7/07H03L7/0991H03L7/16Y02D10/126
    • A frequency control apparatus and an information processing apparatus are disclosed wherein it is possible, in control of an operation frequency of a control object performed in response to a result of observation of an operation state of the control object, to limit the operation frequency or designate an allowable value or the like to achieve improvement in performance and power-saving. The frequency control apparatus (1) includes an observation section (3) for observing an operation state of a control object (2) which operates with a variably controlled frequency, a frequency determination section (4) for determining a clock frequency in response to the operation state, and a frequency limitation section (5) for limiting a range or a value of the clock frequency determined by the frequency determination section (4). If the frequency determined in response to the operation state of the control object (2) is within an allowable range, the control is performed with the frequency, but if the frequency is outside the allowable range, the frequency is limited to the range.
    • 公开了一种频率控制装置和信息处理装置,其中在控制对应于控制对象的操作状态的观察结果而执行的控制对象的操作频率的情况下,可以限制操作频率或指定 允许值等来实现性能和功率节省的改善。 频率控制装置(1)包括用于观察以可变控制频率工作的控制对象(2)的操作状态的观察部(3),响应于该频率判定部确定时钟频率的频率判定部(4) 操作状态,以及用于限制由频率确定部分(4)确定的时钟频率的范围或值的频率限制部分(5)。 如果响应于控制对象(2)的操作状态而确定的频率在容许范围内,则以频率进行控制,但是如果频率在允许范围之外,则频率被限制在该范围内。
    • 19. 发明授权
    • Data processing apparatus and data processing method
    • 数据处理装置及数据处理方法
    • US08707057B2
    • 2014-04-22
    • US13237317
    • 2011-09-20
    • Kazuyoshi FurukawaTakeshi ShimoyamaMasahiko Takenaka
    • Kazuyoshi FurukawaTakeshi ShimoyamaMasahiko Takenaka
    • G06F11/30G06F12/14
    • H04L9/002H04L9/06H04L2209/12
    • A data processing apparatus includes an address bus, a scramble unit, and a data bus. The address bus outputs address data to be given to a memory apparatus. The scramble unit scrambles write-in data into a storage position in the memory apparatus identified by the address data to obtain confidential data. The data bus outputs the confidential data. The scramble unit includes a first scrambler, a first converter and a second scrambler. The first scrambler XORs first mask data corresponding to the address data and the write-in data for each bit and makes it first scrambled data. The first converter performs one-to-one substitution conversion of the first scrambled data. The second scrambler XORs second mask data corresponding to the address data and data after the conversion of the first scrambled data by the first converter and outputs obtained second scrambled data as the confidential data.
    • 数据处理装置包括地址总线,加扰单元和数据总线。 地址总线输出要提供给存储装置的地址数据。 加扰单元将写入数据加密到由地址数据识别的存储装置中的存储位置,以获得机密数据。 数据总线输出机密数据。 加扰单元包括第一加扰器,第一转换器和第二加扰器。 第一加扰器将对应于地址数据的第一掩码数据和每个位的写入数据进行异或,并使其成为第一个加扰数据。 第一转换器执行第一加扰数据的一对一替换转换。 第二加扰器将对应于地址数据的第二掩码数据和由第一转换器转换第一加扰数据之后的数据进行异或,并将获得的第二加密数据作为机密数据输出。
    • 20. 发明申请
    • DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD
    • 数据处理设备和数据处理方法
    • US20120008782A1
    • 2012-01-12
    • US13237317
    • 2011-09-20
    • Kazuyoshi FURUKAWATakeshi ShimoyamaMasahiko Takenaka
    • Kazuyoshi FURUKAWATakeshi ShimoyamaMasahiko Takenaka
    • H04L9/20
    • H04L9/002H04L9/06H04L2209/12
    • A data processing apparatus includes an address bus, a scramble unit, and a data bus. The address bus outputs address data to be given to a memory apparatus. The scramble unit scrambles write-in data into a storage position in the memory apparatus identified by the address data to obtain confidential data. The data bus outputs the confidential data. The scramble unit includes a first scrambler, a first converter and a second scrambler. The first scrambler XORs first mask data corresponding to the address data and the write-in data for each bit and makes it first scrambled data. The first converter performs one-to-one substitution conversion of the first scrambled data. The second scrambler XORs second mask data corresponding to the address data and data after the conversion of the first scrambled data by the first converter and outputs obtained second scrambled data as the confidential data.
    • 数据处理装置包括地址总线,加扰单元和数据总线。 地址总线输出要提供给存储装置的地址数据。 加扰单元将写入数据加密到由地址数据识别的存储装置中的存储位置,以获得机密数据。 数据总线输出机密数据。 加扰单元包括第一加扰器,第一转换器和第二加扰器。 第一加扰器将对应于地址数据的第一掩码数据和每个位的写入数据进行异或,并使其成为第一个加扰数据。 第一转换器执行第一加扰数据的一对一替换转换。 第二加扰器将对应于地址数据的第二掩码数据和由第一转换器转换第一加扰数据之后的数据进行异或,并将获得的第二加密数据作为机密数据输出。