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11. 发明专利

DE602004018663D1 未知
公开(公告)号：DE602004018663D1
公开(公告)日：2009-02-05
申请号：DE602004018663
申请日：2004-09-21
申请人： SANDISK CORP
发明人： QUADER KHANDKER N , CERNEA RAUL-ADRIAN
IPC分类号： G11C16/14 , G11C11/34 , G11C16/04 , G11C16/16 , G11C16/34
摘要： A non-volatile memory and method for its operation that can reduce the amount of disturb in non-selected cells during an erase process are presented. For a set of storage elements formed over a common well structure, all word-lines are initially charged with the same high voltage erase signal that charges the well to insure there is no net voltage difference between the well and word-lines. The selected word-lines are then discharged to ground while the non-selected word-lines and the well are maintained at the high voltage. This can be accomplished without increasing any pitch area circuit or adding new wires in the memory array, and at minimal additional peripheral area. Advantages include less potential erase disturb in the non-selected storage elements and a tighter erase distribution for the selected elements.

12. 发明专利

ES2262014T3 TECNICAS PARA REDUCIR LOS EFECTOS DE LAS UNIONES ENTRE ELEMENTOS DE ALMACENAJE DE FILAS ADYACENTES DE CELULAS DE MEMORIA. 未知
公开(公告)号：ES2262014T3
公开(公告)日：2006-11-16
申请号：ES03794474
申请日：2003-08-13
申请人： SANDISK CORP
发明人： CERNEA RAUL-ADRIAN , QUADER KHANDKER N , LI YAN , CHEN JIAN , FONG YUPIN
IPC分类号： G11C16/02 , G11C11/56 , G11C16/10 , G11C16/34 , G11C16/04
摘要： Un método para operar una matriz de células de memoria no volátil que almacena datos como diferentes niveles de carga en elementos de almacenamiento de carga, en donde entre los grupos adyacentes de los elementos de almacenamiento de carga existe acoplamiento de campo: programar datos en un primer grupo (35) de los elementos de almacenamiento de la carga con un primer juego de niveles de almacenamiento (VL) junto con una indicación TB=L de que se ha usado el primer juego de niveles de almacenamiento, a continuación programar datos en un segundo grupo (39) de los elementos de almacenamiento de carga con el primer juego de niveles de almacenamiento junto con una indicación de que se ha usado el primer juego de niveles de almacenamiento, y a continuación aumentar los niveles de carga del primero (35) de los grupos de elementos de almacenamiento de carga desde el primer juego de niveles de almacenamiento hasta un segundo juego de niveles de almacenamiento y almacenar una indicación (TB=H) de que se ha usado el segundo juego de niveles de almacenamiento.

13. 发明专利

AT321339T 未知
公开(公告)号：AT321339T
公开(公告)日：2006-04-15
申请号：AT03794474
申请日：2003-08-13
申请人： SANDISK CORP
发明人： CERNEA RAUL-ADRIAN , QUADER KHANDKER N , LI YAN , CHEN JIAN , FONG YUPIN
IPC分类号： G11C16/02 , G11C11/56 , G11C16/10 , G11C16/34 , G11C16/04
摘要： Techniques of reducing erroneous readings of the apparent charge levels stored in a number of rows of memory cells on account of capacitive coupling between the cells. All pages of a first row are programmed with a first pass, followed by programming all pages of a second adjacent row with a first pass, after which the first row is programmed with a second pass, and then all pages of a third row are programmed with a first pass, followed by returning to program the second row with a second pass, and so on, in a back-and-forth manner across the rows of an array. This minimizes the effect on the apparent charge stored on rows of memory cells that can occur by later writing data into adjacent rows of memory cells.

14. 发明专利

AU2003262675A1 TECHNIQUES FOR REDUCING EFFECTS OF COUPLING BETWEEN STORAGE ELEMENTS OF ADJACENT ROWS OF MEMORY CELLS 未知
公开(公告)号：AU2003262675A1
公开(公告)日：2004-03-29
申请号：AU2003262675
申请日：2003-08-13
申请人： SANDISK CORP
发明人： QUADER KHANDKER N , LI YAN , CHEN JIAN , FONG YUPIN , CERNEA RAUL-ADRIAN
IPC分类号： G11C16/02 , G11C11/56 , G11C16/10 , G11C16/34 , G11C16/04
摘要： Techniques of reducing erroneous readings of the apparent charge levels stored in a number of rows of memory cells on account of capacitive coupling between the cells. All pages of a first row are programmed with a first pass, followed by programming all pages of a second adjacent row with a first pass, after which the first row is programmed with a second pass, and then all pages of a third row are programmed with a first pass, followed by returning to program the second row with a second pass, and so on, in a back-and-forth manner across the rows of an array. This minimizes the effect on the apparent charge stored on rows of memory cells that can occur by later writing data into adjacent rows of memory cells.

15. 发明专利

AU2002359496A1 METHOD AND SYSTEM FOR PROGRAMMING AND INHIBITING MULTI-LEVEL, NON-VOLATILE MEMORY CELLS 未知
公开(公告)号：AU2002359496A1
公开(公告)日：2003-06-30
申请号：AU2002359496
申请日：2002-11-26
申请人： SANDISK CORP
发明人： QUADER KHANDKER N , NGUYEN KHANH T , PAN FENG , PHAM LONG C , MAK ALEXANDER K
IPC分类号： G11C16/02 , G11C11/56 , G11C16/04 , G11C16/06 , G11C7/00
摘要： A multi-level non-volatile memory cell programming/lockout method and system are provided. The programming/lockout method and system advantageously prevent memory cells that charge faster than other memory cells from being over-programmed.

16. 发明专利

AU6976701A Multiple output current mirror with improved accuracy 未知
公开(公告)号：AU6976701A
公开(公告)日：2001-12-24
申请号：AU6976701
申请日：2001-06-08
申请人： SANDISK CORP
发明人： QUADER KHANDKER N , HUYNH SHARON Y
IPC分类号： H03F3/343 , G11C7/02 , G11C11/56 , G11C27/00 , H03F3/00
摘要： A multiple output current mirror of improved accuracy suitable for use in a multi-level memory or analog applications is described. A reference current is mirrored in number of branches to produce replicas of the original current without degrading the original current. Both the mirrored transistor, through which the original current flows, and the mirroring transistors, which provide the replicated currents in each of the branches, are subdivided into a number of separate transistors. The effective channel width of a corresponding original transistor is shared among the transistors forming its subdivision. These subdivided elements are then physically arranged into a number partial current mirrors whose outputs are combined to form the total current mirror. By altering the physical arrangement of the pieces from one partial mirror to the next, variations in operating characteristics and manufacturing processes that are dependent upon positions are reduced since the variation in one partial mirror offsets that in another partial mirror. In an exemplary embodiment, the mirrored element, producing the reference current, and the mirroring elements in each of k branches are each composed of N transistors with a width w, giving an effective width W=Nw for each element and consequently a mirroring ration of 1 for all the branches. All of these N(k+1) transistors are physical placed in a linear arrangement of N partial current mirrors of (k+1) transistors each, where each partial mirror contains a transistor supplying part of the mirrored current and one transistor from each of the k branches mirroring it. Each of the N partial mirrors has its (k+1) elements arranged in a different permutation. The N=5, k=3 case is described in some detail.

17. 发明申请

WO02058073A2 METHOD OF REDUCING DISTURBS IN NON-VOLATILE MEMORY 审中-公开
标题翻译：减少非易失性存储器中的干扰的方法
公开(公告)号：WO02058073A2
公开(公告)日：2002-07-25
申请号：PCT/US0150168
申请日：2001-10-26
申请人： SANDISK CORP
发明人： MANGAN JOHN S , GUTERMAN DANIEL C , SAMACHISA GEORGE , MURPHY BRIAN , WANG CHI-MING , QUADER KHANDKER N
IPC分类号： G11C16/02 , G11C16/12 , G11C16/00
CPC分类号： G11C7/12 , G11C16/12 , G11C16/3427 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50012 , G11C2029/1204
摘要： In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in distrubs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selected the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these. In a second, complementary aspect, the rate at which the voltage levels on the bit lines are changed is adjustable. By monitoring the frequency of disturbs, or based upon the device's application, the rate at which the bit line drives change the bit line voltage can be adjusted. This can be implemented by setting the rate externally, or by the controller based upon device performance and the amount of data error being generated.
摘要翻译：在非易失性存储器中，当阵列位线上的电压电平发生变化时，在未选择的字线中产生的位移电流可导致分配。提出了减少这些电流的技术。在第一方面，减少了在字线上同时编程的单元的数量。在非易失性存储器中，存储器单元阵列由多个单元组成，并且单元被组合成共享公共字线的平面，避免同一平面内的单元的同时编程。多个单元可以并行编程，但是它们被布置成处于分开的平面中。这通过选择要并行编程的单元数量和它们的顺序来完成，使得所有编程在一起的单元都是来自不同的平面，通过比较要编程的单元以查看是否来自同一平面，或者组合这些。在第二个互补方面，位线上的电压电平改变的速率是可调节的。通过监视干扰的频率，或者基于设备的应用，可以调整位线驱动器改变位线电压的速率。这可以通过外部设置速率或由控制器基于设备性能和产生的数据错误量来实现。

18. 发明申请

WO0197373A3 MULTIPLE OUTPUT CURRENT MIRROR WITH IMPROVED ACCURACY 审中-公开
标题翻译：具有改进精度的多输出电流镜
公开(公告)号：WO0197373A3
公开(公告)日：2002-05-30
申请号：PCT/US0118578
申请日：2001-06-08
申请人： SANDISK CORP
发明人： QUADER KHANDKER N , HUYNH SHARON Y
IPC分类号： H03F3/343 , G11C7/02 , G11C11/56 , G11C27/00 , G05F3/26
CPC分类号： G11C27/005 , G11C11/5621 , G11C11/5642 , G11C2211/5634 , G11C2211/5645
摘要： A multiple output current mirror of improved accuracy suitable for use in a multi-level memory or analog applications is described. A reference current is mirrored in number of branches to produce replicas of the original current without degrading the original current. Both the mirrored transistor, through which the original current flows, and the mirroring transistors, which provide the replicated currents in each of the branches, are subdivided into a number of separate transistors. The effective channel width of a corresponding original transistor is shared among the transistors forming its subdivision. These subdivided elements are then physically arranged into a number partial current mirrors whose outputs are combined to form the total current mirror. By altering the physical arrangement of the pieces from one partial mirror to the next, variations in operating characteristics and manufacturing processes that are dependent upon positions are reduced since the variation in one partial mirror offsets that in another partial mirror.
摘要翻译：描述了适用于多级存储器或模拟应用的改进精度的多输出电流镜。参考电流以分支数量进行镜像，以产生原始电流的副本，而不会降低原始电流。原始电流流过的镜像晶体管和在每个分支中提供复制电流的镜像晶体管都被细分为多个独立的晶体管。相应的原始晶体管的有效沟道宽度在形成其细分的晶体管中共享。然后将这些细分的元件物理地排列成多个部分电流镜，其输出被组合以形成总电流镜。通过将件从一个局部反射镜改变到下一个部分反射镜的物理布置，减少了依赖于位置的操作特性和制造过程的变化，因为一个部分反射镜的变化抵消了另一部分反射镜中的变化。

19. 发明公开

EP1456852A4 METHOD AND SYSTEM FOR PROGRAMMING AND INHIBITING MULTI-LEVEL, NON-VOLATILE MEMORY CELLS 有权
标题翻译：方法和系统编程和阻断非挥发性记忆体单元包含多个层次
公开(公告)号：EP1456852A4
公开(公告)日：2005-12-21
申请号：EP02794038
申请日：2002-11-26
申请人： SANDISK CORP
发明人： QUADER KHANDKER N , NGUYEN KHANH T , PAN FENG , PHAM LONG C , MAK ALEXANDER K
IPC分类号： G11C16/02 , G11C11/56 , G11C16/04 , G11C7/00 , G11C16/06
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/3486
摘要： A multi-level non-volatile memory cell programming/lockout method and system (100) are provided. The non-volatile memory cell comprising a first set of one or more memory cells selected to store a charge equal or greater than a first predetermined charge level (504), a second set of one or more memory cells selected tos tore a charge equal or greater than a second predetermined charge level, the memory device is configured to simultaneously program the first and second sets of memory cells and inhibit progamming of any memory cell that reaches or exceeds the first predetermined charge level until all memory cells in the first set have reached or exceeded the first predetermined charge level.

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