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11. 发明授权

US07672803B1 Input of test conditions and output generation for built-in self test 有权
标题翻译：输入测试条件和输出产生内置自检
公开(公告)号：US07672803B1
公开(公告)日：2010-03-02
申请号：US11006034
申请日：2004-12-07
申请人： Mimi Lee , Darlene Hamilton , Ken Cheong Cheah
发明人： Mimi Lee , Darlene Hamilton , Ken Cheong Cheah
IPC分类号： G01R27/28
CPC分类号： G11C29/16 , G01R31/318511 , G11C16/04 , G11C29/12005 , G11C29/44
摘要： A system and method is discussed for providing programmable test conditions for a built-in self test circuit of a flash memory device. The present invention employs a flash memory having BIST circuit for testing the memory and a BIST interface circuit adapted to adjust the test conditions of the memory tests. The BIST interface circuit is operable to receive one or more global variables associated with the test conditions of a plurality of tests used on the flash memory and to output results of the memory tests based on the value of the variables. The global variables are used to adjust the test conditions and to trim one or more references used in various flash memory tests and operations. The system may further include a serial communications medium for communicating the global variables to the BIST interface and test results from the interface.
摘要翻译：讨论了一种用于为闪存器件的内置自测电路提供可编程测试条件的系统和方法。本发明采用具有用于测试存储器的BIST电路的闪速存储器和适于调整存储器测试的测试条件的BIST接口电路。 BIST接口电路可操作以接收与闪存上使用的多个测试的测试条件相关联的一个或多个全局变量，并且基于变量的值输出存储器测试的结果。全局变量用于调整测试条件并修剪用于各种闪存测试和操作的一个或多个引用。该系统还可以包括用于将全局变量传送到BIST接口的串行通信介质以及来自接口的测试结果。

12. 发明授权

US07284167B2 Automated tests for built-in self test 有权
标题翻译：自动测试内置自检
公开(公告)号：US07284167B2
公开(公告)日：2007-10-16
申请号：US11041608
申请日：2005-01-24
申请人： Mimi Lee , Darlene Hamilton , Ken Cheong Cheah , Kendra Nguyen , Xin Guo
发明人： Mimi Lee , Darlene Hamilton , Ken Cheong Cheah , Kendra Nguyen , Xin Guo
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/021 , G11C16/04 , G11C29/02 , G11C29/028 , G11C29/1201 , G11C29/16
摘要： A method is discussed for providing programmable test conditions for a built-in self test circuit of a flash memory device. The method comprises providing a BIST interface adapted to adjust a test condition used in a BIST circuit, providing the memory cells of the Flash memory device, and providing the BIST circuit adapted to test the flash memory. The method further comprises communicating with the BIST interface one or more global variables associated with the test condition, adjusting the test condition used by the BIST circuit based on the values represented by the global variables, performing one or more test operations on the flash memory in accordance with the adjusted test condition, and reporting the results of the memory test operations. The method of the present invention may further include a serial communications medium and the use of a serial test protocol for communicating the global variables to the BIST interface and test results from the interface. The global variables may also be provided by a memory device user.
摘要翻译：讨论了一种用于为闪存设备的内置自测电路提供可编程测试条件的方法。该方法包括提供BIST接口，其适于调整在BIST电路中使用的测试条件，提供闪存设备的存储单元，以及提供适于测试闪速存储器的BIST电路。该方法还包括与BIST接口通信与测试条件相关联的一个或多个全局变量，基于由全局变量表示的值来调整由BIST电路使用的测试条件，对闪速存储器执行一个或多个测试操作根据调整的测试条件，并记录测试操作的结果。本发明的方法还可以包括串行通信介质和使用串行测试协议来将全局变量传送到BIST接口并从接口测试结果。全局变量也可由存储器设备用户提供。

13. 发明授权

US07415646B1 Page—EXE erase algorithm for flash memory 有权
标题翻译：闪存的Page-EXE擦除算法
公开(公告)号：US07415646B1
公开(公告)日：2008-08-19
申请号：US10946812
申请日：2004-09-22
申请人： Mimi Lee , Darlene Hamilton , Ken Cheong Cheah
发明人： Mimi Lee , Darlene Hamilton , Ken Cheong Cheah
IPC分类号： G01R31/28
CPC分类号： G11C16/344 , G11C16/04 , G11C16/16 , G11C16/3445 , G11C29/50004 , G11C29/52 , G11C2216/18
摘要： Methods of performing a sector erase of flash memory devices incorporating built-in self test circuitry are provided. The present invention employs an interactive verification and sector erase algorithm to verify and repeatedly erase the sector until a portion of the groups of each page of the sector are erased or a first maximum number of erase pulses is achieved. The algorithm further includes a word verification and erase operation that sequentially verifies and erases each word of the sector until each word is erased or a second maximum number of erase pulses is achieved. The second maximum number of erase pulses may be based on a function of the first maximum number of erase pulses. The second maximum number of erase pulses may be input to the sector erase algorithm as a multi-bit code. The second maximum number of erase pulses and conversion of the multi-bit code may be based on a binary multiple of the first maximum number of erase pulses.
摘要翻译：提供了包含内置自测电路的闪存器件的扇区擦除方法。本发明使用交互验证和扇区擦除算法来验证并重复地擦除扇区，直到扇区的每一页的一部分组被擦除或实现了第一最大数目的擦除脉冲。该算法还包括一个字验证和擦除操作，其顺序地验证和擦除扇区的每个字，直到每个字被擦除或者实现第二个最大数量的擦除脉冲。第二最大擦除脉冲数可以基于第一最大数量的擦除脉冲的函数。擦除脉冲的第二个最大数量可以作为多位代码输入到扇区擦除算法。擦除脉冲的第二个最大数量和多位代码的转换可以基于第一最大数量的擦除脉冲的二进制数。

14. 发明授权

US06891752B1 System and method for erase voltage control during multiple sector erase of a flash memory device 有权
标题翻译：闪存器件的多扇区擦除期间擦除电压控制的系统和方法
公开(公告)号：US06891752B1
公开(公告)日：2005-05-10
申请号：US10210378
申请日：2002-07-31
申请人： Edward V. Bautista , Ken Cheong Cheah , Weng Fook Lee
发明人： Edward V. Bautista , Ken Cheong Cheah , Weng Fook Lee
IPC分类号： G11C16/16 , G11C16/34 , G11C16/04
CPC分类号： G11C16/3472 , G11C16/16 , G11C16/344
摘要： A method for erasing a flash memory. In a flash memory device having multiple sectors a plurality of sectors is selected for erase (810). a subset of sectors is selected (815) and an erase pulse is applied simultaneously to all sectors in the subset (820). After the application of an erase pulse having an initial voltage value, at least one sector of the subset is verified (825). If there is at least one unerased cell in the verified sector, the erase voltage is adjusted (830) and another erase pulse is applied to the subset of sectors (820). The adjustment of the erase voltage may be a function of the number of times that an erase pulse has been applied to the subset. This cycle is repeated on the subset until the selected sector is verified as erased. After a sector is verified, the erase/verify cycle is applied to one or more of the remaining sectors in the subset until each of the remaining sectors has been verified as erased. After all of the sectors in the subset are erased, the erase voltage is reset to its initial value (840) and another subset of sectors is selected for erase/verify as described above (815). The process may be repeated until all of the memory sectors in the device have been erased (850). A flash memory device with embedded logic may be used to execute the method.
摘要翻译：一种擦除闪存的方法。在具有多个扇区的快闪存储器件中，选择多个扇区用于擦除（810）。选择扇区的子集（815），并且将消除脉冲同时应用于子集（820）中的所有扇区。在施加具有初始电压值的擦除脉冲之后，验证该子集的至少一个扇区（825）。如果在验证扇区中存在至少一个未故障单元，则调整擦除电压（830），并向扇区子集（820）施加另一擦除脉冲。擦除电压的调整可以是将擦除脉冲施加到子集的次数的函数。在子集上重复该循环，直到所选择的扇区被确认为擦除。在验证扇区之后，将擦除/验证周期应用于子集中的一个或多个剩余扇区，直到其余扇区中的每一个已被验证为已擦除。在子集中的所有扇区被擦除之后，擦除电压被复位到其初始值（840），并且如上所述（815）选择另一扇区子集进行擦除/验证。可以重复该过程，直到设备中的所有存储器扇区被擦除（850）。具有嵌入式逻辑的闪速存储器件可用于执行该方法。

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