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11. 发明授权

US07527742B2 Etchant, method of etching, laminate formed thereby, and device 有权
标题翻译：蚀刻剂，蚀刻方法，由此形成的层压体和装置
公开(公告)号：US07527742B2
公开(公告)日：2009-05-05
申请号：US11167719
申请日：2005-06-27
申请人： Steven Alfred Tysoe , Steven Francis LeBoeuf , Mark Philip D'Evelyn , Venkat Subramaniam Venkataramani , Vinayak Tilak , Jeffrey Bernard Fortin , Charles Adrian Becker , Stephen Daley Arthur , Samhita Dasgupta , Kanakasabapathi Subramanian , Robert John Wojnarowski , Abasifreke Udo Ebong
发明人： Steven Alfred Tysoe , Steven Francis LeBoeuf , Mark Philip D'Evelyn , Venkat Subramaniam Venkataramani , Vinayak Tilak , Jeffrey Bernard Fortin , Charles Adrian Becker , Stephen Daley Arthur , Samhita Dasgupta , Kanakasabapathi Subramanian , Robert John Wojnarowski , Abasifreke Udo Ebong
IPC分类号： C03C15/00 , C03C25/68
CPC分类号： H01L21/31111
摘要： An etchant including a halogenated salt, such as Cryolite (Na3AlF6) or potassium tetrafluoro borate (KBF4), is provided. The salt may be present in the etchant in an amount sufficient to etch a substrate and may have a melt temperature of greater than about 200 degrees Celsius. A method of wet etching may include contacting an etchant to at least one surface of a support layer of a multi-layer laminate, wherein the support layer may include aluminum oxide; or contacting an etchant to at least one surface of a support layer of a multi-layer laminate, wherein the etchant may include Cryolite (Na3AlF6), potassium tetrafluoro borate (KBF4), or both; and etching at least a portion of the support layer. The method may provide a laminate produced by growing a crystal onto an aluminum oxide support layer, and chemically removing at least a portion of the support layer by wet etch. An electronic device, optical device or combined device including the laminate is provided.
摘要翻译：提供包括卤化盐的蚀刻剂，例如冰晶石（Na 3 AlF 6）或四氟硼酸钾（KBF 4）。盐可以以足以蚀刻基材的量存在于蚀刻剂中，并且可以具有大于约200摄氏度的熔体温度。湿蚀刻的方法可以包括使蚀刻剂与多层层压体的支撑层的至少一个表面接触，其中所述支撑层可以包括氧化铝; 或使蚀刻剂与多层层压体的支撑层的至少一个表面接触，其中所述蚀刻剂可以包括冰晶石（Na 3 AlF 6），四氟硼酸钾（KBF 4）或两者; 并蚀刻所述支撑层的至少一部分。该方法可以提供通过将结晶生长到氧化铝载体层上并通过湿蚀刻化学去除至少一部分载体层而制备的层压体。提供了包括层压板的电子设备，光学设备或组合设备。

12. 发明授权

US06655011B1 Method for fabricating a switch structure 有权
标题翻译：开关结构的制造方法
公开(公告)号：US06655011B1
公开(公告)日：2003-12-02
申请号：US09677718
申请日：2000-10-02
申请人： William Paul Kornrumpf , Robert John Wojnarowski
发明人： William Paul Kornrumpf , Robert John Wojnarowski
IPC分类号： H01H1100
CPC分类号： H01H1/0036 , H01H61/0107 , H01H2001/0042 , H01H2001/0073 , H01H2001/0084 , H01H2061/006 , Y10T29/49105 , Y10T29/49128 , Y10T29/49155
摘要： A switch structure having a base surface; a first high density interconnect (HDI) plastic interconnect layer overlying the base surface layer; a cavity within the HDI plastic interconnect layer; at least one patterned shape memory alloy (SMA) layer overlying the HDI plastic interconnect layer and the cavity, and at least one patterned conductive layer over the at least one patterned SMA layer; a fixed contact pad within the cavity and attached to the base surface and a movable contact pad attached to a portion of the first patterned SMA layer within the cavity such that when the first and second patterned SMA layers and the first and second patterned metallized layers are in a first stable position, the movable contact pad touches the fixed contact pad, thereby providing an electrical connection and forming a closed switch. The structure has a second stable position in which the SMA and metallized layers are flexed away from the cavity so that the contact pads are not in contact and form an open switch.
摘要翻译：具有基面的开关结构; 覆盖基底表面层的第一高密度互连（HDI）塑料互连层; HDI塑料互连层内的空腔; 覆盖HDI塑料互连层和空腔的至少一个图案形状记忆合金（SMA）层，以及至少一个图案化的SMA层上的至少一个图案化导电层; 空腔内的固定接触焊盘并附接到基体表面，以及可移动接触垫，其附接到空腔内的第一图案化SMA层的一部分，使得当第一和第二图案化SMA层和第一和第二图案化金属化层为在第一稳定位置，可动接触垫接触固定接触垫，由此提供电连接并形成闭合的开关。该结构具有第二稳定位置，其中SMA和金属化层从空腔弯曲，使得接触焊盘不接触并形成开放的开关。

13. 发明授权

US06092280A Flexible interface structures for electronic devices 有权
标题翻译：灵活的电子设备接口结构
公开(公告)号：US06092280A
公开(公告)日：2000-07-25
申请号：US318952
申请日：1999-05-26
申请人： Robert John Wojnarowski
发明人： Robert John Wojnarowski
IPC分类号： H01L23/12 , H01L21/48 , H01L23/32 , H01L23/485 , H01L23/498 , H05K3/32 , H05K3/34 , H05K3/40 , H01R43/00 , H01L23/40
CPC分类号： H01L24/02 , H01L21/4853 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H05K3/3436 , H01L2224/0401 , H01L2224/16225 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01021 , H01L2924/01022 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/12042 , H01L2924/19041 , H01L2924/19043 , H01L2924/30107 , H01L2924/3511 , H05K2201/0373 , H05K2201/10257 , H05K2201/10378 , H05K3/326 , H05K3/4092 , Y02P70/613 , Y10S428/901 , Y10T29/49124 , Y10T29/4913 , Y10T428/24917
摘要： A flexible film interface includes a flexible film; flexible material attached to a portion of the flexible film; surface metallization on the flexible material, the flexible film having at least one via extending therethrough to the surface metallization; and a floating pad structure including floating pad metallization patterned over the flexible material and the surface metallization, a first portion of the floating pad metallization forming a central pad and a second portion of the floating pad metallization forming at least one extension from the central pad and extending into the at least one via.
摘要翻译：柔性膜界面包括柔性膜; 柔性材料附着在柔性膜的一部分上; 在柔性材料上的表面金属化，所述柔性膜具有至少一个通过其延伸到表面金属化的通孔; 以及浮动焊盘结构，其包括在所述柔性材料和所述表面金属化之上图案化的浮动焊盘金属化，所述浮动焊盘金属化的第一部分形成中心焊盘，并且所述浮动焊盘金属化的第二部分形成从所述中心焊盘的至少一个延伸部，延伸到所述至少一个通孔中。

14. 发明授权

US6046410A Interface structures for electronic devices 有权
标题翻译：电子设备接口结构
公开(公告)号：US6046410A
公开(公告)日：2000-04-04
申请号：US139049
申请日：1998-08-24
申请人： Robert John Wojnarowski , Barry Scott Whitmore , Bernard Gorowitz
发明人： Robert John Wojnarowski , Barry Scott Whitmore , Bernard Gorowitz
IPC分类号： H01L21/48 , H01L23/485 , H01L23/498 , H05K3/32 , H05K3/34 , H05K3/40 , H01R9/09
CPC分类号： H01L24/02 , H01L21/4853 , H01L23/49811 , H01L23/49816 , H01L23/49827 , H05K3/3436 , H01L2224/0401 , H01L2224/16 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/014 , H01L2924/12042 , H01L2924/19041 , H01L2924/19043 , H01L2924/30107 , H01L2924/3511 , H05K2201/0373 , H05K2201/10257 , H05K2201/10378 , H05K3/326 , H05K3/4092 , Y02P70/613 , Y10S438/94 , Y10T29/49124 , Y10T29/49126 , Y10T29/4913
摘要： An interface includes a surface having an electrically conductive pad; a compliant coating over the surface having a via extending to the pad; metallization patterned over the compliant coating and extending into the via; a low modulus dielectric interface layer overlying the compliant coating and having an interface via extending to the metallization; and a floating pad structure including floating pad metallization patterned over the dielectric interface layer with a first portion forming a central pad and a second portion forming an extension from the central pad extending into the interface via. Another interface includes a substrate including a low modulus dielectric interface material having a hole extending at least partially therethrough and a floating contact structure including electrically conductive material coating the hole with at least some of the floating pad metallization forming an extension from the hole. A conductive contact area interface may include an electrically conductive first contact area; an electrically conductive second contact area facing and being substantially aligned with the first contact area; and at least one interface structure coupled between the first and second contact areas and including an electrical conductor having a partially open interior to form a compliant joint between the first and second contact areas.
摘要翻译：界面包括具有导电垫的表面; 表面上的柔顺涂层具有延伸到垫的通孔; 金属化图案化在柔性涂层上并延伸到通孔中; 覆盖顺应性涂层并具有延伸到金属化的界面的低模量介电界面层; 以及浮动衬垫结构，其包括在电介质界面层上图案化的浮动衬垫金属化，第一部分形成中心焊盘，第二部分形成从延伸到接口通孔的中心焊盘的延伸部分。另一个界面包括一个衬底，该衬底包括一个具有至少部分贯穿其中延伸的孔的低模量介电界面材料，以及一个浮动接触结构，其包括导电材料，该导电材料涂覆孔，浮动金属化中的至少一些从孔形成延伸。导电接触区界面可以包括导电的第一接触区域; 面向并基本上与第一接触区域对准的导电的第二接触区域; 以及耦合在所述第一和第二接触区域之间的至少一个接口结构，并且包括具有部分敞开的内部的电导体，以在所述第一和第二接触区域之间形成柔性接头。

15. 发明授权

US5949133A Semiconductor interconnect structure for high temperature applications 失效
标题翻译：用于高温应用的半导体互连结构
公开(公告)号：US5949133A
公开(公告)日：1999-09-07
申请号：US815546
申请日：1997-03-12
申请人： Robert John Wojnarowski
发明人： Robert John Wojnarowski
IPC分类号： H01L21/98 , H01L23/538 , H01L23/495 , H01L23/04 , H01L23/14 , H01L23/34
CPC分类号： H01L25/50 , H01L23/5381 , H01L23/5385 , H01L23/5389 , H01L24/24 , H01L24/82 , H01L2224/24137 , H01L2224/24225 , H01L2224/24227 , H01L2224/32225 , H01L2224/32245 , H01L2224/48472 , H01L2224/73267 , H01L2224/92244 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01042 , H01L2924/01074 , H01L2924/014 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/15153 , H01L2924/15165
摘要： A circuit module includes at least one high temperature semiconductor chip having chip pads; a substrate having substrate metallization, the chip pads and the substrate metallization being substantially planar; and a deposited flexible pattern of electrical conductors capable of withstanding high temperatures and coupling selected chip pads and portions of the substrate metallization. The deposited flexible pattern of electrical conductors includes a plurality of integral interconnect segments, at least one of the integral interconnect segments including first and second leg portions and a shelf portion with the shelf portion being spaced apart from the at least one semiconductor chip and substrate and being coupled by the first leg portion to a selected chip pad and by the second leg portion to one of another selected chip pad or a selected portion of the substrate metallization.
摘要翻译：电路模块包括至少一个具有芯片焊盘的高温半导体芯片; 具有衬底金属化的衬底，所述芯片焊盘和所述衬底金属化基本上是平面的; 以及沉积的能够耐受高温并且耦合所选芯片焊盘和衬底金属化部分的电导体的柔性图案。电导体的沉积的柔性图案包括多个整体的互连区段，整体互连区段中的至少一个包括第一和第二腿部部分以及搁架部分，搁架部分与至少一个半导体芯片和衬底间隔开，并且通过第一腿部部分耦合到选定的芯片焊盘，并且通过第二腿部部分耦合到另一个选定的芯片焊盘之一或衬底金属化的选定部分。

16. 发明授权

US5897728A Integrated circuit test structure and test process 失效
标题翻译：集成电路测试结构和测试过程
公开(公告)号：US5897728A
公开(公告)日：1999-04-27
申请号：US759691
申请日：1991-09-06
申请人： Herbert Stanley Cole , James Wilson Rose , Robert John Wojnarowski , Charles William Eichelberger
发明人： Herbert Stanley Cole , James Wilson Rose , Robert John Wojnarowski , Charles William Eichelberger
IPC分类号： G01R31/30 , G01R1/04 , G01R31/00 , G01R31/28 , H01L21/60 , H01L21/66 , H01L23/538 , H01L23/58 , B32B32/00
CPC分类号： G01R1/04 , G01R31/2863 , H01L22/32 , H01L23/5389 , H01L24/05 , H01L24/24 , H01L24/48 , H01L24/82 , H01L24/85 , H01L2224/04042 , H01L2224/05599 , H01L2224/05624 , H01L2224/24227 , H01L2224/32225 , H01L2224/451 , H01L2224/48091 , H01L2224/48137 , H01L2224/4823 , H01L2224/48465 , H01L2224/48471 , H01L2224/73265 , H01L2224/73267 , H01L2224/82039 , H01L2224/85205 , H01L24/45 , H01L2924/00014 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15312 , H01L2924/15787 , H01L2924/30105
摘要： For fully testing and burning-in an integrated circuit chip before it is incorporated into a high density interconnect or other standard hybrid bare chip circuit, a temporary test substrate having pins extending therethrough holds the chip within a cavity. Chip pads are electrically connected with the pins to create a package that can be tested using commercially available testing and burn-in devices. After testing, the chip is retrieved from the test structure undamaged. In using HDI techniques to interconnect the chip with the pins, metal-filled vias in a polymer layer overlying the temporary test substrate electrically connect the chip to the pins through a metal interconnect pattern on the polymer layer. In another embodiment, the chip is interconnected with the pins through wire bonds. Metal-filled vias pass through an insulative coating on the chip and make electrical contact with the chip pad. A temporary buffer pad connected to a respective via and offset from the chip pad connected to that via comprises a wire-bonding site.
摘要翻译：为了在将集成电路芯片并入高密度互连或其他标准混合裸芯片电路之前对其进行完全测试和烧录，具有延伸穿过的引脚的临时测试基板将芯片保持在空腔内。芯片焊盘与引脚电连接以产生可以使用市售测试和老化设备进行测试的封装。测试后，芯片从测试结构中检索到无损坏。在使用HDI技术将芯片与引脚互连时，覆盖临时测试基板的聚合物层中的金属填充的通孔通过聚合物层上的金属互连图案将芯片电连接到引脚。在另一个实施例中，芯片通过引线键与引脚互连。金属填充的通孔穿过芯片上的绝缘涂层，并与芯片焊盘电接触。连接到相应通孔并与连接到该通孔的芯片焊盘偏移的临时缓冲垫包括引线接合部位。

17. 发明授权

US5888884A Electronic device pad relocation, precision placement, and packaging in arrays 失效
公开(公告)号：US5888884A
公开(公告)日：1999-03-30
申请号：US2314
申请日：1998-01-02
申请人： Robert John Wojnarowski
发明人： Robert John Wojnarowski
IPC分类号： F21K99/00 , H01L21/304 , H01L21/768 , H01L21/78 , H01L23/485 , H01L25/065 , H01L21/301
CPC分类号： H01L24/13 , H01L21/3043 , H01L21/76898 , H01L21/78 , H01L24/10 , H01L25/0652 , H01L2224/02371 , H01L2224/05548 , H01L2224/13 , H01L2224/13099 , H01L2224/16 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10329 , H01L2924/12042 , H01L2924/181 , H01L2924/19042 , H01L2924/3511
摘要： Top die pads are electrically relocated by forming holes through a semiconductor wafer between device active regions. An electrically insulating layer is formed over all exposed surfaces of the wafer, including within the holes, and openings are made in the insulating layer for access to the top interconnection pads. The wafer and holes are metallized and patterned to form bottom interconnection pads electrically connected to corresponding top interconnection pads by metallization extending within the holes. A dicing saw having a kerf width less than the diameter of the holes is employed to separate the individual devices. For accurate position alignment of repatterned die, an alignment structure, such as projecting pins or an egg crate structure, engages the die, and alignment pads can be patterned on the die.

18. 发明授权

US5872040A Method for fabricating a thin film capacitor 失效
标题翻译：薄膜电容器的制造方法
公开(公告)号：US5872040A
公开(公告)日：1999-02-16
申请号：US862994
申请日：1997-05-27
申请人： Robert John Wojnarowski , James Wilson Rose , Ernest Wayne Balch , Leonard Richard Douglas , Evan Taylor Downey , Michael Gdula
发明人： Robert John Wojnarowski , James Wilson Rose , Ernest Wayne Balch , Leonard Richard Douglas , Evan Taylor Downey , Michael Gdula
IPC分类号： H01C17/12 , H01C17/24 , H01G4/06 , H01G4/08 , H05K1/16 , H01L21/20
CPC分类号： H01C17/24 , H01C17/12 , H01C17/2416 , H01G4/06 , H01G4/08 , H05K1/167 , Y10S148/136
摘要： A method is provided for the manufacture of precision electronic components such as resistors, inductors, and capacitors on a polymer or ceramic surface. The electronic components can be deposited and trimmed to precise or matched values without having precise depositions of all of the pre-patterned materials. Thin film electronic components are deposited on a surface, parameter values are measured or estimated, a correction offset file is generated, and the components are trimmed using adaptive lithography to a very close tolerance. A computer program can be used to enable the adjustment of electronic components by techniques such as changing the physical length of an inductor coil or resistor lead, or by changing a capacitor plate area.
摘要翻译：提供了一种用于在聚合物或陶瓷表面上制造诸如电阻器，电感器和电容器的精密电子部件的方法。电子部件可以沉积和修整成精确或匹配的值，而不会精确沉积所有预图案化材料。薄膜电子部件沉积在表面上，测量或估计参数值，产生校正偏移文件，并且使用适应光刻将组件修剪到非常接近的公差。可以使用计算机程序来实现电子部件的调整，例如改变电感线圈或电阻器引线的物理长度，或者改变电容器板面积。

19. 发明授权

US5683928A Method for fabricating a thin film resistor 失效
标题翻译：制造薄膜电阻的方法
公开(公告)号：US5683928A
公开(公告)日：1997-11-04
申请号：US349278
申请日：1994-12-05
申请人： Robert John Wojnarowski , James Wilson Rose , Ernest Wayne Balch , Leonard Richard Douglas , Evan Taylor Downey , Michael Gdula
发明人： Robert John Wojnarowski , James Wilson Rose , Ernest Wayne Balch , Leonard Richard Douglas , Evan Taylor Downey , Michael Gdula
IPC分类号： H01C17/12 , H01C17/24 , H01G4/06 , H01G4/08 , H05K1/16 , H01L21/70
CPC分类号： H01C17/24 , H01C17/12 , H01C17/2416 , H01G4/06 , H01G4/08 , H05K1/167 , Y10S148/136
摘要： A method is provided for the manufacture of precision electronic components such as resistors, inductors, and capacitors on a polymer or ceramic surface. The electronic components can be deposited and trimmed to precise or matched values without having precise depositions of all of the pre-patterned materials. Thin film electronic components are deposited on a surface, parameter values are measured or estimated, a correction offset file is generated, and the components are trimmed using adaptive lithography to a very close tolerance. A computer program can be used to enable the adjustment of electronic components by techniques such as changing the physical length of an inductor coil or resistor lead, or by changing a capacitor plate area.
摘要翻译：提供了一种用于在聚合物或陶瓷表面上制造诸如电阻器，电感器和电容器的精密电子部件的方法。电子部件可以沉积和修整成精确或匹配的值，而不会精确沉积所有预图案化材料。薄膜电子部件沉积在表面上，测量或估计参数值，产生校正偏移文件，并且使用适应光刻将组件修剪到非常接近的公差。可以使用计算机程序来实现电子部件的调整，例如改变电感线圈或电阻器引线的物理长度，或者改变电容器板面积。

20. 发明申请

US20080143216A1 Piezoelectric composite apparatus and related methods 有权
标题翻译：压电复合设备及相关方法
公开(公告)号：US20080143216A1
公开(公告)日：2008-06-19
申请号：US11640803
申请日：2006-12-18
申请人： Ertugrul Berkcan , Emad Andarawis Andarawis , Robert John Wojnarowski , Charles Scott Sealing , Charles Erklin Seeley , Eladio Clemente Delgado , David Cecil Hays , Christopher James Kapusta , Nanette Judith Gruber
发明人： Ertugrul Berkcan , Emad Andarawis Andarawis , Robert John Wojnarowski , Charles Scott Sealing , Charles Erklin Seeley , Eladio Clemente Delgado , David Cecil Hays , Christopher James Kapusta , Nanette Judith Gruber
IPC分类号： H01L41/083 , H01L41/047 , H01L41/16
CPC分类号： H01L27/20 , G01M5/00 , G01N29/245 , G01N29/2475 , G01N2291/0231 , H01L41/047 , H01L41/1132
摘要： A piezoelectric planar composite apparatus to provide health monitoring of a structure and associated methods are provided. The piezoelectric planar composite apparatus includes a piezoelectric electric material layer, multiple electrodes positioned in electrical contact with the piezoelectric material layer, and multiple sets of electrode interconnect conductors each positioned in electrical contact with a different subset of the of the electrodes and positioned to form multiple complementary electrode patterns. Each of the complementary electrode patterns is positioned to form an electric field having an electric field axis oriented along a different physical axis from that of an electric field formed by at least one other of the complementary electrode patterns. The interconnect conductors can be distributed over several electrode interconnect conductor carrying layers to enhance formation of the different complementary electrode patterns.
摘要翻译：提供了一种用于提供结构和相关方法的健康监测的压电平面复合装置。压电平面复合装置包括压电电材料层，与压电材料层电接触的多个电极，以及多组电极互连导体，每组电极互连导体定位成与电极的不同子集电接触并且定位成形成多个互补电极图案。每个互补电极图案被定位成形成电场轴，该电场轴沿着与至少另一个互补电极图案形成的电场不同的物理轴定向。互连导体可以分布在多个电极互连导体承载层上以增强不同互补电极图案的形成。

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