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11. 发明申请

US20080153227A1 NAND FLASH MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译： NAND闪存存储器件及其制造方法
公开(公告)号：US20080153227A1
公开(公告)日：2008-06-26
申请号：US12041949
申请日：2008-03-04
申请人： Jae Chul Om , Nam Kyeong Kim , Se Jun Kim
发明人： Jae Chul Om , Nam Kyeong Kim , Se Jun Kim
IPC分类号： H01L21/336
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/66825
摘要： A NAND flash memory device and method of manufacturing the same is disclosed. Source and drain select transistor gates are recessed lower than an active region of a semiconductor substrate. A valid channel length of the source and drain select transistor gates is longer than a channel length of memory cell gates. Accordingly, an electric field between a source region and a drain region of the select transistor can be reduced. It is thus possible to prevent program disturbance from occurring in edge memory cells adjacent to the source and drain select transistors in non-selected cell strings.
摘要翻译：公开了NAND闪速存储器件及其制造方法。源极和漏极选择晶体管栅极比半导体衬底的有源区域低。源极和漏极选择晶体管栅极的有效沟道长度比存储器单元栅极的沟道长度长。因此，可以减小选择晶体管的源极区域和漏极区域之间的电场。因此，可以防止在非选择的单元串中与源极和漏极选择晶体管相邻的边缘存储单元中发生程序干扰。

12. 发明授权

US06813196B2 High speed interface type semiconductor memory device 失效
标题翻译：高速接口型半导体存储器件
公开(公告)号：US06813196B2
公开(公告)日：2004-11-02
申请号：US09892549
申请日：2001-06-28
申请人： Yong Jae Park , Se Jun Kim
发明人： Yong Jae Park , Se Jun Kim
IPC分类号： G11C700
CPC分类号： G11C7/222 , G11C7/1072 , G11C7/22 , G11C11/4076
摘要： The present invention discloses a high speed interface type semiconductor memory device which can transmit data of a plurality of DRAMs of a module to a controller by using only one data strobe clock signal. The high speed interface type semiconductor memory device includes a DRAM module unit for generating a strobe clock signal for synchronizing a data signal in a read operation in a DRAM farthest from a controller among a plurality of DRAMs, providing the strobe clock signal to the other DRAMs, and transmitting data to the controller in the read operation, and a controller for transmitting a clock signal and data signals synchronized with the clock signal to the plurality of DRAMs, and receiving data signals from the DRAMs.
摘要翻译：本发明公开了一种高速接口型半导体存储器件，其可以通过仅使用一个数据选通时钟信号将模块的多个DRAM的数据传输到控制器。高速接口型半导体存储器件包括：DRAM模块单元，用于产生用于在多个DRAM中与控制器最远的DRAM中的读取操作中的数据信号同步的选通时钟信号，将选通时钟信号提供给其它DRAM ，以及在读取操作中向控制器发送数据，以及用于将时钟信号和与时钟信号同步的数据信号发送到多个DRAM的控制器，以及从DRAM接收数据信号。

13. 发明授权

US06686788B2 Delay circuit of clock synchronization device using delay cells having wide delay range 失效
标题翻译：使用具有宽延迟范围的延迟单元的时钟同步装置的延迟电路
公开(公告)号：US06686788B2
公开(公告)日：2004-02-03
申请号：US10140280
申请日：2002-05-06
申请人： Se Jun Kim , Sang Hoon Hong
发明人： Se Jun Kim , Sang Hoon Hong
IPC分类号： H03H1126
CPC分类号： H03K5/133 , H03K2005/00026 , H03K2005/00208 , H03K2005/00234 , H03L7/0812 , H03L7/0995
摘要： A delay circuit of a clock synchronization device that includes an operational amplifier for setting the level of a current control voltage according to a voltage difference between a regulation voltage and a reference voltage. A number of unit delay cells connected in series are included, each having a delay time set according to a resistance control voltage and the current control voltage. Also, a variable resistance unit is included having a resistance value adjusted according to the resistance control voltage, where the variable resistance unit includes a cross coupled adjustment device that outputs signals to a next unit delay cell. The delay cells are controlled by using the operational amplifier and a replica cell to have a wide delay range. As a result, the working range can be set wide, jitters may be reduced and the chip size may also be reduced.
摘要翻译：时钟同步装置的延迟电路，其包括用于根据调节电压和参考电压之间的电压差来设定电流控制电压的电平的运算放大器。包括串联连接的多个单元延迟单元，每个具有根据电阻控制电压和电流控制电压设置的延迟时间。此外，包括根据电阻控制电压调整的电阻值的可变电阻单元，其中可变电阻单元包括向下一个单位延迟单元输出信号的交叉耦合调整装置。通过使用运算放大器和复制单元来控制延迟单元具有宽的延迟范围。结果，可以将工作范围设定得很宽，可能减少抖动，并且芯片尺寸也可能降低。

14. 发明授权

US06597298B2 Clock synchronization device 失效
公开(公告)号：US06597298B2
公开(公告)日：2003-07-22
申请号：US10180131
申请日：2002-06-27
申请人： Se Jun Kim , Sang Hoon Hong
发明人： Se Jun Kim , Sang Hoon Hong
IPC分类号： H03M148
CPC分类号： H03L7/089 , H03L7/0812 , H04L7/0037
摘要： A clock synchronization device divides a digital-to-analog converting unit into main and sub digital-to-analog converters and operates both main and sub digital-to-analog converting units if an output voltage of the digital-to-analog converting unit is lower than a reference voltage based on a voltage obtained when the delay rate of a variable delay line VDL is sharply increased or operates only the main digital-to-analog converting unit if the output voltage of the digital-to-analog converting unit is higher than the reference voltage. As a result, the clock synchronization device can make the output voltage of the digital-to-analog converting unit be linear with respect to a digital code, thereby improving a jitter property in a band with a very large gain of the variable delay line.

15. 发明授权

US07955960B2 Nonvolatile memory device and method of fabricating the same 失效
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US07955960B2
公开(公告)日：2011-06-07
申请号：US12052914
申请日：2008-03-21
申请人： Se Jun Kim , Eun Seok Choi , Kyoung Hwan Park , Hyun Seung Yoo , Myung Shik Lee , Young Ok Hong , Jung Ryul Ahn , Yong Top Kim , Kyung Pil Hwang , Won Sic Woo , Jae Young Park , Ki Hong Lee , Ki Seon Park , Moon Sig Joo
发明人： Se Jun Kim , Eun Seok Choi , Kyoung Hwan Park , Hyun Seung Yoo , Myung Shik Lee , Young Ok Hong , Jung Ryul Ahn , Yong Top Kim , Kyung Pil Hwang , Won Sic Woo , Jae Young Park , Ki Hong Lee , Ki Seon Park , Moon Sig Joo
IPC分类号： H01L21/336
CPC分类号： H01L29/513 , H01L27/105 , H01L27/11568 , H01L27/11573 , H01L29/792
摘要： A nonvolatile memory device and a method of fabricating the same is provided to prevent charges stored in a charge trap layer from moving to neighboring memory cells. The method of fabricating a nonvolatile memory device, includes forming a first dielectric layer on a semiconductor substrate in which active regions are defined by isolation layers, forming a charge trap layer on the first dielectric layer, removing the first dielectric layer and the charge trap layer over the isolation layers, forming a second dielectric layer on the isolation layers including the charge trap layer, and forming a conductive layer on the second dielectric layer.
摘要翻译：提供了一种非易失性存储器件及其制造方法，以防止存储在电荷陷阱层中的电荷移动到相邻存储器单元。制造非易失性存储器件的方法包括在半导体衬底上形成第一电介质层，其中有源区由隔离层限定，在第一电介质层上形成电荷陷阱层，去除第一介电层和电荷陷阱层在隔离层上，在包括电荷陷阱层的隔离层上形成第二电介质层，并在第二介电层上形成导电层。

16. 发明申请

US20080042737A1 Band-gap reference voltage generator 失效
标题翻译：带隙基准电压发生器
公开(公告)号：US20080042737A1
公开(公告)日：2008-02-21
申请号：US11648462
申请日：2006-12-28
申请人： Se Jun Kim , Chun Seok Jeong
发明人： Se Jun Kim , Chun Seok Jeong
IPC分类号： G05F1/10
CPC分类号： G05F3/30
摘要： A band-gap reference voltage generator includes a first reference current generator, a second reference current generator, and a reference voltage generator. The first reference current generator includes: a driver generating a first reference current in response to a first voltage signal generated by comparison of the unique voltage and the thermal voltage. The second reference current generator includes a driver generating a second reference current in response to a second voltage signal generated by comparison of a division voltage of a power-supply voltage and the unique voltage. The reference voltage generator includes a driver forming current mirrors in association with each of the first reference current generator and the second reference current generator, respectively, and generating a third reference current and a fourth reference current via the formed current mirrors, and a current-voltage converter converting the sum of the third reference current and the fourth reference current into a reference voltage, and outputting the reference voltage.
摘要翻译：带隙参考电压发生器包括第一参考电流发生器，第二参考电流发生器和参考电压发生器。第一参考电流发生器包括：响应于通过比较唯一电压和热电压而产生的第一电压信号而产生第一参考电流的驱动器。第二参考电流发生器包括响应于通过比较电源电压的分压和独特电压而产生的第二电压信号而产生第二参考电流的驱动器。参考电压发生器包括分别与第一参考电流发生器和第二参考电流发生器相关联地形成电流镜的驱动器，并且经由形成的电流镜产生第三参考电流和第四参考电流，电压转换器将第三参考电流和第四参考电流的和转换成参考电压，并输出参考电压。

17. 发明授权

US06677794B2 Clock synchronization device 失效
标题翻译：时钟同步装置
公开(公告)号：US06677794B2
公开(公告)日：2004-01-13
申请号：US10330863
申请日：2002-12-27
申请人： Se Jun Kim
发明人： Se Jun Kim
IPC分类号： H03L700
CPC分类号： H03L7/07 , H03L7/0814 , H03L7/0818
摘要： A clock synchronization device includes: a coarse delay line arranged to sequentially delay an external clock signal and output one or more pairs of first multi-phase clock signals and one or more pairs of second multi-phase clock signals; a clock interface arranged to select a pair of clock signals having opposite phases from among the one or more pairs of first multi-phase clock signals and the one or more pairs of second multi-phase clock signals and further arranged to synthesize the phase of a pair of the selected clock signals; and a fine delay line arranged to finely delay the pair the selected clock signals from the clock interface and output an internal clock signal synchronized with the external clock signal.
摘要翻译：时钟同步装置包括：粗延迟线，被布置成顺序地延迟外部时钟信号并输出一对或多对第一多相时钟信号和一对或多对第二多相时钟信号; 时钟接口，布置成选择一对时钟信号，所述一对时钟信号具有来自所述一对或多对第一多相时钟信号和所述一对或多对第二多相时钟信号中的相位相位，并且还被布置为合成一个所选择的时钟信号对; 以及精细延迟线，其被布置成从时钟接口精细地延迟所选择的时钟信号，并输出与外部时钟信号同步的内部时钟信号。

18. 发明授权

US08446778B2 Method for operating a flash memory device 有权
标题翻译：操作闪存设备的方法
公开(公告)号：US08446778B2
公开(公告)日：2013-05-21
申请号：US12650787
申请日：2009-12-31
申请人： Se Jun Kim
发明人： Se Jun Kim
IPC分类号： G11C11/34
CPC分类号： G11C16/3459 , G11C16/3454
摘要： A charge trap flash memory device is capable of preventing a data retention fail by ensuring a data retention margin. A method for operating the charge trap flash memory device is provided. A selected memory cell is programmed using a program voltage. The selected memory cell is verified using a first program verify voltage. Date retention states of selected memory cell having passed the program verify step are verified using a retention verify voltage. A read step of determining a program pass or fail by reading data of the selected memory cell having passed the retention verify step is performed using a read voltage.
摘要翻译：充电陷阱闪存设备能够通过确保数据保留余量来防止数据保留失败。提供了一种用于操作电荷陷阱闪存器件的方法。使用编程电压对选定的存储单元进行编程。使用第一程序验证电压验证所选存储单元。使用保留验证电压验证已经通过程序验证步骤的选定存储单元的保持状态。使用读取电压来执行通过读取已经通过保留验证步骤的所选存储单元的数据来确定程序通过或失败的读取步骤。

19. 发明申请

US20110171797A1 NAND FLASH MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译： NAND闪存存储器件及其制造方法
公开(公告)号：US20110171797A1
公开(公告)日：2011-07-14
申请号：US13069273
申请日：2011-03-22
申请人： Jae Chul OM , Nam Kyeong Kim , Se Jun Kim
发明人： Jae Chul OM , Nam Kyeong Kim , Se Jun Kim
IPC分类号： H01L21/336
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/66825
摘要： A NAND flash memory device and method of manufacturing the same is disclosed. Source and drain select transistor gates are recessed lower than an active region of a semiconductor substrate. A valid channel length of the source and drain select transistor gates is longer than a channel length of memory cell gates. Accordingly, an electric field between a source region and a drain region of the select transistor can be reduced. It is thus possible to prevent program disturbance from occurring in edge memory cells adjacent to the source and drain select transistors in non-selected cell strings.
摘要翻译：公开了NAND闪速存储器件及其制造方法。源极和漏极选择晶体管栅极比半导体衬底的有源区域低。源极和漏极选择晶体管栅极的有效沟道长度比存储器单元栅极的沟道长度长。因此，可以减小选择晶体管的源极区域和漏极区域之间的电场。因此，可以防止在非选择的单元串中与源极和漏极选择晶体管相邻的边缘存储单元中发生程序干扰。

20. 发明授权

US07910430B2 NAND flash memory device and method of manufacturing the same 有权
标题翻译： NAND闪存器件及其制造方法
公开(公告)号：US07910430B2
公开(公告)日：2011-03-22
申请号：US12041949
申请日：2008-03-04
申请人： Jae Chul Om , Nam Kyeong Kim , Se Jun Kim
发明人： Jae Chul Om , Nam Kyeong Kim , Se Jun Kim
IPC分类号： H01L21/336
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/66825
摘要： A NAND flash memory device and method of manufacturing the same is disclosed. Source and drain select transistor gates are recessed lower than an active region of a semiconductor substrate. A valid channel length of the source and drain select transistor gates is longer than a channel length of memory cell gates. Accordingly, an electric field between a source region and a drain region of the select transistor can be reduced. It is thus possible to prevent program disturbance from occurring in edge memory cells adjacent to the source and drain select transistors in non-selected cell strings.
摘要翻译：公开了NAND闪速存储器件及其制造方法。源极和漏极选择晶体管栅极比半导体衬底的有源区域低。源极和漏极选择晶体管栅极的有效沟道长度比存储器单元栅极的沟道长度长。因此，可以减小选择晶体管的源极区域和漏极区域之间的电场。因此，可以防止在非选择的单元串中与源极和漏极选择晶体管相邻的边缘存储单元中发生程序干扰。

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