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1. 发明授权

US08268685B2 NAND flash memory device and method of manufacturing the same 有权
标题翻译： NAND闪存器件及其制造方法
公开(公告)号：US08268685B2
公开(公告)日：2012-09-18
申请号：US13069273
申请日：2011-03-22
申请人： Jae Chul Om , Nam Kyeong Kim , Se Jun Kim
发明人： Jae Chul Om , Nam Kyeong Kim , Se Jun Kim
IPC分类号： H01L21/336
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/66825
摘要： A NAND flash memory device and method of manufacturing the same is disclosed. Source and drain select transistor gates are recessed lower than an active region of a semiconductor substrate. A valid channel length of the source and drain select transistor gates is longer than a channel length of memory cell gates. Accordingly, an electric field between a source region and a drain region of the select transistor can be reduced. It is thus possible to prevent program disturbance from occurring in edge memory cells adjacent to the source and drain select transistors in non-selected cell strings.
摘要翻译：公开了NAND闪速存储器件及其制造方法。源极和漏极选择晶体管栅极比半导体衬底的有源区域低。源极和漏极选择晶体管栅极的有效沟道长度比存储器单元栅极的沟道长度长。因此，可以减小选择晶体管的源极区域和漏极区域之间的电场。因此，可以防止在非选择的单元串中与源极和漏极选择晶体管相邻的边缘存储单元中发生程序干扰。

2. 发明授权

US07570107B2 Band-gap reference voltage generator 失效
标题翻译：带隙基准电压发生器
公开(公告)号：US07570107B2
公开(公告)日：2009-08-04
申请号：US11648462
申请日：2006-12-28
申请人： Se Jun Kim , Chun Seok Jeong
发明人： Se Jun Kim , Chun Seok Jeong
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G05F3/30
摘要： A band-gap reference voltage generator is provided that is capable of being used at low voltage simultaneously with adjusting a reference voltage.
摘要翻译：提供带隙参考电压发生器，其能够在调节参考电压的同时以低电压使用。

3. 发明申请

US20070207580A1 METHOD OF MANUFACTURING FLASH MEMORY DEVICE 失效
标题翻译：制造闪存存储器件的方法
公开(公告)号：US20070207580A1
公开(公告)日：2007-09-06
申请号：US11618702
申请日：2006-12-29
申请人： Sun Mi Park , Yoo Nam Jeon , Nam Kyeong Kim , Se Jun Kim
发明人： Sun Mi Park , Yoo Nam Jeon , Nam Kyeong Kim , Se Jun Kim
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L21/76849 , H01L21/76877 , H01L27/11521
摘要： A method of manufacturing a flash memory device includes etching an insulating layer provided over a substrate to form a contact hole to define a contact hole exposing a junction region formed on the substrate. The contact hole is filled with a first conductive material, the first conductive material contacting the junction region and extending above an upper surface of the contact hole. The first conductive material is etched to partly fill the contact hole, so that the first conductive material fills a lower portion of the contact hole, wherein an upper portion of the contact hole remains not filled due to the etching of the first conductive material, wherein the etched first conductive material defines a contact plug. A first dielectric layer and a second dielectric layer are formed over the contact plug, thereby filling the upper portion of the contact hole. Part of the first and second dielectric layers is etched to expose the contact plug and the upper portion of the contact hole. A second conductive material is formed on the contact plug and filling the upper portion of the contact hole to form a bit line.
摘要翻译：制造闪速存储器件的方法包括蚀刻设置在衬底上的绝缘层以形成接触孔，以限定暴露形成在衬底上的接合区域的接触孔。接触孔填充有第一导电材料，第一导电材料接触接合区并在接触孔的上表面上方延伸。第一导电材料被蚀刻以部分地填充接触孔，使得第一导电材料填充接触孔的下部，其中接触孔的上部部分由于蚀刻第一导电材料而保持未填充，其中蚀刻的第一导电材料限定接触插塞。第一电介质层和第二电介质层形成在接触插塞上，从而填充接触孔的上部。蚀刻第一和第二电介质层的一部分以暴露接触插塞和接触孔的上部。第二导电材料形成在接触插塞上并填充接触孔的上部以形成位线。

4. 发明授权

US06583654B2 Clock synchronization device 失效
标题翻译：时钟同步装置
公开(公告)号：US06583654B2
公开(公告)日：2003-06-24
申请号：US10139889
申请日：2002-05-06
申请人： Se Jun Kim , Jae Kyung Wee
发明人： Se Jun Kim , Jae Kyung Wee
IPC分类号： H03L700
CPC分类号： H03L7/0812 , H03L7/089
摘要： A clock synchronization device is disclosed that includes a phase detecting unit for detecting a phase difference between an external clock signal and an internal clock signal, a binary code generating unit for outputting a binary code value according to output signals from the phase detecting unit, a code converting unit for converting the binary code value from the binary code generating unit into a thermometer code value, a D/A converting unit for outputting a voltage corresponding to the thermometer code value from the code converting unit and a clock synchronization control unit for outputting the internal clock signal from the external clock signal according to the output voltage from the D/A converting unit. As the result, the clock synchronization device is controlled by employing the D/A converting unit for converting the binary code to the thermometer code in order to decrease the number of the registers, the leakage current and the chip size.
摘要翻译：公开了一种时钟同步装置，包括用于检测外部时钟信号和内部时钟信号之间的相位差的相位检测单元，用于根据来自相位检测单元的输出信号输出二进制码值的二进制码产生单元，代码转换单元，用于将来自二进制代码生成单元的二进制代码值转换为温度计代码值; D / A转换单元，用于从代码转换单元输出与温度计代码值相对应的电压;以及时钟同步控制单元，用于输出来自外部时钟信号的内部时钟信号根据来自D / A转换单元的输出电压。结果，通过采用用于将二进制码转换为温度计代码的D / A转换单元来控制时钟同步装置，以便减少寄存器的数量，漏电流和芯片尺寸。

5. 发明授权

US09349456B2 Method of operating non-volatile memory device 有权
标题翻译：操作非易失性存储器件的方法
公开(公告)号：US09349456B2
公开(公告)日：2016-05-24
申请号：US13483521
申请日：2012-05-30
申请人： Se Jun Kim , Hea Jong Yang
发明人： Se Jun Kim , Hea Jong Yang
IPC分类号： G11C16/06 , G11C16/34 , G11C16/16 , G11C16/04
CPC分类号： G11C16/06 , G11C16/0483 , G11C16/16 , G11C16/3409
摘要： A method of operating a non-volatile memory device includes erasing a memory cell block, supplying a first drain turn-on voltage higher than a target level to the drain select line of the memory cell block, and performing a soft program operation by supplying a soft program voltage to the word lines of the memory cell block.
摘要翻译：一种操作非易失性存储器件的方法包括擦除存储器单元块，将高于目标电平的第一漏极导通电压提供给存储器单元块的漏极选择线，并且通过提供一个软编程电压到存储单元块的字线。

6. 发明授权

US07616496B2 Charge trap type non-volatile memory device and program method thereof 失效
标题翻译：电荷陷阱型非易失性存储器件及其编程方法
公开(公告)号：US07616496B2
公开(公告)日：2009-11-10
申请号：US11771632
申请日：2007-06-29
申请人： Eun Seok Choi , Se Jun Kim , Kyoung Hwan Park , Hyun Seung Yoo
发明人： Eun Seok Choi , Se Jun Kim , Kyoung Hwan Park , Hyun Seung Yoo
IPC分类号： G11C16/04
CPC分类号： G11C16/3454 , G11C16/0466
摘要： A method of programming a charge trap type non-volatile memory device includes applying a program pulse to a selected memory cell, applying a detrap pulse to the selected memory cell, and applying a program verify pulse to the memory cell. The charge trap type non-volatile memory device includes a memory cell array including a charge trap memory cell, and a high voltage generator for supplying a detrap pulse to the charge trap memory cell.
摘要翻译：一种对电荷陷阱型非易失性存储器件进行编程的方法包括将程序脉冲施加到所选择的存储单元，向所选择的存储单元施加去除脉冲，以及将程序验证脉冲施加到存储单元。电荷陷阱型非易失性存储器件包括具有电荷陷阱存储单元的存储单元阵列，以及用于向电荷陷阱存储单元提供去除脉冲的高电压发生器。

7. 发明授权

US07456466B2 NAND flash memory device and method of manufacturing the same 有权
标题翻译： NAND闪存器件及其制造方法
公开(公告)号：US07456466B2
公开(公告)日：2008-11-25
申请号：US11445770
申请日：2006-06-02
申请人： Jae Chul Om , Nam Kyeong Kim , Se Jun Kim
发明人： Jae Chul Om , Nam Kyeong Kim , Se Jun Kim
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/66825
摘要： A NAND flash memory device and method of manufacturing the same is disclosed. Source and drain select transistor gates are recessed lower than an active region of a semiconductor substrate. A valid channel length of the source and drain select transistor gates is longer than a channel length of memory cell gates. Accordingly, an electric field between a source region and a drain region of the select transistor can be reduced. It is thus possible to prevent program disturbance from occurring in edge memory cells adjacent to the source and drain select transistors in non-selected cell strings.
摘要翻译：公开了NAND闪速存储器件及其制造方法。源极和漏极选择晶体管栅极比半导体衬底的有源区域低。源极和漏极选择晶体管栅极的有效沟道长度比存储器单元栅极的沟道长度长。因此，可以减小选择晶体管的源极区域和漏极区域之间的电场。因此，可以防止在非选择的单元串中与源极和漏极选择晶体管相邻的边缘存储单元中发生程序干扰。

8. 发明授权

US06757210B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US06757210B2
公开(公告)日：2004-06-29
申请号：US10330892
申请日：2002-12-27
申请人： Sang Hoon Hong , Se Jun Kim , Jeong Hoon Kook
发明人： Sang Hoon Hong , Se Jun Kim , Jeong Hoon Kook
IPC分类号： G11C800
CPC分类号： G11C7/1066 , G11C7/10 , G11C2207/002
摘要： A semiconductor memory device configured to share a local I/O line is described herein. The device includes: a memory cell array including a plurality of memory cells; a plurality of bit line sense amplifiers configured to sense and to amplify data stored in the plurality of memory cells; a plurality of bit lines configured to transmit transmitting the data stored in the plurality of memory cells to the plurality of bit line sense amplifiers, respectively; a plurality of bit line dividing circuits configured to selectively divide the plurality of bit lines; and a plurality of column selecting circuits configured to sequentially transmit the data amplified by the plurality of bit line sense amplifiers to corresponding I/O lines.
摘要翻译：这里描述了配置成共享本地I / O线的半导体存储器件。该装置包括：包括多个存储单元的存储单元阵列; 多个位线读出放大器，被配置为感测和放大存储在所述多个存储器单元中的数据; 多个位线，被配置为分别将多个存储单元中存储的数据发送到多个位线读出放大器; 多个位线分割电路，被配置为选择性地划分所述多个位线; 以及多个列选择电路，被配置为顺序地将由多个位线读出放大器放大的数据发送到对应的I / O线。

9. 发明申请

US20080153227A1 NAND FLASH MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译： NAND闪存存储器件及其制造方法
公开(公告)号：US20080153227A1
公开(公告)日：2008-06-26
申请号：US12041949
申请日：2008-03-04
申请人： Jae Chul Om , Nam Kyeong Kim , Se Jun Kim
发明人： Jae Chul Om , Nam Kyeong Kim , Se Jun Kim
IPC分类号： H01L21/336
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/66825
摘要： A NAND flash memory device and method of manufacturing the same is disclosed. Source and drain select transistor gates are recessed lower than an active region of a semiconductor substrate. A valid channel length of the source and drain select transistor gates is longer than a channel length of memory cell gates. Accordingly, an electric field between a source region and a drain region of the select transistor can be reduced. It is thus possible to prevent program disturbance from occurring in edge memory cells adjacent to the source and drain select transistors in non-selected cell strings.
摘要翻译：公开了NAND闪速存储器件及其制造方法。源极和漏极选择晶体管栅极比半导体衬底的有源区域低。源极和漏极选择晶体管栅极的有效沟道长度比存储器单元栅极的沟道长度长。因此，可以减小选择晶体管的源极区域和漏极区域之间的电场。因此，可以防止在非选择的单元串中与源极和漏极选择晶体管相邻的边缘存储单元中发生程序干扰。

10. 发明授权

US06813196B2 High speed interface type semiconductor memory device 失效
标题翻译：高速接口型半导体存储器件
公开(公告)号：US06813196B2
公开(公告)日：2004-11-02
申请号：US09892549
申请日：2001-06-28
申请人： Yong Jae Park , Se Jun Kim
发明人： Yong Jae Park , Se Jun Kim
IPC分类号： G11C700
CPC分类号： G11C7/222 , G11C7/1072 , G11C7/22 , G11C11/4076
摘要： The present invention discloses a high speed interface type semiconductor memory device which can transmit data of a plurality of DRAMs of a module to a controller by using only one data strobe clock signal. The high speed interface type semiconductor memory device includes a DRAM module unit for generating a strobe clock signal for synchronizing a data signal in a read operation in a DRAM farthest from a controller among a plurality of DRAMs, providing the strobe clock signal to the other DRAMs, and transmitting data to the controller in the read operation, and a controller for transmitting a clock signal and data signals synchronized with the clock signal to the plurality of DRAMs, and receiving data signals from the DRAMs.
摘要翻译：本发明公开了一种高速接口型半导体存储器件，其可以通过仅使用一个数据选通时钟信号将模块的多个DRAM的数据传输到控制器。高速接口型半导体存储器件包括：DRAM模块单元，用于产生用于在多个DRAM中与控制器最远的DRAM中的读取操作中的数据信号同步的选通时钟信号，将选通时钟信号提供给其它DRAM ，以及在读取操作中向控制器发送数据，以及用于将时钟信号和与时钟信号同步的数据信号发送到多个DRAM的控制器，以及从DRAM接收数据信号。

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