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1. 发明授权

US09033505B2 Method of tracking a position of an eye and a medical head lamp using the same 有权
标题翻译：跟踪眼睛位置的方法和使用该眼睛的医疗头灯的方法
公开(公告)号：US09033505B2
公开(公告)日：2015-05-19
申请号：US13515581
申请日：2012-01-31
申请人： Sung Min Kim , Sang Hoon Hong , Chan Beom Jeong , Jeon Pil Han , Kwon Hee Lee
发明人： Sung Min Kim , Sang Hoon Hong , Chan Beom Jeong , Jeon Pil Han , Kwon Hee Lee
IPC分类号： A61B3/10 , F21V21/084 , A61B1/06 , A61B3/11 , A61B3/113 , A61B19/00 , G06K9/00 , G02B27/00 , G06T7/00 , G06T7/20 , F21V21/14 , A61B17/00
CPC分类号： A61B1/06 , A61B3/111 , A61B3/113 , A61B90/30 , A61B90/35 , A61B2017/00216 , A61B2090/502 , F21V21/084 , F21V21/145 , G02B27/0093 , G06K9/00604 , G06K9/0061 , G06T7/246 , G06T7/73 , G06T2207/30201
摘要： A method of tracking a position of an eye is provided. The method of tracking a position of an eye includes converting an obtained image into a binary number image, classifying the corner of the eye, maximum and minimum values of a pupil of the eye, and extracting a feature point from the binary number image on which the binarization step is completed, calculating a distance and inclination between the corner and the pupil of the eye using the feature point extracted through the feature point extraction step, and determining a gaze direction of the eye based on the distance and inclination calculated through the distance and inclination calculation step.
摘要翻译：提供了跟踪眼睛位置的方法。跟踪眼睛位置的方法包括将获得的图像转换成二进制数图像，对眼睛的角部进行分类，眼睛的瞳孔的最大值和最小值，以及从二进制数图像中提取特征点完成二值化步骤，使用通过特征点提取步骤提取的特征点计算眼睛的角部和瞳孔之间的距离和倾斜度，并且基于通过距离计算出的距离和倾斜度来确定眼睛的视线方向和倾斜度计算步骤。

2. 发明授权

US07174418B2 Semiconductor memory device for enhancing refresh operation in high speed data access 有权
标题翻译：用于增强高速数据访问中的刷新操作的半导体存储器件
公开(公告)号：US07174418B2
公开(公告)日：2007-02-06
申请号：US10749766
申请日：2003-12-30
申请人： Sang-Hoon Hong , Jin-Hong Ahn , Jae-Bum Ko , Se-Jun Kim
发明人： Sang-Hoon Hong , Jin-Hong Ahn , Jae-Bum Ko , Se-Jun Kim
IPC分类号： G06F12/00
CPC分类号： G11C11/406 , G11C11/40603 , G11C11/40618
摘要： A semiconductor device for refreshing data stored in a memory device includes a cell area having N+1 number of unit cell blocks, each including M number of word lines which respectively are coupled to a plurality of unit cells; a tag block having N+1 number of unit tag blocks, each storing at least one physical cell block address denoting a row address storing a data; and a control block for controlling the tag block and the predetermined cell block table for refreshing the data in the plurality of unit cells coupled to a word line in response to the physical cell block address.
摘要翻译：用于刷新存储在存储器件中的数据的半导体器件包括具有N + 1个单元单元块的单元区域，每个单元单元块包括分别耦合到多个单位单元的M个字线; 具有N + 1个单位标签块的标签块，每个存储表示存储数据的行地址的至少一个物理单元块地址; 以及控制块，用于控制标签块和预定的单元块表，用于响应于物理单元块地址刷新与字线耦合的多个单元单元中的数据。

3. 发明授权

US06987409B2 Analog delay locked loop with tracking analog-digital converter 有权
标题翻译：具有跟踪模数转换器的模拟延迟锁定环
公开(公告)号：US06987409B2
公开(公告)日：2006-01-17
申请号：US10749448
申请日：2003-12-31
申请人： Se-Jun Kim , Sang-Hoon Hong , Jae-Bum Ko
发明人： Se-Jun Kim , Sang-Hoon Hong , Jae-Bum Ko
IPC分类号： H03L7/06
CPC分类号： H03M1/48 , H03L7/0812 , H03L7/0891 , H03L7/0995
摘要： An analog DLL device includes a delay model for modeling delay time for buffering the external clock signal; a phase comparator for comparing a phase of the reference clock signal with an phase of an outputted signal from the delay model; a charge pump for pumping charges; a loop filter for generating a reference voltage; a voltage control delay line and a tracking digital-analog converter which converts the reference voltage to a digital value; and stores the digital value for keeping the reference voltage safely.
摘要翻译：模拟DLL设备包括用于建模用于缓冲外部时钟信号的延迟时间的延迟模型; 相位比较器，用于将参考时钟信号的相位与来自延迟模型的输出信号的相位进行比较; 用于泵送充电的电荷泵; 用于产生参考电压的环路滤波器; 电压控制延迟线和将参考电压转换为数字值的跟踪数模转换器; 并存储用于保持参考电压的数字值。

4. 发明授权

US06930630B1 Analog-to-digital converter 有权
标题翻译：模数转换器
公开(公告)号：US06930630B1
公开(公告)日：2005-08-16
申请号：US11021963
申请日：2004-12-23
申请人： Se-Jun Kim , Sang-Hoon Hong , Jae-Bum Ko
发明人： Se-Jun Kim , Sang-Hoon Hong , Jae-Bum Ko
IPC分类号： H03M1/06 , H03M1/48 , H03M1/68 , H03M1/12
CPC分类号： H03M1/0607 , H03M1/48 , H03M1/687
摘要： An analog-to-digital converter outputs a reliable digital value corresponding to an input analog value without regard to variation of process, temperature and driving voltage. The analog-to-digital converter includes a voltage comparator for comparing an input voltage with a comparison voltage, a binary up/down counter for up/down converting an outputted binary digital code based on the comparison result of the voltage comparator, a digital-to-analog converting unit for converting the binary digital code that is transferred from the up/down counter as the comparison voltage by using a bias voltage and an offset voltage and for outputting a feedback upper threshold voltage and a feedback lower threshold voltage, and a feedback bias unit for comparing the feedback upper threshold voltage with an upper threshold voltage having the maximum level of the input voltage to output the bias voltage and comparing the feedback lower threshold voltage with a lower threshold voltage having the minimum level of the input voltage to output the offset voltage.
摘要翻译：模数转换器输出对应于输入模拟值的可靠数字值，而不考虑过程，温度和驱动电压的变化。模数转换器包括用于将输入电压与比较电压进行比较的电压比较器，用于根据电压比较器的比较结果对输出的二进制数字代码进行上/下转换的二进制递增/递减计数器，模拟转换单元，用于通过使用偏置电压和偏移电压来转换从上/下计数器传送的二进制数字代码作为比较电压，并输出反馈上阈值电压和反馈下阈值电压，以及反馈偏置单元，用于将反馈上阈值电压与具有输入电压的最大电平的上阈值电压进行比较，以输出偏置电压，并将反馈下阈值电压与具有输入电压的最小电平的较低阈值电压进行比较以输出偏移电压。

5. 发明授权

US06466501B2 Semiconductor memory device having sense amplifier and method for driving sense amplifier 失效
标题翻译：具有读出放大器和驱动读出放大器的方法的半导体存储器件
公开(公告)号：US06466501B2
公开(公告)日：2002-10-15
申请号：US09891507
申请日：2001-06-27
申请人： Si Hong Kim , Sang Hoon Hong
发明人： Si Hong Kim , Sang Hoon Hong
IPC分类号： G11C702
CPC分类号： G11C7/065 , G11C7/062
摘要： A semiconductor memory device with a sense amplifier of the present invention reduces an offset voltage between input and output terminals of the sense amplifier to improve sensing sensitivity, whereby improving cell density of the device as well as achieving a stable operation in low voltage. For the purpose of achieving the foregoing objects, the semiconductor memory device with the sense amplifier includes a plurality of switch means for sequentially turning an amplifying method of the sense amplifier to rapidly sense and sufficiently amplify the data loaded on a bit line in response to a plurality of switch control signals.
摘要翻译：具有本发明的读出放大器的半导体存储器件减少了读出放大器的输入和输出端之间的偏移电压，以提高感测灵敏度，从而提高器件的单元密度以及实现低电压稳定运行。为了实现上述目的，具有读出放大器的半导体存储器件包括多个开关装置，用于顺序地转换读出放大器的放大方法，以响应于一个位置线快速地感测和充分放大加载在位线上的数据多个开关控制信号。

6. 发明申请

US20110085405A1 SEMICONDUCTOR MEMORY DEVICE HAVING ADVANCED TAG BLOCK 审中-公开
标题翻译：具有高级标签块的半导体存储器件
公开(公告)号：US20110085405A1
公开(公告)日：2011-04-14
申请号：US12969483
申请日：2010-12-15
申请人： Sang-Hoon Hong , Jin-Hong Ahn , Jae-Bum Ko , Se-Jun Kim
发明人： Sang-Hoon Hong , Jin-Hong Ahn , Jae-Bum Ko , Se-Jun Kim
IPC分类号： G11C8/00 , G11C8/10
CPC分类号： G11C8/06
摘要： A semiconductor memory device includes a row decoding block for decoding an inputted address to thereby generate a logical unit cell block address and a decoded word line address; a tag block for converting the logical unit cell block address into a physical unit cell block address; a decoded address latching block for latching the decoded word line address to thereby output the decoded word line address as a word line activation signal in response to the physical unit cell block; and a cell area for outputting a data, which is stored therein, in response to the word line activation signal.
摘要翻译：一种半导体存储器件包括用于对输入的地址进行解码的行解码块，从而生成逻辑单元单元块地址和解码字线地址; 用于将逻辑单元单元块地址转换为物理单元单元块地址的标签块; 解码地址锁存块，用于锁存解码字线地址，从而响应于物理单元单元块将解码字线地址作为字线激活信号输出; 以及用于响应于字线激活信号输出存储在其中的数据的单元区域。

7. 发明授权

US07870362B2 Semiconductor memory device having advanced tag block 失效
标题翻译：具有高级标签块的半导体存储器件
公开(公告)号：US07870362B2
公开(公告)日：2011-01-11
申请号：US10879660
申请日：2004-06-28
申请人： Sang-Hoon Hong , Jin-Hong Ahn , Jae-Bum Ko , Se-Jun Kim
发明人： Sang-Hoon Hong , Jin-Hong Ahn , Jae-Bum Ko , Se-Jun Kim
IPC分类号： G06F12/00 , G06F12/02 , G06F12/08 , G06F12/10
CPC分类号： G11C8/06
摘要： A semiconductor memory device includes a row decoding block for decoding an inputted address to thereby generate a logical unit cell block address and a decoded word line address; a tag block for converting the logical unit cell block address into a physical unit cell block address; a decoded address latching block for latching the decoded word line address to thereby output the decoded word line address as a word line activation signal in response to the physical unit cell block; and a cell area for outputting a data, which is stored therein, in response to the word line activation signal.
摘要翻译：一种半导体存储器件包括用于对输入的地址进行解码的行解码块，从而生成逻辑单元单元块地址和解码字线地址; 用于将逻辑单元单元块地址转换为物理单元单元块地址的标签块; 解码地址锁存块，用于锁存解码字线地址，从而响应于物理单元单元块将解码字线地址作为字线激活信号输出; 以及用于响应于字线激活信号输出存储在其中的数据的单元区域。

8. 发明授权

US07304877B2 Semiconductor memory device with uniform data access time 有权
标题翻译：具有统一数据存取时间的半导体存储器
公开(公告)号：US07304877B2
公开(公告)日：2007-12-04
申请号：US11023659
申请日：2004-12-29
申请人： Jae-Bum Ko , Sang-Hoon Hong , Se-Jun Kim
发明人： Jae-Bum Ko , Sang-Hoon Hong , Se-Jun Kim
IPC分类号： G11C5/02
CPC分类号： G11C8/12 , G11C5/025 , G11C5/063 , G11C2207/105
摘要： A semiconductor memory device includes: a core region having a plurality of bank sets for outputting/storing a data in response to an inputted address, wherein each bank set includes one bank, one row address control unit and two column address control units; and a peripheral region having two pad groups, wherein two pad groups are respectively located at the opposite side of the core region.
摘要翻译：半导体存储器件包括：具有多个存储体组的核心区域，用于响应于输入的地址输出/存储数据，其中每个存储体组包括一个存储体，一个行地址控制单元和两个列地址控制单元; 以及具有两个焊盘组的周边区域，其中两个焊盘组分别位于芯区域的相对侧。

9. 发明授权

US07277977B2 DRAM for high-speed data access 失效
标题翻译： DRAM用于高速数据访问
公开(公告)号：US07277977B2
公开(公告)日：2007-10-02
申请号：US10330482
申请日：2002-12-30
申请人： Jeong-Hoon Kook , Sang-Hoon Hong , Se-Jun Kim
发明人： Jeong-Hoon Kook , Sang-Hoon Hong , Se-Jun Kim
IPC分类号： G06F12/00
CPC分类号： G06F12/0893 , G06F12/0607 , G06F2212/3042 , G11C11/4076 , G11C2207/2245
摘要： A DRAM with a general interleaving scheme for data input/output uses a normal bank structure. The DRAM provides a high-performance without consideration of a data access pattern. In order to implement the high-performance, the DRAM includes a plurality of normal banks, at least one cache bank, which has the same data access scheme with the normal banks, for selectively storing data with a normal bank selected at a read mode and a controller for controlling the access to the cache bank and the selected normal bank when continuous read commands are occurred to the selected normal bank.
摘要翻译：具有用于数据输入/输出的通用交织方案的DRAM使用正常的存储体结构。 DRAM提供高性能而不考虑数据访问模式。为了实现高性能，DRAM包括多个正常库，至少一个与正常库具有相同数据访问方案的高速缓存组，用于选择性地以读取模式选择存储与正常存储库的数据;以及控制器，用于在连续读取命令发生到所选择的法线段时控制对高速缓存组和所选择的法线库的访问。

10. 发明授权

US07075847B2 Semiconductor memory device having optimum refresh cycle according to temperature variation 有权
标题翻译：具有根据温度变化的最佳刷新周期的半导体存储器件
公开(公告)号：US07075847B2
公开(公告)日：2006-07-11
申请号：US10877886
申请日：2004-06-23
申请人： Se-Jun Kim , Sang-Hoon Hong , Jae-Bum Ko
发明人： Se-Jun Kim , Sang-Hoon Hong , Jae-Bum Ko
IPC分类号： G11C7/00
CPC分类号： G11C11/40626 , G11C11/406
摘要： An apparatus for controlling a refresh cycle in a semiconductor memory device includes a temperature detection controller for generating a detection control signal and a converting control signal; a temperature detection block, which is enabled by the detection control signal, for generating an analog detection voltage in response to a temperature variation; an analog to digital converter, which is enabled by the converting control signal, for converting the analog detection voltage into a digital control code; and a refresh controller for generating a refresh cycle control signal based on the digital control code in order to control the refresh cycle.
摘要翻译：一种用于控制半导体存储装置中的刷新周期的装置，包括用于产生检测控制信号和转换控制信号的温度检测控制器; 由所述检测控制信号启用的温度检测块，用于响应温度变化产生模拟检测电压; 模数转换器，其由转换控制信号使能，用于将模拟检测电压转换为数字控制码; 以及刷新控制器，用于基于数字控制码产生刷新周期控制信号，以便控制刷新周期。

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