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11. 发明申请

US20100237354A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100237354A1
公开(公告)日：2010-09-23
申请号：US12794120
申请日：2010-06-04
申请人： Yoshiaki YAMAMOTO , Koichiro TANAKA , Atsuo ISOBE , Daisuke OHGARANE , Shunpei YAMAZAKI
发明人： Yoshiaki YAMAMOTO , Koichiro TANAKA , Atsuo ISOBE , Daisuke OHGARANE , Shunpei YAMAZAKI
IPC分类号： H01L29/786
CPC分类号： H01L21/6835 , H01L21/02532 , H01L21/02683 , H01L21/02691 , H01L21/84 , H01L23/544 , H01L24/29 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/85 , H01L27/12 , H01L29/78603 , H01L29/78648 , H01L2221/6835 , H01L2223/5442 , H01L2223/54426 , H01L2223/6677 , H01L2224/16 , H01L2224/2919 , H01L2224/2929 , H01L2224/293 , H01L2224/32225 , H01L2224/48091 , H01L2224/48464 , H01L2224/73265 , H01L2224/83191 , H01L2224/838 , H01L2224/85 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01018 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/0104 , H01L2924/01041 , H01L2924/01042 , H01L2924/01044 , H01L2924/01045 , H01L2924/0106 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01076 , H01L2924/01077 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/04941 , H01L2924/04953 , H01L2924/0665 , H01L2924/0781 , H01L2924/10253 , H01L2924/12044 , H01L2924/14 , H01L2924/15788 , H01L2924/19043 , H01L2924/30105 , H01Q1/38 , H01Q9/285 , H01Q23/00 , Y10S438/982 , H01L2924/00 , H01L2224/29099 , H01L2224/29199 , H01L2224/29299 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： It is an object of the present invention to provide a method of separating a thin film transistor, and circuit or a semiconductor device including the thin film transistor from a substrate by a method different from that disclosed in the patent document 1 and transposing the thin film transistor, and the circuit or the semiconductor device to a substrate having flexibility. According to the present invention, a large opening or a plurality of openings is formed at an insulating film, a conductive film connected to a thin film transistor is formed at the opening, and a peeling layer is removed, then, a layer having the thin film transistor is transposed to a substrate provided with a conductive film or the like. A thin film transistor according to the present invention has a semiconductor film which is crystallized by laser irradiation and prevents a peeling layer from exposing at laser irradiation not to be irradiated with laser light.
摘要翻译：本发明的目的是提供一种通过与专利文献1中公开的方法不同的方法从衬底分离薄膜晶体管和包括薄膜晶体管的电路或半导体器件的方法，并且将薄膜晶体管，以及电路或半导体器件到具有柔性的衬底。根据本发明，在绝缘膜上形成大的开口或多个开口，在开口处形成连接到薄膜晶体管的导电膜，并且去除剥离层，然后，将具有薄的薄膜晶体管转置到具有导电膜等的基板上。根据本发明的薄膜晶体管具有通过激光照射而结晶的半导体膜，并且防止剥离层在不被激光照射的激光照射下曝光。

12. 发明申请

US20090078970A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090078970A1
公开(公告)日：2009-03-26
申请号：US12209696
申请日：2008-09-12
申请人： Shunpei YAMAZAKI , Atsuo ISOBE , Hiromichi GODO , Yutaka OKAZAKI
发明人： Shunpei YAMAZAKI , Atsuo ISOBE , Hiromichi GODO , Yutaka OKAZAKI
IPC分类号： H01L27/12
CPC分类号： H01L21/8221 , H01L27/0688 , H01L2224/16225 , H01L2224/16227 , H01L2224/32245 , H01L2924/00011 , H01L2924/00014 , H01L2224/29099 , H01L2224/13099 , H01L2224/80001
摘要： A semiconductor device is demonstrated in which a plurality of field-effect transistors is stacked with an interlayer insulating layer interposed therebetween over a substrate having an insulating surface. Each of the plurality of filed-effect transistors has a semiconductor layer which is prepared by a process including separation of the semiconductor layer from a semiconductor substrate followed by bonding thereof over the substrate. Each of the plurality of field-effect transistors is covered with an insulating film which provides distortion of the semiconductor layer. Furthermore, the crystal axis of the semiconductor layer, which is parallel to the crystal plane thereof, is set to a channel length direction of the semiconductor layer, which enables production of the semiconductor device with high performance and low power consumption having an SOI structure.
摘要翻译：示出了一种半导体器件，其中在具有绝缘表面的衬底上层叠多个场效应晶体管，层间绝缘层介于其间。多个场效应晶体管中的每一个具有半导体层，该半导体层通过包括将半导体层与半导体衬底分离并随后在衬底上结合的工艺制备。多个场效应晶体管中的每一个被覆盖有提供半导体层失真的绝缘膜。此外，将半导体层的与其晶面平行的晶轴设定为半导体层的沟道长度方向，能够制造具有SOI结构的高性能，低功耗的半导体器件。

13. 发明申请

US20100237418A1 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100237418A1
公开(公告)日：2010-09-23
申请号：US12793237
申请日：2010-06-03
申请人： Shunpei YAMAZAKI , Atsuo ISOBE , Tetsuji YAMAGUCHI , Hiromichi GODO
发明人： Shunpei YAMAZAKI , Atsuo ISOBE , Tetsuji YAMAGUCHI , Hiromichi GODO
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L27/127 , H01L27/1214 , H01L27/1285 , H01L27/1288 , H01L27/13 , H01L29/458 , H01L29/4908 , H01L29/78621 , H01L29/78624
摘要： It is an object of the present invention to manufacture a thin film transistor having a required property without complicating steps and devices. It is another object of the present invention to provide a technique for manufacturing a semiconductor device having high reliability and better electrical characteristics with a higher yield at lower cost. In the present invention, a lightly doped impurity region is formed in a source region side or a drain region side of a semiconductor layer covered with a gate electrode layer in a thin film transistor. The semiconductor layer is doped diagonally to the surface thereof using the gate electrode layer as a mask to form the lightly doped impurity region. Therefore, the properties of the thin film transistor can be minutely controlled.
摘要翻译：本发明的目的是制造具有所需性能的薄膜晶体管，而不会使步骤和装置复杂化。本发明的另一个目的是提供一种以更低的成本制造具有高可靠性和更好的电气特性并以较高产量获得的半导体器件的技术。在本发明中，在薄膜晶体管中由栅极电极层覆盖的半导体层的源区域侧或漏极区侧形成有轻掺杂杂质区。使用栅极电极层作为掩模将半导体层以其对面的方式对角地掺杂以形成轻掺杂杂质区域。因此，可以精细地控制薄膜晶体管的性质。

14. 发明申请

US20090079000A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090079000A1
公开(公告)日：2009-03-26
申请号：US12209739
申请日：2008-09-12
申请人： Shunpei YAMAZAKI , Atsuo ISOBE , Hiromichi GODO , Yutaka OKAZAKI
发明人： Shunpei YAMAZAKI , Atsuo ISOBE , Hiromichi GODO , Yutaka OKAZAKI
IPC分类号： H01L27/08
CPC分类号： H01L27/1266 , H01L21/823807 , H01L21/823871 , H01L23/433 , H01L23/481 , H01L23/552 , H01L27/0688 , H01L27/1214 , H01L27/1229 , H01L29/7843 , H01L2224/16 , H01L2224/73253 , H01L2924/01046 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/12044 , H01L2924/16152 , H01L2924/16195
摘要： An object is to realize high performance and low power consumption in a semiconductor device having an SOI structure. In addition, another object is to provide a semiconductor device having a high performance semiconductor element which is more highly integrated. A semiconductor device is such that a plurality of n-channel field-effect transistors and p-channel field-effect transistors are stacked with an interlayer insulating layer interposed therebetween over a substrate having an insulating surface. By controlling a distortion caused to a semiconductor layer due to an insulating film having a stress, a plane orientation of the semiconductor layer, and a crystal axis in a channel length direction, difference in mobility between the n-channel field-effect transistor and the p-channel field-effect transistor can be reduced, whereby current driving capabilities and response speeds of the n-channel field-effect transistor and the p-channel field-effect can be comparable.
摘要翻译：目的是在具有SOI结构的半导体器件中实现高性能和低功耗。此外，另一个目的是提供一种具有更高集成度的高性能半导体元件的半导体器件。半导体器件使得多个n沟道场效应晶体管和p沟道场效应晶体管层叠在其间具有绝缘表面的衬底之间的层间绝缘层。通过控制由于具有应力的绝缘膜，半导体层的平面取向和沟道长度方向的晶轴引起的半导体层的失真，n沟道场效应晶体管和可以减小p沟道场效应晶体管，由此n沟道场效应晶体管的电流驱动能力和响应速度与p沟道场效应相当。

15. 发明申请

US20120032236A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120032236A1
公开(公告)日：2012-02-09
申请号：US13277489
申请日：2011-10-20
申请人： Shunpei YAMAZAKI , Atsuo ISOBE , Hiromichi GODO , Yutaka OKAZAKI
发明人： Shunpei YAMAZAKI , Atsuo ISOBE , Hiromichi GODO , Yutaka OKAZAKI
IPC分类号： H01L27/092
CPC分类号： H01L27/1266 , H01L21/823807 , H01L21/823871 , H01L23/433 , H01L23/481 , H01L23/552 , H01L27/0688 , H01L27/1214 , H01L27/1229 , H01L29/7843 , H01L2224/16 , H01L2224/73253 , H01L2924/01046 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/12044 , H01L2924/16152 , H01L2924/16195
摘要： An object is to realize high performance and low power consumption in a semiconductor device having an SOI structure. In addition, another object is to provide a semiconductor device having a high performance semiconductor element which is more highly integrated. A semiconductor device is such that a plurality of n-channel field-effect transistors and p-channel field-effect transistors are stacked with an interlayer insulating layer interposed therebetween over a substrate having an insulating surface. By controlling a distortion caused to a semiconductor layer due to an insulating film having a stress, a plane orientation of the semiconductor layer, and a crystal axis in a channel length direction, difference in mobility between the n-channel field-effect transistor and the p-channel field-effect transistor can be reduced, whereby current driving capabilities and response speeds of the n-channel field-effect transistor and the p-channel field-effect can be comparable.
摘要翻译：目的是在具有SOI结构的半导体器件中实现高性能和低功耗。此外，另一个目的是提供一种具有更高集成度的高性能半导体元件的半导体器件。半导体器件使得多个n沟道场效应晶体管和p沟道场效应晶体管层叠在其间具有绝缘表面的衬底之间的层间绝缘层。通过控制由于具有应力的绝缘膜，半导体层的平面取向和沟道长度方向的晶轴引起的半导体层的失真，n沟道场效应晶体管和可以减小p沟道场效应晶体管，由此n沟道场效应晶体管的电流驱动能力和响应速度与p沟道场效应相当。

16. 发明申请

US20100297809A1 ORGANIC TRANSISTOR, MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND ORGANIC TRANSISTOR 有权
标题翻译：有机晶体管，半导体器件和有机晶体管的制造方法
公开(公告)号：US20100297809A1
公开(公告)日：2010-11-25
申请号：US12850652
申请日：2010-08-05
申请人： Ryota IMAHAYASHI , Shinobu FURUKAWA , Atsuo ISOBE , Yasuyuki ARAI , Shunpei YAMAZAKI
发明人： Ryota IMAHAYASHI , Shinobu FURUKAWA , Atsuo ISOBE , Yasuyuki ARAI , Shunpei YAMAZAKI
IPC分类号： H01L51/40
CPC分类号： H01L51/0512 , H01L21/02175 , H01L21/02244 , H01L21/02247 , H01L21/02252 , H01L21/31683 , H01L51/0002 , H01L51/0055 , H01L51/0525 , H01L51/0541 , H01L51/0545 , H01L51/0566
摘要： It is an object to form a high quality gate insulating film which is dense and has a strong insulation resistance property, and to propose a high reliable organic transistor in which a tunnel leakage current is little. One mode of the organic transistor of the present invention has a step of forming the gate insulating film by forming the conductive layer which becomes the gate electrode activating oxygen (or gas including oxygen) or nitrogen (or gas including nitrogen) or the like using dense plasma in which density of electron is 1011 cm−3 or more, and electron temperature is a range of 0.2 eV to 2.0 eV with plasma activation, and reacting directly with a portion of the conductive layer which becomes the gate electrode to be insulated.
摘要翻译：本发明的目的是形成致密且具有很强绝缘电阻特性的高质量栅极绝缘膜，并且提出了隧道泄漏电流很小的高可靠性有机晶体管。本发明的有机晶体管的一种模式具有如下步骤：通过使用密集的方法形成作为活化氧（或含氧气体）或氮（或含氮气体）的栅极的导电层形成栅极绝缘膜电子密度为1011cm -3以上的等离子体，等离子体活化时电子温度为0.2eV〜2.0eV的范围，直接与成为要被绝缘的栅电极的导体层的一部分反应。

17. 发明申请

US20090098720A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090098720A1
公开(公告)日：2009-04-16
申请号：US12334589
申请日：2008-12-15
申请人： Atsuo ISOBE , Satoshi MURAKAMI , Tamae TAKANO , Shunpei YAMAZAKI
发明人： Atsuo ISOBE , Satoshi MURAKAMI , Tamae TAKANO , Shunpei YAMAZAKI
IPC分类号： H01L21/28 , H01L21/31
CPC分类号： H01L29/66757 , H01L27/12 , H01L27/1248 , H01L29/42384
摘要： A manufacturing method of a semiconductor device of the present invention includes the steps of forming a first insulating film over a substrate, forming a semiconductor film over the first insulating film, oxidizing or nitriding the semiconductor film by conducting a plasma treatment to the semiconductor film under a condition of an electron density of 1×1011 cm−3 or more and 1×1013 cm−3 or less and an electron temperature of 0.5 eV or more and 1.5 eV or less, using a high frequency wave, forming a second insulating film to cover the semiconductor film, forming a gate electrode over the second insulating film, forming a third insulating film to cover the gate electrode, and forming a conductive film over the third insulating film.
摘要翻译：本发明的半导体器件的制造方法包括以下步骤：在衬底上形成第一绝缘膜，在第一绝缘膜上形成半导体膜，通过对半导体膜进行等离子体处理来对半导体膜进行氧化或氮化使用高频波，电子密度为1×10 11 cm -3以上且1×10 13 cm -3以下，电子温度为0.5eV以上且1.5eV以下的条件，形成覆盖半导体的第2绝缘膜在所述第二绝缘膜上形成栅电极，形成第三绝缘膜以覆盖所述栅电极，以及在所述第三绝缘膜上形成导电膜。

18. 发明申请

US20120267709A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120267709A1
公开(公告)日：2012-10-25
申请号：US13446026
申请日：2012-04-13
申请人： Atsuo ISOBE , Toshinari SASAKI
发明人： Atsuo ISOBE , Toshinari SASAKI
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/78603 , H01L29/4236 , H01L29/42384 , H01L29/7869 , H01L29/78696
摘要： To provide a highly reliable semiconductor device. To provide a semiconductor device which prevents a defect and achieves miniaturization. An oxide semiconductor layer in which the thickness of a region serving as a source region or a drain region is larger than the thickness of a region serving as a channel formation region is formed in contact with an insulating layer including a trench. In a transistor including the oxide semiconductor layer, variation in threshold voltage, degradation of electric characteristics, and shift to normally on can be suppressed and source resistance or drain resistance can be reduced, so that the transistor can have high reliability.
摘要翻译：提供高度可靠的半导体器件。提供一种防止缺陷并实现小型化的半导体器件。形成与包括沟槽的绝缘层接触的用作源区或漏区的区域的厚度大于用作沟道形成区的区的厚度的氧化物半导体层。在包括氧化物半导体层的晶体管中，可以抑制阈值电压的变化，电特性的劣化和正常的导通，可以降低源电阻或漏极电阻，从而晶体管可以具有高的可靠性。

19. 发明申请

US20110297928A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110297928A1
公开(公告)日：2011-12-08
申请号：US13117588
申请日：2011-05-27
申请人： Atsuo ISOBE , Yoshinori IEDA , Keitaro IMAI , Kiyoshi KATO , Yuto YAKUBO , Yuki HATA
发明人： Atsuo ISOBE , Yoshinori IEDA , Keitaro IMAI , Kiyoshi KATO , Yuto YAKUBO , Yuki HATA
IPC分类号： H01L27/105
CPC分类号： H01L27/105 , H01L27/1052 , H01L27/108 , H01L27/1156 , H01L27/1225 , H01L28/60
摘要： The semiconductor device is provided in which a plurality of memory cells each including a first transistor, a second transistor, and a capacitor is arranged in matrix and a wiring (also referred to as a bit line) for connecting one of the memory cells and another one of the memory cells and a source or drain region in the first transistor are electrically connected through a conductive layer and a source or drain electrode in the second transistor provided therebetween. With this structure, the number of wirings can be reduced in comparison with a structure in which the source or drain electrode in the first transistor and the source or drain electrode in the second transistor are connected to different wirings. Thus, the integration degree of a semiconductor device can be increased.
摘要翻译：提供了一种半导体器件，其中包括第一晶体管，第二晶体管和电容器的多个存储单元被布置成矩阵，并且布线（也称为位线）用于连接其中一个存储单元和另一个第一晶体管中的一个存储单元和源极或漏极区域通过导电层和设置在其间的第二晶体管中的源极或漏极电连接。利用这种结构，与第一晶体管中的源极或漏极以及第二晶体管中的源极或漏极连接到不同布线的结构相比，可以减少布线的数量。因此，可以提高半导体器件的集成度。

20. 发明申请

US20080142921A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20080142921A1
公开(公告)日：2008-06-19
申请号：US11955496
申请日：2007-12-13
申请人： Atsuo ISOBE , Suguru OZAWA
发明人： Atsuo ISOBE , Suguru OZAWA
IPC分类号： H01L27/12 , H01L21/22
CPC分类号： H01L27/1266 , H01L27/124 , H01L29/458
摘要： To fabricate a Schottky barrier diode in which a decrease in on current due to parasitic resistance is suppressed, variations in on current are suppressed, and an increase in off current is suppressed. The fabricating method includes the steps of forming an island-shape semiconductor film; doping the island-shape semiconductor film with a first impurity element to form a first impurity region; forming an insulating film so as to cover the island-shape semiconductor film; etching the insulating film to form a first opening and a second opening that partly expose the first impurity region; forming a mask over the insulating film so as to cover the first opening and expose the second opening; doping the first impurity region with a second impurity element to form a second impurity region; and forming a first wiring in contact with the first impurity region exposed at the first opening, and forming a second wiring in contact with the second impurity region exposed at the second opening. Since the second impurity element is added through the second opening, the periphery of the second opening is also doped with a slight amount of the second impurity element. Therefore, the first impurity region and the second wiring are located away a short distance from each other such that they are not shorted.
摘要翻译：为了制造由于寄生电阻引起的导通电流的降低被抑制的肖特基势垒二极管，抑制了导通电流的变化，抑制了关断电流的增大。该制造方法包括形成岛状半导体膜的步骤; 用第一杂质元素掺杂岛状半导体膜以形成第一杂质区; 形成绝缘膜以覆盖岛状半导体膜; 蚀刻绝缘膜以形成部分地暴露第一杂质区的第一开口和第二开口; 在所述绝缘膜上形成掩模以覆盖所述第一开口并暴露所述第二开口; 用第二杂质元素掺杂第一杂质区以形成第二杂质区; 以及形成与在所述第一开口处暴露的所述第一杂质区域接触的第一布线，以及形成与在所述第二开口处露出的所述第二杂质区域接触的第二布线。由于通过第二开口添加第二杂质元素，所以第二开口的周边也掺杂有少量的第二杂质元素。因此，第一杂质区域和第二布线彼此距离很短，使得它们不短路。

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