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11. 发明授权

US06479307B2 Method of monitoring loss of silicon nitride 失效
标题翻译：监测氮化硅损失的方法
公开(公告)号：US06479307B2
公开(公告)日：2002-11-12
申请号：US09854007
申请日：2001-05-10
申请人： Shu-Ya Chuang , Gow-Wei Sun , Ga-Ming Hong , Steven Chen , Pei-Jen Wang
发明人： Shu-Ya Chuang , Gow-Wei Sun , Ga-Ming Hong , Steven Chen , Pei-Jen Wang
IPC分类号： H01L2166
CPC分类号： H01L22/34 , H01L21/76802
摘要： A method of monitoring loss of silicon nitride, used to monitor the loss of a first etch stop layer below a first insulating layer in a first contact opening opening after the first contact opening is formed in the first insulating layer over a device region and scribe line of a wafer. A dummy wafer is provided on which stacks in sequence a second etch stop layer and a second insulating layer. The second insulating layer is patterned by removing a portion of the second insulating layer, so that a monitoring opening that exposes the second etch stop layer and a second contact opening are formed in the second insulating layer. A first measuring step is performed to measure a first thickness loss and a second thickness loss from the second etch stop layer exposed respectively by the monitoring opening and the second contact opening on the dummy wafer. And a correlation is established from the first and second thickness losses. A second measuring step is performed to measure a third thickness loss from the first etch stop layer exposed by the monitoring opening on the wafer. The result is then compared with the correlation to deduce a fourth thickness loss from the first contact opening on the wafer.
摘要翻译：一种监测氮化硅损失的方法，用于监测在第一接触开口之后的第一绝缘层中的第一绝缘层下方的第一蚀刻停止层的损失，该第一绝缘层在第一绝缘层上形成在器件区域和划线的晶片。提供了一个虚设晶片，其上依次叠置有第二蚀刻停止层和第二绝缘层。通过去除第二绝缘层的一部分来图形化第二绝缘层，使得在第二绝缘层中形成暴露第二蚀刻停止层和第二接触开口的监视开口。执行第一测量步骤以测量分别由伪晶片上的监视开口和第二接触开口暴露的第二蚀刻停止层的第一厚度损失和第二厚度损失。并且从第一和第二厚度损失建立相关性。执行第二测量步骤以测量由晶片上的监视开口暴露的第一蚀刻停止层的第三厚度损失。然后将结果与相关性进行比较以推导出晶片上的第一接触开口的第四厚度损失。

12. 发明授权

US06172388B2 Method of fabricating dynamic random access memories 失效
标题翻译：制作动态随机存取存储器的方法
公开(公告)号：US06172388B2
公开(公告)日：2001-01-09
申请号：US09270027
申请日：1999-03-16
申请人： Shu-Ya Chuang
发明人： Shu-Ya Chuang
IPC分类号： H01L27108
CPC分类号： H01L27/108 , H01L27/10808
摘要： An improved method for fabricating DRAM with a thin film transistor can increase reading and writing speed. In this method, a substrate with a transfer transistor, a word line, a bit line and an interlayer dielectric layer is provided. A bit line contact and a terminal contact are formed in the interlayer dielectric layer. The bit line contact couples to the bit line and the terminal contact couples to the transfer transistor. The terminal contact is a T-shaped structure. An oxide layer is formed to cover the interlayer dielectric layer and the terminal contact to expose the bit line contact. A polysilicon layer is formed to cover the oxide layer and the bit line contact. An ion implantation step is performed to form a first doped region and a second doped region in the polysilicon layer. The polysilicon layer is patterned to make the first doped region into a source region and to make the second doped region into a drain region. The drain region is on one side of the terminal contact corresponding to the source region.
摘要翻译：用薄膜晶体管制造DRAM的改进方法可以提高读写速度。在该方法中，提供具有转移晶体管，字线，位线和层间电介质层的衬底。在层间电介质层中形成位线接触和端子接触。位线接触耦合到位线，并且端子触点耦合到转移晶体管。端子触点是T形结构。形成氧化物层以覆盖层间电介质层和端子触点以暴露位线接触。形成多晶硅层以覆盖氧化物层和位线接触。执行离子注入步骤以在多晶硅层中形成第一掺杂区域和第二掺杂区域。图案化多晶硅层以使第一掺杂区域成为源极区域并使第二掺杂区域成为漏极区域。漏极区域位于与源极区域对应的端子触点的一侧。

13. 发明授权

US5960282A Method for fabricating a dynamic random access memory with a vertical pass transistor 失效
标题翻译：用垂直传输晶体管制造动态随机存取存储器的方法
公开(公告)号：US5960282A
公开(公告)日：1999-09-28
申请号：US206065
申请日：1998-12-04
申请人： Shu-Ya Chuang
发明人： Shu-Ya Chuang
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10876 , H01L27/10808 , H01L27/10823
摘要： A method for fabricating a DRAM cell with a vertical pass transistor is provided. The method of the invention includes sequentially forming a drain region, a gate structure, a source region, and a capacitor on a semiconductor substrate in a vertical distribution so that an area used by the drain region is the total area used by the DRAM cell on the substrate. In other world, the gate structure, the source region, and the capacitor are formed above the semiconductor substrate without direct contact.
摘要翻译：提供了一种用垂直传输晶体管制造DRAM单元的方法。本发明的方法包括在垂直分布中在半导体衬底上依次形成漏极区，栅极结构，源区和电容，使得漏极区所用的区域是由DRAM单元使用的总面积底物。在另一方面，栅极结构，源极区和电容器形成在半导体衬底的上方，而不会直接接触。

14. 发明授权

US06774002B2 Structure and method for forming self-aligned bipolar junction transistor with expitaxy base 有权
公开(公告)号：US06774002B2
公开(公告)日：2004-08-10
申请号：US10279549
申请日：2002-10-23
申请人： Shu-Ya Chuang
发明人： Shu-Ya Chuang
IPC分类号： H01L21331
CPC分类号： H01L29/66287
摘要： The present invention proposes a novel method to fabricate a Bipolar Junction Transistor device. The steps of the present invention include forming a shallow trench isolation structure in a substrate. An oxide layer is formed on the substrate. Subsequently, a polysilicon layer is next formed on the oxide layer, and the polysilicon layer has first type ion. Successively, a polysilicon layer is patterned on the oxide layer. The next step is to perform a second type ion implantation, thereby forming a collector region in the substrate and below the emitter window. The oxide layer is removed inside the emitter window. An expitaxy base is then formed on the polysilicon layer and substrate, thereby forming base region on the collector region, wherein the expitaxy base has the first type ion. After the expitaxy base is formed, a dielectric layer is formed over the expitaxy base. Next, the dielectric layer is etched to form inner spacer on sidewalls of the expitaxy base inside the emitter window. A second polysilicon layer is formed over the expitaxy base and the emitter window, wherein the second polysilicon layer has the second type ion. Finally, an etching process is introduced to etch the second polysilicon layer to form emitter plug. That is self-aligned to the emitter window.

15. 发明授权

US06548373B2 Method for forming shallow trench isolation structure 失效
标题翻译：浅沟槽隔离结构的形成方法
公开(公告)号：US06548373B2
公开(公告)日：2003-04-15
申请号：US09821432
申请日：2001-03-29
申请人： Shu-Ya Chuang , Aaron Lee
发明人： Shu-Ya Chuang , Aaron Lee
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： A method for forming a STI structure. A pad oxide layer is formed over a substrate. A sacrificial layer is formed over the pad oxide layer. A mask layer is formed over the sacrificial layer. The mask layer is patterned, and then the sacrificial layer, the pad oxide layer and the substrate are etched in sequence to form a trench. A thermal oxidation is performed to form a liner layer along the exposed sidewalls of the sacrificial layer and the exposed substrate surface inside the trench. Insulation material is deposited over the substrate, completely filling the trench. A chemical-mechanical polishing step is performed to remove a portion of the insulation layer and a portion of the mask layer so that an insulation plug is formed inside the trench. After the polishing step, the top surface of the insulation plug and the top surface of the mask layer are at the same surface. The mask layer is patterned to expose a portion of the sacrificial layer near the central region of two neighboring trenches. An ion implantation is carried out. The mask layer and the sacrificial layer are removed.
摘要翻译：一种用于形成STI结构的方法。在衬底上形成衬垫氧化物层。在衬垫氧化物层上形成牺牲层。在牺牲层上形成掩模层。对掩模层进行图案化，然后依次蚀刻牺牲层，焊盘氧化物层和衬底以形成沟槽。执行热氧化以沿着牺牲层的暴露的侧壁和沟槽内的暴露的衬底表面形成衬垫层。绝缘材料沉积在衬底上，完全填充沟槽。执行化学机械抛光步骤以去除绝缘层的一部分和掩模层的一部分，使得在沟槽内部形成绝缘插头。在抛光步骤之后，绝缘塞的顶表面和掩模层的顶表面处于相同的表面。对掩模层进行图案化以在两个相邻沟槽的中心区域附近露出牺牲层的一部分。进行离子注入。去除掩模层和牺牲层。

16. 发明授权

US06417036B1 Method of fabricating dynamic random access memories 失效
标题翻译：制作动态随机存取存储器的方法
公开(公告)号：US06417036B1
公开(公告)日：2002-07-09
申请号：US09627400
申请日：2000-07-27
申请人： Shu-Ya Chuang
发明人： Shu-Ya Chuang
IPC分类号： H01L2974
CPC分类号： H01L27/108 , G11C11/404
摘要： An improved method for fabricating DRAM with a thin film transistor can increase reading and writing speed. In this method, a substrate with a transfer transistor, a word line, a bit line and an interlayer dielectric layer is provided. A bit line contact and a terminal contact are formed in the interlayer dielectric layer. The bit line contact couples to the bit line and the terminal contact couples to the transfer transistor. The terminal contact is a T-shaped structure. An oxide layer is formed to cover the interlayer dielectric layer and the terminal contact to expose the bit line contact. A polysilicon layer is formed to cover the oxide layer and the bit line contact. An ion implantation step is performed to form a first doped region and a second doped region in the polysilicon layer. The polysilicon layer is patterned to make the first doped region into a source region and to make the second doped region into a drain region. The drain region is on one side of the terminal contact corresponding to the source region.
摘要翻译：用薄膜晶体管制造DRAM的改进方法可以提高读写速度。在该方法中，提供具有转移晶体管，字线，位线和层间电介质层的衬底。在层间电介质层中形成位线接触和端子接触。位线接触耦合到位线，并且端子触点耦合到转移晶体管。端子触点是T形结构。形成氧化物层以覆盖层间电介质层和端子触点以暴露位线接触。形成多晶硅层以覆盖氧化物层和位线接触。执行离子注入步骤以在多晶硅层中形成第一掺杂区域和第二掺杂区域。图案化多晶硅层以使第一掺杂区域成为源极区域并使第二掺杂区域成为漏极区域。漏极区域位于与源极区域对应的端子触点的一侧。

17. 发明授权

US06344415B1 Method for forming a shallow trench isolation structure 失效
标题翻译：形成浅沟槽隔离结构的方法
公开(公告)号：US06344415B1
公开(公告)日：2002-02-05
申请号：US09397161
申请日：1999-09-15
申请人： Shu-Ya Chuang , Aaron Lee
发明人： Shu-Ya Chuang , Aaron Lee
IPC分类号： H01L21302
CPC分类号： H01L21/76224
摘要： A method for forming a STI structure. A pad oxide layer is formed over a substrate. An amorphous silicon layer is formed over the pad oxide layer. A mask layer is formed over the amorphous silicon layer. The mask layer is patterned, and then the amorphous silicon layer, the pad oxide layer and the substrate are etched in sequence to form a trench. A thermal oxidation is performed to form a liner layer along the exposed sidewalls of the amorphous silicon layer and the exposed substrate surface inside the trench. Insulation material is deposited over the substrate, completely filling the trench. A chemical-mechanical polishing step is performed to remove a portion of the insulation layer and a portion of the mask layer so that an insulation plug is formed inside the trench. After the polishing step, the top surface of the insulation plug and the top surface of the mask layer are at the same surface. The mask layer is patterned to expose a portion of the amorphous silicon layer near the central region of two neighboring trenches. An ion implantation is carried out. The mask layer is removed. The amorphous silicon layer is removed.
摘要翻译：一种用于形成STI结构的方法。在衬底上形成衬垫氧化物层。在衬垫氧化物层上形成非晶硅层。在非晶硅层上形成掩模层。对掩模层进行构图，然后依次蚀刻非晶硅层，衬垫氧化物层和衬底以形成沟槽。执行热氧化以沿着非晶硅层的暴露的侧壁和沟槽内的暴露的衬底表面形成衬垫层。绝缘材料沉积在衬底上，完全填充沟槽。执行化学机械抛光步骤以去除绝缘层的一部分和掩模层的一部分，使得在沟槽内部形成绝缘插头。在抛光步骤之后，绝缘塞的顶表面和掩模层的顶表面处于相同的表面。将掩模层图案化以暴露出两个相邻沟槽的中心区域附近的非晶硅层的一部分。进行离子注入。去除掩模层。去除非晶硅层。

18. 发明授权

US6107159A Method for fabricating a shallow trench isolation structure 失效
标题翻译：浅沟槽隔离结构的制造方法
公开(公告)号：US6107159A
公开(公告)日：2000-08-22
申请号：US261094
申请日：1999-03-02
申请人： Shu-Ya Chuang
发明人： Shu-Ya Chuang
IPC分类号： H01L21/762 , H01L21/763 , H01L21/76
CPC分类号： H01L21/763 , H01L21/76229
摘要： A method for forming a STI structure is provided. The method contains sequenitially forming a pad oxide layer and a mask layer on a semiconductor substrate. Several trenches in the substrate through the mask layer and the pad oxide layer. The trenches has a wider trench and a narrower trench. A liner oxide layer is formed at each sidewall of the trenches in the substrate. A spacer is formed on each sidewall of the wider trench, in which the narrower trench simultaneously is filled with same insulating material. A conformal polysilicon layer is formed over the substrate, in which the wider trench is not completely filled yet. An insulating plug is formed to fill the wider trench. Using the insulating plug as an etching mask a portion of the polysilicon layer is removed by etching. As a result, a polysilicon pivot sidewall of the remaining polysilicon layer due to etching may occur. The polysilicon pivot sidewall is compensated with polysilicon. The mask layer and the pad oxide layer are removed, and a gate oxide layer is formed instead. During the formation of the gate oxide layer, a surface portion of the polysilicon layer is also oxidized so that the insulating plug and the spacer are merged through the oxidized portion of the polysilicon to form a round isolation structure.
摘要翻译：提供了一种用于形成STI结构的方法。该方法包括在半导体衬底上顺序地形成衬垫氧化物层和掩模层。通过掩模层和衬垫氧化物层在衬底中的几个沟槽。沟槽具有较宽的沟槽和较窄的沟槽。在衬底中的沟槽的每个侧壁处形成衬里氧化物层。在较宽沟槽的每个侧壁上形成间隔物，其中较窄的沟槽同时填充有相同的绝缘材料。在衬底上形成共形多晶硅层，其中较宽的沟槽尚未完全填充。形成绝缘插头以填充较宽的沟槽。使用绝缘插头作为蚀刻掩模，通过蚀刻去除多晶硅层的一部分。结果，可能发生由于蚀刻而导致剩余多晶硅层的多晶硅枢转侧壁。多晶硅枢轴侧壁由多晶硅补偿。除去掩模层和焊盘氧化物层，形成栅氧化层。在栅极氧化层的形成期间，多晶硅层的表面部分也被氧化，使得绝缘插塞和间隔物通过多晶硅的氧化部分合并形成圆形隔离结构。

19. 发明授权

US5998259A Method of fabricating dual cylindrical capacitor 失效
标题翻译：制造双圆柱电容器的方法
公开(公告)号：US5998259A
公开(公告)日：1999-12-07
申请号：US66196
申请日：1998-04-24
申请人： Shu-Ya Chuang
发明人： Shu-Ya Chuang
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817
摘要： A method of fabricating a dual cylindrical capacitor in a DRAM. A semiconductor substrate comprising a gate, a source/drain region, field oxide layer, a first oxide layer covering the whole semiconductor substrate, and a poly-via penetrating through the first oxide layer to electrically connect the source/drain region is provided. A first poly-silicon layer is formed on the first oxide layer and the poly-via. A silicon nitride layer is formed and patterned on the first poly-silicon layer and aligned with the poly-via. An oxide spacer is formed on a side wall of the silicon nitride layer, so that a part of the first poly-silicon layer is covered by the oxide spacer. A part of the first poly-silicon layer is removed with the oxide spacer and the silicon nitride layer as a mask until the first oxide layer is exposed. The silicon nitride layer is removed. A poly-silicon spacer is formed around the oxide spacer. The oxide spacer is removed, so that the remaining first poly-silicon layer and the poly-silicon spacer are combined as a bottom electrode. A dielectric layer is formed on a surface of the electrode. A top electrode is formed on the dielectric layer.
摘要翻译：一种在DRAM中制造双圆柱形电容器的方法。提供了包括栅极，源极/漏极区域，场氧化物层，覆盖整个半导体衬底的第一氧化物层和穿过第一氧化物层的多通孔以电连接源极/漏极区域的半导体衬底。在第一氧化物层和多通孔上形成第一多晶硅层。在第一多晶硅层上形成并图案化氮化硅层并与多通孔对准。在氮化硅层的侧壁上形成氧化物间隔物，使得第一多晶硅层的一部分被氧化物间隔物覆盖。用氧化物间隔物和氮化硅层作为掩模去除第一多晶硅层的一部分，直到暴露出第一氧化物层。去除氮化硅层。在氧化物间隔物周围形成多晶硅间隔物。去除氧化物间隔物，使得剩余的第一多晶硅层和多晶硅间隔物作为底部电极组合。在电极的表面上形成介电层。在电介质层上形成顶部电极。

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