专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明申请

US20090294798A1 Bipolar Device Compatible with CMOS Process Technology 有权
标题翻译：双极器件兼容CMOS工艺技术
公开(公告)号：US20090294798A1
公开(公告)日：2009-12-03
申请号：US12256376
申请日：2008-10-22
申请人： Shine Chung , Fu-Lung Hsueh
发明人： Shine Chung , Fu-Lung Hsueh
IPC分类号： H01L29/739
CPC分类号： H01L29/735 , H01L27/0207 , H01L27/0623 , H01L29/0692 , H01L29/1008
摘要： A bipolar device includes: an emitter of a first polarity type constructed on a semiconductor substrate; a collector of the first polarity type constructed on the semiconductor substrate; a gate pattern in a mesh configuration defining the emitter and the collector; an intrinsic base of a second polarity type underlying the gate pattern; and an extrinsic base constructed atop the gate pattern and coupled with the intrinsic base, for functioning together with the intrinsic base as a base of the bipolar device.
摘要翻译：双极器件包括：构造在半导体衬底上的第一极性类型的发射极; 在半导体衬底上构造的第一极性类型的集电极; 限定发射极和集电极的网格配置中的栅极图案; 位于栅极图案下方的第二极性类型的本征基极; 以及构造在栅极图案顶部并与本征基极耦合的外部基极，用于与作为双极器件的基极的本征基极一起工作。

12. 发明申请

US20090174487A1 VOLTAGE-CONTROL OSCILLATOR CIRCUITS WITH COMBINED MOS AND BIPOLAR DEVICE 有权
标题翻译：具有组合MOS和双极器件的电压控制振荡器电路
公开(公告)号：US20090174487A1
公开(公告)日：2009-07-09
申请号：US12237187
申请日：2008-09-24
申请人： Shine Chung , Fu-Lung Hsueh
发明人： Shine Chung , Fu-Lung Hsueh
IPC分类号： H03K3/00 , H03B5/02
CPC分类号： H03B5/1228 , H03B5/1203 , H03B5/1212 , H03B5/1215 , H03B5/1231 , H03B5/124
摘要： A voltage controlled oscillator includes: a first merged device having a first bipolar transistor and a first MOS transistor, the first bipolar transistor having a collector sharing a common active area with a source/drain of the first MOS transistor, and an emitter sharing the common active area with another source/drain of the first MOS transistor, a second merged device having a second bipolar transistor and a second MOS transistor, the second bipolar transistor having a collector sharing a common active area with a source/drain of the second MOS transistor, and an emitter sharing the common active area with another source/drain of the second MOS transistor, and a first inductor connected to both the collector of the first bipolar transistor and a base of the second bipolar transistor.
摘要翻译：压控振荡器包括：具有第一双极晶体管和第一MOS晶体管的第一合并器件，所述第一双极晶体管具有与第一MOS晶体管的源极/漏极共用公共有效面积的集电极，以及共享公共具有第一MOS晶体管的另一源/漏极的有源区，具有第二双极晶体管和第二MOS晶体管的第二合并器件，所述第二双极晶体管具有与第二MOS晶体管的源极/漏极共用共用有效面积的集电极以及与第二MOS晶体管的另一个源极/漏极共用公共有源区域的发射极，以及连接到第一双极晶体管的集电极和第二双极晶体管的基极的第一电感器。

13. 发明申请

US20080283963A1 Electrical Fuse Circuit for Security Applications 有权
标题翻译：用于安全应用的电保险电路
公开(公告)号：US20080283963A1
公开(公告)日：2008-11-20
申请号：US11748959
申请日：2007-05-15
申请人： Shine Chung , Fu-Lung Hsueh , Fu-Chieh Hsu
发明人： Shine Chung , Fu-Lung Hsueh , Fu-Chieh Hsu
IPC分类号： H01L23/62 , H01L29/00
CPC分类号： G11C17/18
摘要： A fuse circuit is disclosed, which comprises at least one electrical fuse element having a resistance that changes after being stressed in an electromigration mode, a switching device serially coupled with the electrical fuse element in a predetermined path between a fuse programming power supply (VDDQ) and a low voltage power supply (GND) for selectively allowing a programming current passing through the electrical fuse element during a programming operation, and at least one peripheral circuit coupled to the VDDQ, wherein the peripheral circuit is active and draws current from the VDDQ during a fuse programming operation.
摘要翻译：公开了一种熔丝电路，其包括至少一个电熔丝元件，该电熔丝元件具有在电迁移模式下受到应力之后变化的电阻;开关装置，其在熔丝编程电源（VDDQ）之间的预定路径中与电熔丝元件串联连接，以及用于在编程操作期间选择性地允许通过电熔丝元件的编程电流的低电压电源（GND），以及耦合到所述VDDQ的至少一个外围电路，其中所述外围电路是有效的并且在VDDQ期间从VDDQ引出电流保险丝编程操作。

14. 发明授权

US08305790B2 Electrical anti-fuse and related applications 有权
标题翻译：电抗保险丝及相关应用
公开(公告)号：US08305790B2
公开(公告)日：2012-11-06
申请号：US12724556
申请日：2010-03-16
申请人： Tao-Wen Chung , Po-Yao Ke , Shine Chung , Fu-Lung Hsueh
发明人： Tao-Wen Chung , Po-Yao Ke , Shine Chung , Fu-Lung Hsueh
IPC分类号： G11C17/00
CPC分类号： H01L23/5252 , G11C17/16 , H01L27/112 , H01L29/785 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A first terminal and a second terminal of a FinFET transistor are used as two terminals of an anti-fuse. To program the anti-fuse, a gate of the FinFET transistor is controlled, and a voltage having a predetermined amplitude and a predetermined duration is applied to the first terminal to cause the first terminal to be electrically shorted to the second terminal.
摘要翻译： FinFET晶体管的第一端子和第二端子用作反熔丝的两个端子。为了对反熔丝进行编程，控制FinFET晶体管的栅极，并且将具有预定幅度和预定持续时间的电压施加到第一端子，以使第一端子与第二端子电短路。

15. 发明授权

US07843747B2 System and method for better testability of OTP memory 有权
标题翻译： OTP内存的更好的可测试性的系统和方法
公开(公告)号：US07843747B2
公开(公告)日：2010-11-30
申请号：US12124989
申请日：2008-05-21
申请人： Fu-Lung Hsueh , Shine Chung , Wen-Kuan Fang , Po-Hung Chen
发明人： Fu-Lung Hsueh , Shine Chung , Wen-Kuan Fang , Po-Hung Chen
IPC分类号： G11C29/00
CPC分类号： G11C29/08 , G11C2216/26
摘要： A system for testing logic circuits for executing writing and reading operations in a one-time programmable (OTP) memory having an array of memory cells is disclosed, the system comprising a column of testing cells having the same number of cells as that of an entire column of the array of memory cells, a row of testing cells having the same number of cells as that of an entire row of the array of memory cells, wherein both the column and row of testing cells are first written to and then read out from during a testing operation, and can never be accessed during non-testing operations of the OTP memory.
摘要翻译：公开了一种用于测试在具有存储器单元阵列的一次可编程（OTP）存储器中执行写入和读取操作的逻辑电路的系统，该系统包括具有与整个存储器单元相同数量的单元格的测试单元列存储单元阵列的列，一行具有与存储器单元阵列的整行相同数量的单元的测试单元，其中测试单元的列和行首先被写入然后从在测试操作期间，并且在OTP存储器的非测试操作期间永远不能被访问。

16. 发明授权

US07821041B2 Electrical fuse circuit for security applications 有权
标题翻译：电熔丝电路用于安全应用
公开(公告)号：US07821041B2
公开(公告)日：2010-10-26
申请号：US11748959
申请日：2007-05-15
申请人： Shine Chung , Fu-Lung Hsueh , Fu-Chieh Hsu
发明人： Shine Chung , Fu-Lung Hsueh , Fu-Chieh Hsu
IPC分类号： H01L29/73
CPC分类号： G11C17/18
摘要： A fuse circuit is disclosed, which comprises at least one electrical fuse element having a resistance that changes after being stressed in an electromigration mode, a switching device serially coupled with the electrical fuse element in a predetermined path between a fuse programming power supply (VDDQ) and a low voltage power supply (GND) for selectively allowing a programming current passing through the electrical fuse element during a programming operation, and at least one peripheral circuit coupled to the VDDQ, wherein the peripheral circuit is active and draws current from the VDDQ during a fuse programming operation.
摘要翻译：公开了一种熔丝电路，其包括至少一个电熔丝元件，该电熔丝元件具有在电迁移模式下受到应力之后变化的电阻;开关装置，其在熔丝编程电源（VDDQ）之间的预定路径中与电熔丝元件串联连接，以及用于在编程操作期间选择性地允许通过电熔丝元件的编程电流的低电压电源（GND），以及耦合到所述VDDQ的至少一个外围电路，其中所述外围电路是有效的并且在VDDQ期间从VDDQ引出电流保险丝编程操作。

17. 发明申请

US20080012663A1 Waveguides in integrated circuits 有权
标题翻译：集成电路中的波导
公开(公告)号：US20080012663A1
公开(公告)日：2008-01-17
申请号：US11486903
申请日：2006-07-14
申请人： Shine Chung , Fu-Lung Hsueh
发明人： Shine Chung , Fu-Lung Hsueh
IPC分类号： H01P3/12
CPC分类号： H01P3/12 , H01L2924/0002 , H01L2924/00
摘要： A waveguide in semiconductor integrated circuit is disclosed, the waveguide comprises a horizontal first metal plate, a horizontal second metal plate above the first metal plate, separated by an insulation material, and a plurality of metal vias positioned in two parallel lines, running vertically through the insulation material in contacts with both the first and second metal plates, wherein the first and second metal plates and the plurality of metal vias form a metal enclosure in a cross-sectional view that can serve as a waveguide.
摘要翻译：公开了一种半导体集成电路中的波导，波导包括水平的第一金属板，在第一金属板上方的水平的第二金属板，由绝缘材料隔开，并且多个金属通孔位于两条平行的线上，垂直延伸穿过所述绝缘材料与所述第一和第二金属板两者接触，其中所述第一和第二金属板和所述多个金属通孔以横截面视图形成可用作波导的金属外壳。

18. 发明授权

US08703571B2 Methods of fabricating bipolar junction transistors having a fin 有权
标题翻译：制造具有翅片的双极结型晶体管的方法
公开(公告)号：US08703571B2
公开(公告)日：2014-04-22
申请号：US13535090
申请日：2012-06-27
申请人： Po-Yao Ke , Tao-Wen Chung , Shine Chung , Fu-Lung Hsueh
发明人： Po-Yao Ke , Tao-Wen Chung , Shine Chung , Fu-Lung Hsueh
IPC分类号： H01L21/331
CPC分类号： H01L29/73 , H01L21/823431
摘要： A method of forming a semiconductor device is provided. The method includes forming a first fin above a substrate, forming a first emitter region in a first portion of the first fin, forming a first collector region in a second portion of the first fin, and forming a first base region in a third portion of the first fin. The third portion of the first fin is disposed underneath a first gate electrode. The method further includes forming a second fin adjacent to the first fin and above the substrate. The second fin is composed of a semiconductor material. The method also includes forming a first base contact over the second fin. The first base contact is coupled to the first base region through the second fin, the substrate, and the first fin.
摘要翻译：提供一种形成半导体器件的方法。该方法包括在衬底上形成第一鳍片，在第一鳍片的第一部分中形成第一发射极区域，在第一鳍片的第二部分形成第一集电极区域，并在第三鳍片的第三部分形成第一基底区域第一个翅膀第一鳍片的第三部分设置在第一栅电极下方。该方法还包括形成邻近第一鳍片和衬底上方的第二鳍片。第二鳍由半导体材料构成。该方法还包括在第二翅片上形成第一基底接触。第一基底接触件通过第二鳍片，基底和第一鳍片耦合到第一基底区域。

19. 发明授权

US08619488B2 Multi-level electrical fuse using one programming device 有权
标题翻译：使用一个编程设备的多级电气保险丝
公开(公告)号：US08619488B2
公开(公告)日：2013-12-31
申请号：US13492635
申请日：2012-06-08
申请人： Yung-Lung Lin , Jui-Jen Wu , Shine Chung , Fu-Lung Hsueh
发明人： Yung-Lung Lin , Jui-Jen Wu , Shine Chung , Fu-Lung Hsueh
IPC分类号： G11C17/18 , G11C17/14 , G11C17/16 , G11C17/00
CPC分类号： G11C11/5692 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A method for programming a multi-level electrical fuse system comprises providing a fuse box with an electrical fuse and providing one of at least two fuse writing voltages to the electrical fuse to program the electrical fuse to one of at least two resistance states. The fuse box comprises at least one electrical fuse, a programming device serially coupled to the electrical fuse, and a variable power supply coupled to the fuse box and configured to generate two or more voltage levels.
摘要翻译：一种用于编程多电平电熔丝系统的方法包括：提供具有电熔丝的保险丝盒，并向所述电熔丝提供至少两个熔丝写入电压中的一个，以将所述电熔丝编程为至少两个电阻状态之一。保险丝盒包括至少一个电熔丝，串联耦合到电熔丝的编程装置，以及耦合到保险丝盒并配置成产生两个或多个电压电平的可变电源。

20. 发明授权

US08143644B2 Bipolar device compatible with CMOS process technology 有权
标题翻译：双极器件兼容CMOS工艺技术
公开(公告)号：US08143644B2
公开(公告)日：2012-03-27
申请号：US12256376
申请日：2008-10-22
申请人： Shine Chung , Fu-Lung Hsueh
发明人： Shine Chung , Fu-Lung Hsueh
IPC分类号： H01L29/739
CPC分类号： H01L29/735 , H01L27/0207 , H01L27/0623 , H01L29/0692 , H01L29/1008
摘要： A bipolar device includes: an emitter of a first polarity type constructed on a semiconductor substrate; a collector of the first polarity type constructed on the semiconductor substrate; a gate pattern in a mesh configuration defining the emitter and the collector; an intrinsic base of a second polarity type underlying the gate pattern; and an extrinsic base constructed atop the gate pattern and coupled with the intrinsic base, for functioning together with the intrinsic base as a base of the bipolar device.
摘要翻译：双极器件包括：构造在半导体衬底上的第一极性类型的发射极; 在半导体衬底上构造的第一极性类型的集电极; 限定发射极和集电极的网格配置中的栅极图案; 位于栅极图案下方的第二极性类型的本征基极; 以及构造在栅极图案顶部并与本征基极耦合的外部基极，用于与作为双极器件的基极的本征基极一起工作。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式