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11. 发明授权

US06972239B1 Low temperature MOCVD processes for fabrication of PrXCa1-xMnO3 thin films 有权
标题翻译：用于制造PrXCa1-xMnO3薄膜的低温MOCVD工艺
公开(公告)号：US06972239B1
公开(公告)日：2005-12-06
申请号：US10923529
申请日：2004-08-20
申请人： Tingkai Li , Wei-Wei Zhuang , Lawrence J. Charneski , David R. Evans , Sheng Teng Hsu
发明人： Tingkai Li , Wei-Wei Zhuang , Lawrence J. Charneski , David R. Evans , Sheng Teng Hsu
IPC分类号： C23C16/40 , H01L21/20 , H01L45/00
CPC分类号： H01L45/1616 , C23C16/40 , H01L45/04 , H01L45/1233 , H01L45/147
摘要： A method of fabricating a PCMO thin film at low temperature for use in a RRAM device includes preparing a PCMO precursor; preparing a substrate; placing the substrate into a MOCVD chamber; introducing the PCMO precursor into the MOCVD chamber to deposit a PCMO thin film on the substrate; maintaining a MOCVD vaporizer at between about 240° C. to 280° C. and maintaining the MOCVD chamber at a temperature of between about 300° C. to 400° C.; removing the PCMO thin-film bearing substrate from the MOCVD chamber; and completing the RRAM device.
摘要翻译：在低温下制造用于RRAM器件的PCMO薄膜的方法包括制备PCMO前体; 制备底物; 将基板放置在MOCVD室中; 将PCMO前体引入MOCVD室以在衬底上沉积PCMO薄膜; 将MOCVD蒸发器保持在约240℃至280℃之间并将MOCVD室保持在约300℃至400℃之间的温度下; 从MOCVD室中取出PCMO薄膜轴承衬底; 并完成RRAM设备。

12. 发明授权

US06849467B1 MOCVD of TiO2 thin film for use as FeRAM H2 passivation layer 失效
标题翻译：用于FeRAM H2钝化层的TiO2薄膜的MOCVD
公开(公告)号：US06849467B1
公开(公告)日：2005-02-01
申请号：US10621863
申请日：2003-07-16
申请人： Tingkai Li , Wei Pan , Robert A. Barrowcliff , David R. Evans , Sheng Teng Hsu
发明人： Tingkai Li , Wei Pan , Robert A. Barrowcliff , David R. Evans , Sheng Teng Hsu
IPC分类号： H01L21/00 , H01L21/02 , H01L21/28 , H01L21/316 , H01L21/336 , H01L21/8242 , H01L21/8246 , H01L27/115
CPC分类号： H01L27/11502 , H01L21/28291 , H01L21/31604 , H01L27/11585 , H01L27/1159 , H01L28/57 , H01L29/6684
摘要： A method of forming an H2 passivation layer in an FeRAM includes preparing a silicon substrate; depositing a layer of TiOx thin film, where 0
摘要翻译：在FeRAM中形成H 2钝化层的方法包括制备硅衬底; 在大马士革结构上沉积一层TiOx薄膜，其中0

13. 发明授权

US06303502B1 MOCVD metal oxide for one transistor memory 失效
标题翻译： MOCVD金属氧化物用于一个晶体管存储器
公开(公告)号：US06303502B1
公开(公告)日：2001-10-16
申请号：US09588940
申请日：2000-06-06
申请人： Sheng Teng Hsu , David R. Evans , Tingkai Li , Jer-shen Maa , Wei-Wei Zhuang
发明人： Sheng Teng Hsu , David R. Evans , Tingkai Li , Jer-shen Maa , Wei-Wei Zhuang
IPC分类号： H01L2144
CPC分类号： H01L21/28291 , H01L29/78391
摘要： A method of fabricating a one-transistor memory includes, on a single crystal silicon substrate, depositing a bottom electrode structure on a gate oxide layer; implanting ions to form a source region and a drain region and activating the implanted ions spin coating the structure with a first ferroelectric layer; depositing a second ferroelectric layer; and annealing the structure to provide a c-axis ferroelectric orientation.
摘要翻译：制造单晶体管存储器的方法包括在单晶硅衬底上，在栅氧化层上沉积底电极结构; 注入离子以形成源极区域和漏极区域并激活注入的离子旋转涂覆第一铁电层的结构; 沉积第二铁电层; 并退火该结构以提供c轴铁电取向。

14. 发明申请

US20090032817A1 Back-To-Back Metal/Semiconductor/Metal (MSM) Schottky Diode 有权
标题翻译：背对背金属/半导体/金属（MSM）肖特基二极管
公开(公告)号：US20090032817A1
公开(公告)日：2009-02-05
申请号：US12234663
申请日：2008-09-21
申请人： Tingkai Li , Sheng Teng Hsu , David R. Evans
发明人： Tingkai Li , Sheng Teng Hsu , David R. Evans
IPC分类号： H01L29/04 , H01L21/329
CPC分类号： H01L27/101 , G11C13/0007 , G11C2213/31 , H01L27/2409 , H01L29/66143 , H01L29/872 , H01L45/04 , H01L45/1233 , H01L45/147
摘要： A method is provided for forming a metal/semiconductor/metal (MSM) back-to-back Schottky diode from a silicon (Si) semiconductor. The method deposits a Si semiconductor layer between a bottom electrode and a top electrode, and forms a MSM diode having a threshold voltage, breakdown voltage, and on/off current ratio. The method is able to modify the threshold voltage, breakdown voltage, and on/off current ratio of the MSM diode in response to controlling the Si semiconductor layer thickness. Generally, both the threshold and breakdown voltage are increased in response to increasing the Si thickness. With respect to the on/off current ratio, there is an optimal thickness. The method is able to form an amorphous Si (a-Si) and polycrystalline Si (polySi) semiconductor layer using either chemical vapor deposition (CVD) or DC sputtering. The Si semiconductor can be doped with a Group V donor material, which decreases the threshold voltage and increases the breakdown voltage.
摘要翻译：提供了用于从硅（Si）半导体形成金属/半导体/金属（MSM）背对背肖特基二极管的方法。该方法在底电极和顶电极之间沉积Si半导体层，并形成具有阈值电压，击穿电压和开/关电流比的MSM二极管。响应于控制Si半导体层厚度，该方法能够修改MSM二极管的阈值电压，击穿电压和导通/截止电流比。通常，响应于Si厚度的增加，阈值和击穿电压都增加。关于开/关电流比，存在最佳厚度。该方法能够使用化学气相沉积（CVD）或DC溅射形成非晶Si（a-Si）和多晶硅（polySi）半导体层。 Si半导体可以掺杂有V族施主材料，其降低阈值电压并增加击穿电压。

15. 发明授权

US07364665B2 Selective etching processes of SiO2 , Ti and In2 O3 thin films for FeRAM device applications 失效
标题翻译：用于FeRAM器件应用的SiO2，Ti和In2 O3薄膜的选择性蚀刻工艺
公开(公告)号：US07364665B2
公开(公告)日：2008-04-29
申请号：US10970885
申请日：2004-10-21
申请人： Tingkai Li , Bruce D. Ulrich , David R. Evans , Sheng Teng Hsu
发明人： Tingkai Li , Bruce D. Ulrich , David R. Evans , Sheng Teng Hsu
IPC分类号： B44C1/22 , C03C15/00 , C03C25/68 , C23F1/00
CPC分类号： H01L29/6684 , C23F4/00 , H01L21/28291 , H01L21/31116 , H01L21/32136
摘要： A method of selectively etching a three-layer structure consisting of SiO2, In2O3, and titanium, includes etching the SiO2, stopping at the titanium layer, using C3F8 in a range of between about 10 sccm to 30 sccm; argon in a range of between about 20 sccm to 40 sccm, using an RF source in a range of between about 1000 watts to 3000 watts and an RF bias in a range of between about 400 watts to 800 watts at a pressure in a range of between about 2 mtorr to 6 mtorr; and etching the titanium, stopping at the In2O3 layer, using BCl in a range of between about 10 sccm to 50 sccm; chlorine in a range of between about 40 sccm to 80 sccm, a Tcp in a range of between about 200 watts to 500 watts at an RF bias in a range of between about 100 watts to 200 watts at a pressure in a range of between about 4 mtorr to 8 mtorr.
摘要翻译：选择性地蚀刻由SiO 2，In 2 O 3 N 3和Ti构成的三层结构的方法包括蚀刻SiO _{2 ，在钛层上停止，使用C 3 3 F 8 N在约10sccm至30sccm之间; 在约20sccm至40sccm的范围内的氩气，使用在约1000瓦特至3000瓦特之间的范围内的RF源和在约400瓦特至800瓦特范围内的RF偏压，约2mtorr至6mtorr; 并且使用在约10sccm至50sccm之间的范围内的BCl蚀刻钛，停止在In 2 N 3 O 3层处; 在约40sccm至80sccm的范围内的氯，在约200瓦特至200瓦特之间的RF偏压下在约200瓦特至500瓦特之间的范围内的T cp < 在约4mtorr至8mtorr的范围内的压力。}

16. 发明授权

US06939724B2 Method for obtaining reversible resistance switches on a PCMO thin film when integrated with a highly crystallized seed layer 有权
公开(公告)号：US06939724B2
公开(公告)日：2005-09-06
申请号：US10640770
申请日：2003-08-13
申请人： Wei-Wei Zhuang , Tingkai Li , David R. Evans , Sheng Teng Hsu , Wei Pan
发明人： Wei-Wei Zhuang , Tingkai Li , David R. Evans , Sheng Teng Hsu , Wei Pan
IPC分类号： H01L27/04 , H01L21/20 , H01L21/822 , H01L45/00 , H01L21/00
CPC分类号： G11C13/0007 , G11C2213/31 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1608
摘要： A method for obtaining reversible resistance switches on a PCMO thin film when integrated with a highly crystallized seed layer includes depositing, by MOCVD, a seed layer of PCMO, in highly crystalline form, thin film, having a thickness of between about 50 Å to 300 Å, depositing a second PCMO thin film layer on the seed layer, by spin coating, having a thickness of between about 500 Å to 3000 Å, to form a combined PCMO layer; increasing the resistance of the combined PCMO film in a semiconductor device by applying a negative electric pulse of between about −4V to −5V, having a pulse width of between about 75 nsec to 1 μsec; and decreasing the resistance of the combined PCMO layer in a semiconductor device by applying a positive electric pulse of between about +2.5V to +4V, having a pulse width greater than 2.0 μsec.

17. 发明授权

US06927074B2 Asymmetric memory cell 有权
标题翻译：不对称记忆单元
公开(公告)号：US06927074B2
公开(公告)日：2005-08-09
申请号：US10442627
申请日：2003-05-21
申请人： Sheng Teng Hsu , Tingkai Li , David R. Evans
发明人： Sheng Teng Hsu , Tingkai Li , David R. Evans
IPC分类号： H01L27/10 , G11C11/15 , G11C13/00 , H01L21/8246 , H01L27/105 , H01L43/08 , H01L21/00
CPC分类号： G11C13/0007 , B82Y10/00 , G11C11/15 , G11C2213/31 , G11C2213/52 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/147
摘要： An asymmetric memory cell and method for forming an asymmetric memory cell are provided. The method comprises: forming a bottom electrode having a first area; forming an electrical pulse various resistance (EPVR) material overlying the bottom electrode; forming a top electrode overlying the EPVR layer having a second area, less than the first area. In some aspects the second area is at least 20% smaller than the first area. The EPVR is a material such as colossal magnetoresistance (CMR), high temperature super conducting (HTSC), or perovskite metal oxide materials. The method further comprises: inducing an electric field between the electrodes; inducing current flow through the EPVR adjacent the top electrode; and, in response to inducing current flow through the EPVR adjacent the top electrode, modifying the resistance of the EPVR. Typically, the resistance is modified within the range of 100 ohms to 10 mega-ohms.
摘要翻译：提供了一种用于形成非对称存储单元的非对称存储单元和方法。该方法包括：形成具有第一区域的底部电极; 形成覆盖底部电极的各种电阻（EPVR）材料的电脉冲; 形成覆盖在EPVR层上的顶部电极，其具有小于第一区域的第二区域。在一些方面，第二区域比第一区域小至少20％。 EPVR是诸如巨磁阻（CMR），高温超导（HTSC）或钙钛矿金属氧化物材料的材料。该方法还包括：在电极之间引入电场; 通过邻近顶部电极的EPVR引起电流流动; 并且响应于通过与顶部电极相邻的EPVR的电流流动，修改EPVR的电阻。通常，电阻在100欧姆到10兆欧姆的范围内被修改。

18. 发明授权

US07407858B2 Resistance random access memory devices and method of fabrication 有权
标题翻译：电阻随机存取存储器件及其制造方法
公开(公告)号：US07407858B2
公开(公告)日：2008-08-05
申请号：US11403020
申请日：2006-04-11
申请人： Tingkai Li , Sheng Teng Hsu , David R. Evans
发明人： Tingkai Li , Sheng Teng Hsu , David R. Evans
IPC分类号： H01L21/336 , H01L31/072
CPC分类号： H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1616 , H01L45/1641
摘要： A method of fabricating a RRAM includes preparing a substrate and forming a bottom electrode ori the substrate. A PCMO layer is deposited on the bottom electrode using MOCVD or liquid MOCVD, followed by a post-annealing process. The deposited PCMO thin film has a crystallized PCMO structure or a nano-size and amorphous PCMO structure. A top electrode is formed on the PCMO layer.
摘要翻译：制造RRAM的方法包括制备衬底并形成底部电极或衬底。使用MOCVD或液体MOCVD将PCMO层沉积在底部电极上，随后进行后退火处理。沉积的PCMO薄膜具有结晶的PCMO结构或纳米尺寸和无定形PCMO结构。顶部电极形成在PCMO层上。

19. 发明授权

US07235407B2 System and method for forming a bipolar switching PCMO film 有权
标题翻译：用于形成双极开关PCMO膜的系统和方法
公开(公告)号：US07235407B2
公开(公告)日：2007-06-26
申请号：US10855942
申请日：2004-05-27
申请人： Tingkai Li , Lawrence J. Charneski , Wei-Wei Zhuang , David R. Evans , Sheng Teng Hsu
发明人： Tingkai Li , Lawrence J. Charneski , Wei-Wei Zhuang , David R. Evans , Sheng Teng Hsu
IPC分类号： H01L21/00
CPC分类号： H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1616
摘要： A multi-layer PrxCa1-xMnO3 (PCMO) thin film capacitor and associated deposition method are provided for forming a bipolar switching thin film. The method comprises: forming a bottom electrode; depositing a nanocrystalline PCMO layer; depositing a polycrystalline PCMO layer; forming a multi-layer PCMO film with bipolar switching properties; and, forming top electrode overlying the PCMO film. If the polycrystalline layers are deposited overlying the nanocrystalline layers, a high resistance can be written with narrow pulse width, negative voltage pulses. The PCMO film can be reset to a low resistance using a narrow pulse width, positive amplitude pulse. Likewise, if the nanocrystalline layers are deposited overlying the polycrystalline layers, a high resistance can be written with narrow pulse width, positive voltage pulses, and reset to a low resistance using a narrow pulse width, negative amplitude pulse.
摘要翻译：提供了多层Pr 1 x 1 x x MnO 3（PCMO）薄膜电容器和相关的沉积方法，用于形成双极开关薄膜。该方法包括：形成底部电极; 沉积纳米晶体PCMO层; 沉积多晶的PCMO层; 形成具有双极开关特性的多层PCMO膜; 并且形成覆盖PCMO膜的顶部电极。如果多晶层沉积在纳米晶层之上，则可以用窄脉冲宽度，负电压脉冲写入高电阻。 PCMO膜可以使用窄脉冲宽度，正幅度脉冲复位为低电阻。同样，如果纳米晶层沉积在多晶层上，则可以用窄脉冲宽度，正电压脉冲写入高电阻，并使用窄脉冲宽度，负幅度脉冲将其复位为低电阻。

20. 发明授权

US07214583B2 Memory cell with an asymmetric crystalline structure 有权
标题翻译：具有不对称晶体结构的记忆单元
公开(公告)号：US07214583B2
公开(公告)日：2007-05-08
申请号：US11130983
申请日：2005-05-16
申请人： Sheng Teng Hsu , Tingkai Li , David R. Evans , Wei-Wei Zhuang , Wei Pan
发明人： Sheng Teng Hsu , Tingkai Li , David R. Evans , Wei-Wei Zhuang , Wei Pan
IPC分类号： H01L21/8242
CPC分类号： G11C13/0007 , G11C2213/31 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1608 , H01L45/1625
摘要： Asymmetrically structured memory cells and a fabrication method are provided. The method comprises: forming a bottom electrode; forming an electrical pulse various resistance (EPVR) first layer having a polycrystalline structure over the bottom electrode; forming an EPVR second layer adjacent the first layer, with a nano-crystalline or amorphous structure; and, forming a top electrode overlying the first and second EPVR layers. EPVR materials include CMR, high temperature super conductor (HTSC), or perovskite metal oxide materials. In one aspect, the EPVR first layer is deposited with a metalorganic spin coat (MOD) process at a temperature in the range between 550 and 700 degrees C. The EPVR second layer is formed at a temperature less than, or equal to the deposition temperature of the first layer. After a step of removing solvents, the MOD deposited EPVR second layer is formed at a temperature less than, or equal to the 550 degrees C.
摘要翻译：提供了非对称结构的存储单元和制造方法。该方法包括：形成底部电极; 在底部电极上形成具有多晶结构的电脉冲各种电阻（EPVR）第一层; 用纳米结晶或无定形结构形成邻近第一层的EPVR第二层; 并且形成覆盖在第一和第二EPVR层上的顶部电极。 EPVR材料包括CMR，高温超导体（HTSC）或钙钛矿金属氧化物材料。在一个方面，EPVR第一层在550-700℃的温度范围内用金属有机旋涂（MOD）工艺沉积.EPVR第二层是在小于或等于沉积温度的第一层。在除去溶剂的步骤之后，将MOD沉积的EPVR第二层在小于或等于550℃的温度下形成。

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