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11. 发明授权

US08521969B2 Apparatus and method for directing micro architectural memory region accesses 有权
标题翻译：用于指导微架构存储器区域访问的装置和方法
公开(公告)号：US08521969B2
公开(公告)日：2013-08-27
申请号：US11546710
申请日：2006-10-11
申请人： Martin G. Dixon , Scott D. Rodgers , James P. Held , Bill Alexander , Larry O. Smith , Scott H. Robinson , Sham M. Datta
发明人： Martin G. Dixon , Scott D. Rodgers , James P. Held , Bill Alexander , Larry O. Smith , Scott H. Robinson , Sham M. Datta
IPC分类号： G06F12/00
CPC分类号： G06F21/79 , G06F12/1441 , G06F2221/2141
摘要： In an embodiment, memory access requests for information stored within a system memory pass through an integrated circuit. The system memory may include a micro-architectural memory region to store instructions and/or data, where the micro-architectural memory region is to be exclusively accessible by a micro-architectural agent The integrated circuit may include memory access director to direct memory access requests to the micro-architectural memory region if the memory access director determines that the memory access request includes a location within the at least one micro-architectural memory region and the micro-architectural agent is operating in a micro-architectural memory region access mode.
摘要翻译：在一个实施例中，存储在系统存储器内的信息的存储器访问请求通过集成电路。系统存储器可以包括用于存储指令和/或数据的微架构存储器区域，其中微架构存储器区域将被微架构代理程序唯一地访问。集成电路可以包括存储器访问控制器以引导存储器访问请求如果存储器访问指导者确定存储器访问请求包括至少一个微架构存储器区域内的位置，并且微架构代理程序在微架构存储器区域访问模式下操作，则向微架构存储器区域发送。

12. 发明授权

US06775728B2 Method and system for concurrent handler execution in an SMI and PMI-based dispatch-execution framework 有权
标题翻译：在SMI和基于PMI的调度执行框架中执行并发处理程序的方法和系统
公开(公告)号：US06775728B2
公开(公告)日：2004-08-10
申请号：US10011233
申请日：2001-11-15
申请人： Vincent J. Zimmer , Sham M. Datta
发明人： Vincent J. Zimmer , Sham M. Datta
IPC分类号： G06F1324
CPC分类号： G06F9/4812
摘要： A method and system that enables concurrent event handler execution in a system management interrupt (SMI) and processor management interrupt (PMI)-based dispatch-execution framework to service an SMI or PMI event. A plurality of event handlers are loaded into a hidden memory space that is accessible to a hidden execution mode supported by each of a plurality of processors in a multiprocessor computer system but is not accessible to other operating modes of those processors. The event handlers are then dispatched to two or more processors in response to the hidden execution mode event and concurrently executed to service the event. Various embodiments include use of a single event handler to service the event, multiple event handlers that perform different tasks, and multiple event handler instances that concurrently perform a single task. The invention also provides a resource locking mechanism to prevent resource access conflicts.
摘要翻译：一种在系统管理中断（SMI）和基于处理器管理中断（PMI）的调度执行框架中执行并发事件处理程序的服务SMI或PMI事件的方法和系统。多个事件处理程序被加载到可由多处理器计算机系统中的多个处理器中的每一个支持的隐藏执行模式可访问的隐藏存储器空间中，但是对于这些处理器的其它操作模式是不可访问的。然后响应于隐藏的执行模式事件将事件处理程序分派到两个或多个处理器，并且并发执行以对该事件进行服务。各种实施例包括使用单个事件处理程序来服务事件，执行不同任务的多个事件处理程序以及同时执行单个任务的多个事件处理程序实例。本发明还提供了一种防止资源访问冲突的资源锁定机制。

13. 发明授权

US06754828B1 Algorithm for non-volatile memory updates 有权
标题翻译：用于非易失性存储器更新的算法
公开(公告)号：US06754828B1
公开(公告)日：2004-06-22
申请号：US09352715
申请日：1999-07-13
申请人： Suresh Marisetty , Andrew J. Fish , Yan Li , Mani Ayyar , Amy O'Donnell , George Thangadurai , Sham M. Datta
发明人： Suresh Marisetty , Andrew J. Fish , Yan Li , Mani Ayyar , Amy O'Donnell , George Thangadurai , Sham M. Datta
IPC分类号： G06F942
CPC分类号： G06F8/65
摘要： A novel processor architecture and algorithms are provided which improve non-volatile memory updates and increases processor performance in successive generations of processors. A new processor architecture is supported by a software model consisting of two new firmware layers and the legacy 32 bit basic input output system (BIOS) firmware. The new firmware layers consist of a Processor Abstraction Layer (PAL) and a System Abstraction Layer (SAL). The PAL and SAL have procedure calls which allow updates of the firmware components in the non-volatile memory of a system, e.g. non-volatile ROM. The present invention includes invoking a system abstraction layer update procedure to implement a new input binary into the non-volatile memory. An algorithm for the non-volatile memory includes selecting a lead processor to perform an update and using the system abstraction layer update procedure. The system abstraction layer update procedure is used to call an appropriate authentication routine. The system abstraction layer update procedure is used to call a specific non-volatile memory implementation routine.
摘要翻译：提供了一种新颖的处理器架构和算法，其改进了非易失性存储器更新并且在连续几代处理器中提高了处理器性能。由两个新固件层和传统32位基本输入输出系统（BIOS）固件组成的软件模型支持新的处理器架构。新的固件层由处理器抽象层（PAL）和系统抽象层（SAL）组成。 PAL和SAL具有允许更新系统的非易失性存储器中的固件组件的过程调用，例如，非易失性ROM。本发明包括调用系统抽象层更新过程以将新的输入二进制文件实现到非易失性存储器中。用于非易失性存储器的算法包括选择引导处理器来执行更新并使用系统抽象层更新过程。系统抽象层更新过程用于调用适当的认证例程。系统抽象层更新过程用于调用特定的非易失性存储器实现例程。

14. 发明授权

US07254676B2 Processor cache memory as RAM for execution of boot code 有权
标题翻译：处理器缓存内存作为执行启动代码的RAM
公开(公告)号：US07254676B2
公开(公告)日：2007-08-07
申请号：US10295406
申请日：2002-11-15
申请人： Sham M. Datta , Vincent J. Zimmer , Kushagra V. Vaid , William A. Stevens , Amy Lynn Santoni
发明人： Sham M. Datta , Vincent J. Zimmer , Kushagra V. Vaid , William A. Stevens , Amy Lynn Santoni
IPC分类号： G06F12/00
CPC分类号： G06F12/126 , G06F9/4403 , G06F12/0862 , G06F2212/2515
摘要： In one embodiment, a computer boot method allows choosing a predetermined data block alignment for a cache that has multiple cross processor interactions. A cache RAM column of a cache as RAM system is loaded with a tag to prevent unintended cache line evictions, and boot code is executed, with the preloaded cache RAM appearing to the executing boot code stream as a memory store.
摘要翻译：在一个实施例中，计算机引导方法允许为具有多个交叉处理器交互的高速缓存选择预定数据块对齐。作为RAM系统的缓存的高速缓存RAM列被加载有标签以防止意外的高速缓存行驱逐，并且执行引导代码，其中预先加载的高速缓存RAM作为存储器存储器显示在执行的引导代码流中。

15. 发明授权

US5671422A Method and apparatus for switching between the modes of a processor 失效
标题翻译：用于在处理器的模式之间切换的方法和装置
公开(公告)号：US5671422A
公开(公告)日：1997-09-23
申请号：US411450
申请日：1995-03-28
申请人： Sham M. Datta
发明人： Sham M. Datta
IPC分类号： G06F9/32 , G06F9/48 , G06F9/00
CPC分类号： G06F9/4812
摘要： A method for switching between a first mode and a second mode of a processor is provided. According to one embodiment of the invention, a computer system includes the processor coupled to a storage device storing a number of instructions. In response to a first interrupt, a first information is stored in the storage device for switching to processing in the first mode starting at a first of the number of instructions. In response to a second interrupt occurring subsequent to the storing of the first information, said processor switches from processing in the first mode to processing in the second mode. Also in response to the second interrupt, a second information is storm in the storage device for returning to processing in the first mode starting at a second of the number of instructions. In response to said processor switching from said first mode to said second mode, said processor switches from processing in the second mode to processing in the first mode starting at the first instruction using the first information if processing starting at the first instruction is required.
摘要翻译：提供了一种用于在处理器的第一模式和第二模式之间切换的方法。根据本发明的一个实施例，计算机系统包括耦合到存储多个指令的存储设备的处理器。响应于第一中断，第一信息被存储在存储设备中，用于在第一模式中的第一个指令开始处切换到处理。响应于在存储第一信息之后发生的第二中断，所述处理器从第一模式的处理切换到第二模式的处理。此外，响应于第二中断，第二信息在存储设备中暴风雨，以在指令数量的第二位置从第一模式返回到处理。响应于所述处理器从所述第一模式切换到所述第二模式，如果需要从第一指令开始的处理，则所述处理器从第二模式的处理切换到从第一指令开始的处理，使用第一信息。

16. 发明授权

US08423682B2 Address space emulation 有权
标题翻译：地址空间仿真
公开(公告)号：US08423682B2
公开(公告)日：2013-04-16
申请号：US11323465
申请日：2005-12-30
申请人： Sham M. Datta , Robert Greiner , Frank Binns , Keshavan Tiruvallur , Rajesh Parthasarathy , Madhavan Parthasarathy
发明人： Sham M. Datta , Robert Greiner , Frank Binns , Keshavan Tiruvallur , Rajesh Parthasarathy , Madhavan Parthasarathy
IPC分类号： G06F3/00 , G06F12/00 , G06F9/26 , G06F9/34
CPC分类号： G06F9/342 , G06F9/30174 , G06F12/0292 , G06F12/063 , G06F2212/206
摘要： Apparatus and systems, as well as methods and articles, may operate to detect an input/output access operation associated with a configuration memory address and a first memory address bit size. The configuration memory address and associated configuration data may be combined into a packet having a second memory address bit size (e.g., 64 bits) greater than the first memory address bit size (e.g., 32 bits). The packet may be used to establish compatibility for legacy operating systems that attempt to communicate with peripheral component interconnect (PCI) interface-based peripherals, and similar platform devices, that have been integrated into the same package as the processor.
摘要翻译：装置和系统以及方法和物品可以操作以检测与配置存储器地址和第一存储器地址位大小相关联的输入/输出访问操作。配置存储器地址和相关联的配置数据可以被组合成具有大于第一存储器地址位大小（例如，32位）的第二存储器地址位大小（例如，64位）的分组。该分组可以用于为尝试与外围组件互连（PCI）接口的外围设备以及已经集成到与处理器相同的封装中的类似的平台设备进行通信的传统操作系统建立兼容性。

17. 发明授权

US07392371B2 Method and apparatus for using a volume top file to boot firmware modules 有权
标题翻译：使用卷顶文件引导固件模块的方法和装置
公开(公告)号：US07392371B2
公开(公告)日：2008-06-24
申请号：US10032141
申请日：2001-12-20
申请人： Vincent J. Zimmer , Kirk D. Brannock , Sham M. Datta
发明人： Vincent J. Zimmer , Kirk D. Brannock , Sham M. Datta
IPC分类号： G06F9/00
CPC分类号： G06F9/4401
摘要： A boot routine is initialized in a computer by bootstrapping a volume top file (VTF) located in a first addressable location accessible upon the initializing of the boot routine and the volume top file bootstrapping a set of firmware modules.
摘要翻译：引导例程在计算机中通过引导位于第一可寻址位置的卷顶部文件（VTF）来初始化，该第一可寻址位置可以在初始化引导例程和卷顶部文件引导一组固件模块时访问。

18. 发明申请

US20080091917A1 Apparatus and method for directing micro architectural memory region accesses 有权
标题翻译：用于指导微架构存储器区域访问的装置和方法
公开(公告)号：US20080091917A1
公开(公告)日：2008-04-17
申请号：US11546710
申请日：2006-10-11
申请人： Martin G. Dixon , Scott D. Rodgers , James P. Held , Bill Alexander , Larry O. Smith , Scott H. Robinson , Sham M. Datta
发明人： Martin G. Dixon , Scott D. Rodgers , James P. Held , Bill Alexander , Larry O. Smith , Scott H. Robinson , Sham M. Datta
IPC分类号： G06F15/76
CPC分类号： G06F21/79 , G06F12/1441 , G06F2221/2141
摘要： In an embodiment, memory access requests for information stored within a system memory pass through an integrated circuit. The system memory may include a micro-architectural memory region to store instructions and/or data, where the micro-architectural memory region is to be exclusively accessible by a micro-architectural agent The integrated circuit may include memory access director to direct memory access requests to the micro-architectural memory region if the memory access director determines that the memory access request includes a location within the at least one micro-architectural memory region and the micro-architectural agent is operating in a micro-architectural memory region access mode.
摘要翻译：在一个实施例中，存储在系统存储器内的信息的存储器访问请求通过集成电路。系统存储器可以包括用于存储指令和/或数据的微架构存储器区域，其中微架构存储器区域将被微架构代理程序唯一地访问。集成电路可以包括存储器访问控制器以引导存储器访问请求如果存储器访问指导者确定存储器访问请求包括至少一个微架构存储器区域内的位置，并且微架构代理程序在微架构存储器区域访问模式下操作，则向微架构存储器区域发送。

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