专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明申请

US20110051535A1 Fin-Type Device System and Method 有权
标题翻译：翅片式设备系统及方法
公开(公告)号：US20110051535A1
公开(公告)日：2011-03-03
申请号：US12552359
申请日：2009-09-02
申请人： Seung-Chul Song , Mohamed Hassan Abu-Rahma , Beom-Mo Han
发明人： Seung-Chul Song , Mohamed Hassan Abu-Rahma , Beom-Mo Han
IPC分类号： G11C7/00 , H01L21/336 , H01L29/78
CPC分类号： H01L29/785 , G11C11/40 , H01L27/108 , H01L27/10802 , H01L27/10826 , H01L27/10879 , H01L29/66795 , H01L29/7831 , H01L29/7841 , H01L29/7855 , H01L29/78648
摘要： A fin-type device system and method is disclosed. In a particular embodiment, a method of fabricating a transistor is disclosed and includes forming a gate of a transistor within a substrate having a surface and forming a buried oxide (BOX) layer within the substrate and adjacent to the gate at a first BOX layer face. The method also includes forming a raised source-drain channel (“fin”), where at least a portion of the fin extends from the surface of the substrate, and where the fin has a first fin face adjacent a second BOX layer face of the BOX layer.
摘要翻译：公开了一种翅片式装置系统和方法。在特定实施例中，公开了制造晶体管的方法，包括在具有表面的衬底内形成晶体管的栅极，并在衬底内形成掩埋氧化物（BOX）层，并在第一BOX层面。该方法还包括形成凸起的源极 - 漏极通道（“鳍”），其中鳍的至少一部分从衬底的表面延伸，并且其中鳍具有邻近第二BOX层的第一鳍面 BOX层。

12. 发明申请

US20100109086A1 Method of Fabricating A Fin Field Effect Transistor (FinFET) Device 有权
标题翻译：制造Fin场效应晶体管（FinFET）器件的方法
公开(公告)号：US20100109086A1
公开(公告)日：2010-05-06
申请号：US12266183
申请日：2008-11-06
申请人： Seung-Chul Song , Mohamed Hassan Abu-Rahma , Beom-Mo Han
发明人： Seung-Chul Song , Mohamed Hassan Abu-Rahma , Beom-Mo Han
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66795 , H01L29/785
摘要： A method of fabricating a semiconductor using a fin field effect transistor (FINFET) is disclosed. In a particular embodiment, a method includes depositing, on a silicon substrate, a first dummy structure having a first sidewall and a second sidewall separated by a first width. The method also includes depositing, on the silicon substrate, a second dummy structure concurrently with depositing the first dummy structure. The second dummy structure has a third sidewall and a fourth sidewall that are separated by a second width. The second width is substantially greater than the first width. The first dummy structure is used to form a first pair of fins separated by approximately the first width. The second dummy structure is used to form a second pair of fins separated by approximately the second width.
摘要翻译：公开了一种使用鳍状场效应晶体管（FINFET）制造半导体的方法。在特定实施例中，一种方法包括在硅衬底上沉积具有第一侧壁和第二侧壁的第一虚拟结构，所述第一侧壁和第二侧壁被第一宽度分开。该方法还包括在沉积第一虚拟结构的同时在硅衬底上沉积第二虚拟结构。第二虚拟结构具有分隔第二宽度的第三侧壁和第四侧壁。第二宽度基本上大于第一宽度。第一虚拟结构用于形成以大约第一宽度分开的第一对散热片。第二虚拟结构用于形成分开大约第二宽度的第二对散热片。

13. 发明授权

US07026662B2 Semiconductor device having a photon absorption layer to prevent plasma damage 有权
标题翻译：具有光子吸收层以防止等离子体损伤的半导体器件
公开(公告)号：US07026662B2
公开(公告)日：2006-04-11
申请号：US10740570
申请日：2003-12-22
申请人： Seung-Chul Song
发明人： Seung-Chul Song
IPC分类号： H01L33/00
CPC分类号： H01L21/31612 , H01L21/02107 , H01L21/02274 , H01L21/02304 , H01L21/76825 , H01L21/76829 , H01L21/76832
摘要： A MOSFET device structure and a method of manufacturing the same, in which a photon absorption layer is formed over a gate structure and a substrate in order to avoid plasma induced damage to the gate oxide during high density plasma deposition of a interlayer dielectric layer. The device structure may include an etch stop layer below the photon absorption layer. The photon absorption layer is formed entirely of silicon germanium or it may be a multi-layer formed of a silicon layer and a silicon germanium layer. In the multi-layer structure the silicon germanium layer may be formed on top of the silicon layer or vice-versa. The silicon germanium layer may be formed by implanting germanium ions into a silicon layer or by an epitaxial growth of the silicon germanium alloy layer. In the photon absorption layer the germanium may be substituted by another element whose band gap energy is less than that of silicon.
摘要翻译： MOSFET器件结构及其制造方法，其中在栅极结构和衬底上形成光子吸收层，以便在层间电介质层的高密度等离子体沉积期间避免等离子体对栅极氧化物的损伤。器件结构可以包括在光子吸收层下面的蚀刻停止层。光子吸收层完全由硅锗形成，或者它可以是由硅层和硅锗层形成的多层。在多层结构中，硅锗层可以形成在硅层的顶部上，反之亦然。硅锗层可以通过将锗离子注入到硅层中或者通过硅锗合金层的外延生长来形成。在光子吸收层中，锗可以被带隙能量小于硅的另一元素取代。

14. 发明授权

US09875788B2 Low-power 5T SRAM with improved stability and reduced bitcell size 有权
公开(公告)号：US09875788B2
公开(公告)日：2018-01-23
申请号：US12731668
申请日：2010-03-25
申请人： Seong-Ook Jung , Hyunkook Park , Seung-Chul Song , Mohamed Hassan Abu-Rahma , Lixin Ge , Zhongze Wang , Beom-Mo Han
发明人： Seong-Ook Jung , Hyunkook Park , Seung-Chul Song , Mohamed Hassan Abu-Rahma , Lixin Ge , Zhongze Wang , Beom-Mo Han
IPC分类号： G11C11/412
CPC分类号： G11C11/412
摘要： A 5 Transistor Static Random Access Memory (5T SRAM) is designed for reduced cell size and immunity to process variation. The 5T SRAM includes a storage element for storing data, wherein the storage element is coupled to a first voltage and a ground voltage. The storage element can include symmetrically sized cross-coupled inverters. A single access transistor controls read and write operations on the storage element. Control logic is configured to generate a value of the first voltage a write operation that is different from the value of the first voltage for a read operation.

15. 发明申请

US20120256270A1 DUAL METAL GATES USING ONE METAL TO ALTER WORK FUNCTION OF ANOTHER METAL 审中-公开
标题翻译：使用一种金属的双金属门可以改善其他金属的工作功能
公开(公告)号：US20120256270A1
公开(公告)日：2012-10-11
申请号：US13525840
申请日：2012-06-18
申请人： Byoung H. Lee , Sang Ho Bae , Kisik Choi , Rino Choi , Craig Huffman , Prashant Majhi , Jong Hoan Sim , Seung-Chul Song , Zhibo Zhang
发明人： Byoung H. Lee , Sang Ho Bae , Kisik Choi , Rino Choi , Craig Huffman , Prashant Majhi , Jong Hoan Sim , Seung-Chul Song , Zhibo Zhang
IPC分类号： H01L27/092
CPC分类号： H01L21/823842 , H01L21/28088 , H01L29/4966 , H01L29/517
摘要： Methods of forming dual metal gates and the gates so formed are disclosed. A method may include forming a first metal (e.g., NMOS metal) layer on a gate dielectric layer and a second metal (e.g., PMOS metal) layer on the first metal layer, whereby the second metal layer alters a work function of the first metal layer (to form PMOS metal). The method may remove a portion of the second metal layer to expose the first metal layer in a first region; form a silicon layer on the exposed first metal layer in the first region and on the second metal layer in a second region; and form the dual metal gates in the first and second regions. Since the gate dielectric layer is continuously covered with the first metal, it is not exposed to the damage from the metal etch process.
摘要翻译：公开了形成双金属栅极和形成的栅极的方法。一种方法可以包括在第一金属层上的栅极电介质层和第二金属（例如，PMOS金属）层上形成第一金属（例如，NMOS金属）层，由此第二金属层改变第一金属的功函数层（形成PMOS金属）。该方法可以移除第二金属层的一部分以暴露第一区域中的第一金属层; 在第一区域中的暴露的第一金属层上和在第二区域中的第二金属层上形成硅层; 并在第一和第二区域形成双金属栅极。由于栅极电介质层被第一金属连续覆盖，所以不会受到金属蚀刻工艺的损害。

16. 发明申请

US20110235406A1 Low-Power 5T SRAM with Improved Stability and Reduced Bitcell Size 有权
标题翻译：低功耗5T SRAM，具有改进的稳定性和降低位单元大小
公开(公告)号：US20110235406A1
公开(公告)日：2011-09-29
申请号：US12731668
申请日：2010-03-25
申请人： Seong-Ook Jung , Hyunkook Park , Seung-Chul Song , Mohamed Hassan Abu-Rahma , Lixin Ge , Zhongze Wang , Beom-Mo Han
发明人： Seong-Ook Jung , Hyunkook Park , Seung-Chul Song , Mohamed Hassan Abu-Rahma , Lixin Ge , Zhongze Wang , Beom-Mo Han
IPC分类号： G11C11/00 , G11C8/08 , G11C7/00
CPC分类号： G11C11/412
摘要： A 5 Transistor Static Random Access Memory (5T SRAM) is designed for reduced cell size and immunity to process variation. The 5T SRAM includes a storage element for storing data, wherein the storage element is coupled to a first voltage and a ground voltage. The storage element can include symmetrically sized cross-coupled inverters. A single access transistor controls read and write operations on the storage element. Control logic is configured to generate a value of the first voltage a write operation that is different from the value of the first voltage for a read operation.
摘要翻译： 5晶体管静态随机存取存储器（5T SRAM）设计用于减小电池尺寸和对工艺变化的抗扰性。 5T SRAM包括用于存储数据的存储元件，其中存储元件耦合到第一电压和接地电压。存储元件可以包括对称尺寸的交叉耦合的反相器。单个存取晶体管控制对存储元件的读取和写入操作。控制逻辑被配置为产生与读取操作的第一电压的值不同的写入操作的第一电压的值。

17. 发明申请

US20100324850A1 Static Noise Margin Estimation 有权
标题翻译：静态噪声容限估计
公开(公告)号：US20100324850A1
公开(公告)日：2010-12-23
申请号：US12485969
申请日：2009-06-17
申请人： Seong-Ook Jung , Seung-Chul Song , Hyunkook Park
发明人： Seong-Ook Jung , Seung-Chul Song , Hyunkook Park
IPC分类号： G01R29/26 , G06F17/18
CPC分类号： G11C11/412 , G11C11/41 , G11C29/50 , G11C2029/5002
摘要： In a particular embodiment, a method is disclosed that estimates a total static noise margin of a bit cell of a memory. The method includes determining a correlation coefficient of a left static noise margin of the bit cell as compared to a right static noise margin of the bit cell and estimating a total static noise margin of the bit cell by evaluating an analytical function based on the correlation coefficient.
摘要翻译：在特定实施例中，公开了一种估计存储器的位单元的总静态噪声容限的方法。该方法包括：确定比特单元的左静态噪声容限的相关系数，与位单元的右静态噪声容限相比，并通过基于相关系数评估分析函数来估计位单元的总静态噪声容限。

18. 发明申请

US20100308408A1 Apparatus and Method to Fabricate an Electronic Device 有权
标题翻译：制造电子设备的装置和方法
公开(公告)号：US20100308408A1
公开(公告)日：2010-12-09
申请号：US12477412
申请日：2009-06-03
申请人： Seung-Chul Song , Beom-Mo Han , Mohamed Hassan Abu-Rahma
发明人： Seung-Chul Song , Beom-Mo Han , Mohamed Hassan Abu-Rahma
IPC分类号： H01L27/088 , H01L21/027 , B32B3/00
CPC分类号： H01L21/823431 , B82Y10/00 , B82Y40/00 , G03F7/0002 , H01L21/32139 , H01L29/66795 , H01L29/785 , Y10T29/41 , Y10T428/24479
摘要： An apparatus and method to fabricate an electronic device is disclosed. In a particular embodiment, an apparatus includes a template having an imprint surface. The imprint surface includes a first region having a first pattern adapted to fabricate a fin field effect transistor (FinFET) device and a second region having a second pattern adapted to fabricate a planar electronic device.
摘要翻译：公开了一种制造电子设备的装置和方法。在特定实施例中，装置包括具有压印表面的模板。压印表面包括具有适于制造鳍状场效应晶体管（FinFET）器件的第一图案的第一区域和具有适于制造平面电子器件的第二图案的第二区域。

19. 发明授权

US08803253B2 Replacement metal gate process for CMOS integrated circuits 有权
标题翻译： CMOS集成电路的替代金属栅极工艺
公开(公告)号：US08803253B2
公开(公告)日：2014-08-12
申请号：US13609621
申请日：2012-09-11
申请人： Hiroaki Niimi , Seung-Chul Song
发明人： Hiroaki Niimi , Seung-Chul Song
IPC分类号： H01L29/78 , H01L27/092
CPC分类号： H01L21/823857 , H01L21/823814 , H01L21/823828 , H01L21/823842 , H01L27/092 , H01L27/0922 , H01L27/0928
摘要： A complementary metal-oxide-semiconductor (CMOS) integrated circuit structure, and method of fabricating the same according to a replacement metal gate process. P-channel and n-channel MOS transistors are formed with high-k gate dielectric material that differ from one another in composition or thickness, and with interface dielectric material that differ from one another in composition or thickness. The described replacement gate process enables construction so that neither of the p-channel or n-channel transistor gate structures includes the metal gate material from the other transistor, thus facilitating reliable filling of the gate structures with fill metal.
摘要翻译：互补金属氧化物半导体（CMOS）集成电路结构及其替代金属栅极工艺的制造方法。 P沟道和n沟道MOS晶体管由组成或厚度彼此不同的高k栅介质材料形成，并且在组成或厚度上彼此不同的界面电介质材料形成。所描述的替代栅极处理使得能够构造，使得p沟道或n沟道晶体管栅极结构都不包括来自另一个晶体管的金属栅极材料，从而有助于用填充金属可靠地填充栅极结构。

20. 发明授权

US08691644B2 Method of forming a CMOS device with a stressed-channel NMOS transistor and a strained-channel PMOS transistor 有权
标题翻译：用应力通道NMOS晶体管和应变通道PMOS晶体管形成CMOS器件的方法
公开(公告)号：US08691644B2
公开(公告)日：2014-04-08
申请号：US13541957
申请日：2012-07-05
申请人： Seung-Chul Song , Amitabh Jain , Deborah J. Riley
发明人： Seung-Chul Song , Amitabh Jain , Deborah J. Riley
IPC分类号： H01L21/8238 , H01L21/336 , H01L21/3205 , H01L21/4763 , H01L21/8234
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823857 , H01L27/092 , H01L29/6653 , H01L29/6656 , H01L29/66636 , H01L29/7833 , H01L29/7834 , H01L29/7847 , H01L29/7848
摘要： A method of forming stressed-channel NMOS transistors and strained-channel PMOS transistors forms p-type source and drain regions before an n-type source and drain dopant is implanted and a stress memorization layer is formed, thereby reducing the stress imparted to the n-channel of the PMOS transistors. In addition, a non-conductive layer is formed after the p-type source and drain regions are formed, but before the n-type dopant is implanted. The non-conductive layer allows shallower n-type implants to be realized, and also serves as a buffer layer for the stress memorization layer.
摘要翻译：形成应力通道NMOS晶体管和应变通道PMOS晶体管的方法在植入n型源极和漏极掺杂剂之前形成p型源极和漏极区，并且形成应力记忆层，由此减小施加到n - 沟道的PMOS晶体管。此外，在形成p型源极和漏极区之后，但在植入n型掺杂剂之前，形成非导电层。不导电层允许实现较浅的n型植入物，并且还用作应力记忆层的缓冲层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式