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11. 发明授权

US06468914B1 Method of forming gate electrode in semiconductor device 失效
标题翻译：在半导体器件中形成栅电极的方法
公开(公告)号：US06468914B1
公开(公告)日：2002-10-22
申请号：US09472541
申请日：1999-12-27
申请人： Se Aug Jang , In Seok Yeo
发明人： Se Aug Jang , In Seok Yeo
IPC分类号： H01L2144
CPC分类号： H01L29/6656 , H01L21/28061 , H01L21/28247 , H01L29/6659
摘要： A method of forming a gate electrode in a semiconductor device which can prevent abnormal oxidation of a titanium silicide layer when performing gate re-oxidation process after a gate electrode having a stacked structure of a doped polysilicon layer and the titanium silicide layer.
摘要翻译：一种在半导体器件中形成栅电极的方法，其可以在具有掺杂多晶硅层和硅化钛层的堆叠结构的栅极之后执行栅极再氧化处理时防止硅化钛层的异常氧化。

12. 发明授权

US06255206B1 Method of forming gate electrode with titanium polycide structure 有权
标题翻译：用聚硅氧烷结构形成栅电极的方法
公开(公告)号：US06255206B1
公开(公告)日：2001-07-03
申请号：US09434647
申请日：1999-11-05
申请人： Se Aug Jang , Tae Kyun Kim , In Seok Yeo , Sahng Kyoo Lee
发明人： Se Aug Jang , Tae Kyun Kim , In Seok Yeo , Sahng Kyoo Lee
IPC分类号： H01L213205
CPC分类号： H01L21/28061 , H01L21/31683
摘要： A method of forming a gate electrode with a titanium polycide structure which can prevent abnormal oxidation of the gate electrode and reduce the resistivity of the gate electrode when performing a re-oxidation process, is disclosed. According to the present invention, a gate oxide layer, a polysilicon layer and a titanium silicide layer are formed on a semiconductor substrate, in sequence. A mask insulating layer is then formed in the shape of a gate electrode on the titanium silicide layer and the titanium silicide layer and the polysilicon layer are etched using the mask insulating layer to form a gate electrode. Thereafter, the substrate is oxidized using re-oxidation process to form an oxide layer with a uniform thickness on the side wall of the gate electrode and on the surface of the substrate. Here, the re-oxidation process is performed at the temperature of 750° C. or less using dry oxidation. Furthermore, the re-oxidation process is performed at the temperature of 700 to 750° C. and the oxide layer is formed to the thickness of 30 to 60 Å, preferably, about 50 Å.
摘要翻译：公开了一种形成具有可以防止栅电极的异常氧化并降低栅电极的电阻率的多晶硅化钛结构的栅电极的方法。根据本发明，栅极氧化物层在半导体衬底上依次形成多晶硅层和硅化钛层。然后在硅化钛层上形成栅极形状的掩模绝缘层，并且使用掩模绝缘层蚀刻钛硅化物层和多晶硅层以形成栅电极。此后，使用再氧化工艺氧化基板，在栅电极的侧壁和基板的表面上形成均匀厚度的氧化物层。这里，使用干式氧化在750℃以下的温度下进行再氧化处理。此外，再次氧化处理在700-750℃的温度下进行，氧化物层的厚度形成为30至60埃，优选为约50埃。

13. 发明授权

US6153481A Method for forming an isolation insulating film for internal elements of a semiconductor device 失效
标题翻译：用于形成用于半导体器件的内部元件的隔离绝缘膜的方法
公开(公告)号：US6153481A
公开(公告)日：2000-11-28
申请号：US71163
申请日：1998-05-04
申请人： Se Aug Jang , Byung Jin Cho , Chan Lim
发明人： Se Aug Jang , Byung Jin Cho , Chan Lim
IPC分类号： H01L21/316 , H01L21/76 , H01L21/762 , H01L21/336
CPC分类号： H01L21/76202
摘要： There is provided a method for forming element isolation insulating film of a semiconductor device by employing PBL method for reducing the bird's beak and increasing the length of the effective active region. The method comprising the steps of forming a pad-oxide film, a stack-silicon film, and a nitride film on a semiconductor substrate in sequence; forming an element isolation region by selectively patterning the nitride film with an etching process by using an element isolation mask; and forming an element isolation film by field-oxidizing the element isolation region over the semiconductor substrate.
摘要翻译：提供了一种用于通过使用PBL方法来减少鸟嘴并增加有效活性区域的长度来形成半导体器件的元件隔离绝缘膜的方法。该方法包括以下步骤：依次在半导体衬底上形成衬垫氧化膜，叠层硅膜和氮化膜; 通过使用元件隔离掩模通过蚀刻工艺选择性地图案化氮化物膜来形成元件隔离区域; 以及通过在所述半导体衬底上对所述元件隔离区进行场氧化来形成元件隔离膜。

14. 发明授权

US6107144A Method for forming field oxide of semiconductor device and the semiconductor device 失效
标题翻译：用于形成半导体器件的场氧化物的方法和半导体器件
公开(公告)号：US6107144A
公开(公告)日：2000-08-22
申请号：US70911
申请日：1998-05-04
申请人： Se Aug Jang , Young Bog Kim , In Seok Yeo , Jong Choul Kim
发明人： Se Aug Jang , Young Bog Kim , In Seok Yeo , Jong Choul Kim
IPC分类号： H01L21/316 , H01L21/76 , H01L21/762 , H01L21/336
CPC分类号： H01L21/76202
摘要： A method for forming a field oxide of a semiconductor device and the semiconductor device. In order to form the field oxide, first, an element isolation mask is constructed on a semiconductor substrate. Then, a nitride spacer is formed at the side wall of the mask. At this time, a nitrogen-containing polymer is produced on the field region. The exposed region of the semiconductor substrate is oxidized at a temperature of 1,050-1,200.degree. C. to grow a recess-oxide while transforming the nitrogen-containing polymer into a nitride. Thereafter, the recess oxide is removed, together with the nitride, to create a trench in which the field oxide is formed through thermal oxidation. Therefore, the method can prevent an FOU phenomenon upon the growth of a field oxide and improve the field oxide thinning effect, thereby bringing a significant improvement to the production yield and the reliability of a semiconductor device.
摘要翻译：一种用于形成半导体器件的场氧化物和半导体器件的方法。为了形成场氧化物，首先，在半导体衬底上构造元件隔离掩模。然后，在掩模的侧壁上形成氮化物间隔物。此时，在场区域产生含氮聚合物。半导体衬底的暴露区域在1050〜1200℃的温度下被氧化，生长凹陷氧化物，同时将含氮聚合物转化为氮化物。此后，与氮化物一起去除凹陷氧化物，以产生通过热氧化形成场氧化物的沟槽。因此，该方法可以防止场氧化物生长时的FOU现象，提高场氧化物稀化效果，从而显着提高半导体器件的制造成品率和可靠性。

15. 发明授权

US06933226B2 Method of forming a metal gate in a semiconductor device 失效
标题翻译：在半导体器件中形成金属栅极的方法
公开(公告)号：US06933226B2
公开(公告)日：2005-08-23
申请号：US09994284
申请日：2001-11-26
申请人： Sang Ick Lee , Hyung Hwan Kim , Se Aug Jang
发明人： Sang Ick Lee , Hyung Hwan Kim , Se Aug Jang
IPC分类号： H01L29/43 , H01L21/336 , H01L21/338 , H01L29/423 , H01L29/49 , H01L29/78 , H01L21/4763
CPC分类号： H01L29/66545 , H01L29/495
摘要： A method of forming a gate in a semiconductor device includes forming a dummy gate insulating layer on a semiconductor substrate having a field oxide layer isolating the device, depositing a dummy gate polysilicon layer and a hard mask layer on the dummy gate insulating layer sequentially, patterning the hard mask layer into a mask pattern and patterning the dummy gate polysilicon layer using the mask pattern as an etch barrier, forming spacers at both sidewalls of the dummy gate polysilicon layer, depositing an insulating interlayer on the resultant structure after forming the spacers, exposing a surface of the dummy gate polysilicon layer by carrying out an oxide layer CMP process having a high selection ratio against the dummy gate polysilicon layer, forming a damascene structure by removing the dummy gate polysilicon layer and the dummy gate insulating layer using the insulating interlayer as another etch barrier, depositing a gate insulating layer and a gate metal layer on the entire surface of the semiconductor substrate having the damascene structure, and exposing a surface of the insulating interlayer by carrying out a metal CMP process having a high selection ratio against the insulating interlayer.
摘要翻译：在半导体器件中形成栅极的方法包括：在具有隔离器件的场氧化物层的半导体衬底上形成虚拟栅极绝缘层，在虚拟栅极绝缘层上依次沉积伪栅极多晶硅层和硬掩模层，硬掩模层成为掩模图案，并且使用掩模图案作为蚀刻阻挡层图案化虚拟栅极多晶硅层，在伪栅极多晶硅层的两个侧壁处形成间隔物，在形成间隔物之后在所得结构上沉积绝缘中间层，暴露通过对虚拟栅极多晶硅层执行具有高选择比的氧化物层CMP工艺，通过使用绝缘中间层去除伪栅极多晶硅层和伪栅极绝缘层来形成镶嵌结构来形成伪栅极多晶硅层的表面，另一蚀刻屏障，在栅极上沉积栅极绝缘层和栅极金属层具有镶嵌结构的半导体基板的表面，并且通过对绝缘中间层进行具有高选择率的金属CMP工艺，使绝缘中间层的表面露出。

16. 发明授权

US06284635B1 Method for forming titanium polycide gate 失效
标题翻译：形成多晶硅化钛门的方法
公开(公告)号：US06284635B1
公开(公告)日：2001-09-04
申请号：US09471596
申请日：1999-12-23
申请人： Se Aug Jang
发明人： Se Aug Jang
IPC分类号： H01L213205
CPC分类号： H01L21/28061
摘要： A method for forming a titanium polycide gate, comprising the steps of: forming a gate oxide and a doped polysilicon layer over the semiconductor substrate, in turn; implanting impurity ions into the doped polysilicon layer to form an amorphous phase silicon layer in the surface of the polysilicon layer; forming an amorphous phase titanium silicide layer over the amorphous phase silicon layer; carrying out heat-treatment to transform the amorphous phase titanium silicide layer into a crystalline phase titanium silicide layer and to transform the amorphous phase silicon layer into the crystalline silicon layer; and patterning the crystalline phase titanium silicide layer, the polysilicon layer including the crystalline phase silicon layer and the gate oxide to form the titanium polycide gate.
摘要翻译：一种形成多晶硅化钛栅极的方法，包括以下步骤：依次在半导体衬底上形成栅极氧化物和掺杂多晶硅层; 将杂质离子注入到掺杂多晶硅层中以在多晶硅层的表面中形成非晶相硅层; 在所述非晶相硅层上形成非晶相钛硅化物层; 进行热处理以将非晶相钛硅化物层转变为结晶相硅化钛层，并将非晶相硅层转化为晶体硅层; 以及图案化所述结晶相硅化钛层，所述多晶硅层包括所述结晶相硅层和所述栅极氧化物以形成所述多晶硅化钛栅极。

17. 发明授权

US06255173B1 Method of forming gate electrode with titanium polycide structure 有权
标题翻译：用聚硅氧烷结构形成栅电极的方法
公开(公告)号：US06255173B1
公开(公告)日：2001-07-03
申请号：US09466741
申请日：1999-12-17
申请人： Se Aug Jang
发明人： Se Aug Jang
IPC分类号： H01L218236
CPC分类号： H01L29/6659 , H01L21/28247
摘要： A method of forming a gate electrode with a titanium polycide structure capable of preventing abnormal oxidation of the gate electrode when performing gate re-oxidation process, is disclosed. In the present invention, after forming a gate electrode having a stacked structure of a polysilicon layer and a titanium silicide layer, thermal-treating is performed under nitrogen atmosphere to form a TiN layer on the side wall of the titanium silicide layer, considering as silicon content of the titanium silicide layer is high, abnormal oxidation decreases. At this time, a titanium silicide layer having deficient Ti is formed on the side wall of the titanium silicide layer adjacent to the TiN layer. Therefore, after removing the TiN layer, the side wall of the titanium silicide layer having excessive Si (or deficient Ti) is exposed. Thereafter, gate re-oxidation process is performed. At this time, abnormal oxidation of the titanium silicide layer is prevented by the titanium silicide layer having excessive silicon.
摘要翻译：公开了一种在进行栅极再氧化处理时形成具有能够防止栅电极异常氧化的多晶硅化钛结构的栅电极的方法。在本发明中，在形成具有多晶硅层和硅化钛层的堆叠结构的栅电极之后，在氮气气氛下进行热处理，在硅化钛层的侧壁上形成TiN层，考虑为硅硅化钛层的含量高，异常氧化降低。此时，在与TiN层相邻的硅化钛层的侧壁上形成有Ti不足的硅化钛层。因此，在除去TiN层后，露出具有过量Si（或Ti不足）的硅化钛层的侧壁。此后，进行栅极再氧化处理。此时，通过具有过量硅的硅化钛层来防止硅化钛层的异常氧化。

18. 发明授权

US5856230A Method for making field oxide of semiconductor device 失效
标题翻译：制造半导体器件的场氧化物的方法
公开(公告)号：US5856230A
公开(公告)日：1999-01-05
申请号：US963589
申请日：1997-11-04
申请人： Se Aug Jang
发明人： Se Aug Jang
IPC分类号： H01L21/76 , H01L21/762
CPC分类号： H01L29/7843 , H01L21/76202 , Y10S438/928 , Y10S438/938
摘要： There is disclosed a method for making a field oxide, by which wafer warpage is minimized when a local oxidation of silicon process is applied for a large wafer. A material layer having a compressive stress and a nitride are laminated over the back side of a wafer, so that the compressive stress of the material layer complementarily interacts with the tensile stress of the nitride.
摘要翻译：公开了一种制造场氧化物的方法，当将硅工艺的局部氧化应用于大晶片时，晶片翘曲最小化。具有压缩应力的材料层和氮化物层叠在晶片的背面上，使得材料层的压缩应力与氮化物的拉伸应力互补地相互作用。

19. 发明授权

US08058141B2 Recessed gate electrode MOS transistor and method for fabricating the same 有权
标题翻译：嵌入式栅电极MOS晶体管及其制造方法
公开(公告)号：US08058141B2
公开(公告)日：2011-11-15
申请号：US12861111
申请日：2010-08-23
申请人： Jun Ki Kim , Soo Hyun Kim , Hyun Chul Sohn , Se Aug Jang
发明人： Jun Ki Kim , Soo Hyun Kim , Hyun Chul Sohn , Se Aug Jang
IPC分类号： H01L21/76
CPC分类号： H01L29/66795 , H01L27/10876 , H01L27/10879 , H01L29/7853
摘要： Disclosed are a transistor and a method for fabricating the same capable of increasing a threshold voltage and a driving current of the transistor. The method includes the steps of forming a first etch mask on a silicon substrate, forming a trench by etching the exposed isolation area, forming a first insulation layer in the trench and the first etch mask, forming a second insulation layer on the first insulation layer, removing the second insulation layer and the first insulation layer until the first etch mask is exposed, forming a trench type isolation layer on the isolation area, forming a second etch mask on an entire surface of the silicon substrate, etching the exposed channel area, performing an etching process with respect to a resultant substrate structure, and forming a gate in the recess.
摘要翻译：公开了一种晶体管及其制造方法，其能够增加晶体管的阈值电压和驱动电流。该方法包括以下步骤：在硅衬底上形成第一蚀刻掩模，通过蚀刻暴露的隔离区域形成沟槽，在沟槽中形成第一绝缘层和第一蚀刻掩模，在第一绝缘层上形成第二绝缘层去除所述第二绝缘层和所述第一绝缘层直到所述第一蚀刻掩模被暴露，在所述隔离区域上形成沟槽型隔离层，在所述硅衬底的整个表面上形成第二蚀刻掩模，蚀刻所述暴露的沟道区域，对所得基板结构进行蚀刻处理，以及在所述凹部中形成栅极。

20. 发明授权

US07332755B2 Transistor structure of memory device and method for fabricating the same 有权
标题翻译：存储器件的晶体管结构及其制造方法
公开(公告)号：US07332755B2
公开(公告)日：2008-02-19
申请号：US11201951
申请日：2005-08-10
申请人： Se Aug Jang , Yong Soo Kim , Jae Geun Oh , Jae Sung Roh , Hyun Chun Sohn
发明人： Se Aug Jang , Yong Soo Kim , Jae Geun Oh , Jae Sung Roh , Hyun Chun Sohn
IPC分类号： H01L29/72
CPC分类号： H01L27/10876 , H01L27/10823 , H01L27/10826 , H01L27/10873 , H01L27/10879 , H01L29/66621 , H01L29/66795 , H01L29/7851
摘要： A memory device includes an active area protruding from a semiconductor substrate. A recess is formed in the active area. A field oxide layer is formed on the semiconductor substrate. A gate electrode extends across the active area while being overlapped with the recess. A gate insulation layer is interposed between the gate electrode and the active area. Source and drain areas are formed in the active area. The transistor structure above defines a recessed transistor structure if it is sectioned along a source-drain line and defines a Fin transistor structure if it is sectioned along a gate line. The transistor structure ensures sufficient data retention time and improves the current drivability while lowering the back bias dependency of a threshold voltage.
摘要翻译：存储器件包括从半导体衬底突出的有源区。在活动区域中形成凹部。在半导体衬底上形成场氧化物层。栅极电极延伸穿过有源区域同时与凹部重叠。栅极绝缘层介于栅电极和有源区之间。源极和漏极区域形成在有源区域中。如果上述晶体管结构沿着源极 - 漏极线分段而限定了凹陷的晶体管结构，并且如果沿着栅极线分段则限定了Fin晶体管结构。晶体管结构确保足够的数据保持时间，并且在降低阈值电压的反偏压依赖性的同时提高电流驱动能力。

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