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    • 12. 发明申请
    • OPENING HARD MASK AND SOI SUBSTRATE IN SINGLE PROCESS CHAMBER
    • 在单个过程室中打开硬掩模和SOI衬底
    • US20070173067A1
    • 2007-07-26
    • US11275707
    • 2006-01-25
    • Scott AllenKangguo ChengXi LiKevin Winstel
    • Scott AllenKangguo ChengXi LiKevin Winstel
    • H01L21/302
    • H01L21/3081H01L21/31116
    • Methods for opening a hard mask and a silicon-on-insulator substrate in a single process chamber are disclosed. In one embodiment, the method includes patterning a photoresist over a stack including an anti-reflective coating (ARC) layer, a silicon dioxide (SiO2) based hard mask layer, a silicon nitride pad layer, a silicon dioxide (SiO2) pad layer and the SOI substrate, wherein the SOI substrate includes a silicon-on-insulator layer and a buried silicon dioxide (SiO2) layer; and in a single process chamber: opening the ARC layer; etching the silicon dioxide (SiO2) based hard mask layer; etching the silicon nitride pad layer; etching the silicon dioxide (SiO2) pad layer; and etching the SOI substrate. Etching all layers in a single chamber reduces the turn-around-time, lowers the process cost, facilitates process control and/or improve a trench profile.
    • 公开了在单个处理室中打开硬掩模和绝缘体上硅衬底的方法。 在一个实施例中,该方法包括在包括抗反射涂层(ARC)层,基于二氧化硅(SiO 2)的硬掩模层,氮化硅垫层, 二氧化硅(SiO 2)衬垫层和SOI衬底,其中所述SOI衬底包括绝缘体上硅层和掩埋二氧化硅(SiO 2)层; 并在单个处理室中:打开ARC层; 蚀刻基于二氧化硅(SiO 2)的硬掩模层; 蚀刻氮化硅焊盘层; 蚀刻二氧化硅(SiO 2)垫层; 并蚀刻SOI衬底。 在单个室中蚀刻所有层减少了周转时间,降低了工艺成本,便于工艺控制和/或改善沟槽轮廓。
    • 14. 发明授权
    • Trench memory with self-aligned strap formed by self-limiting process
    • 沟槽记忆带自行排列的带子,由自限制过程形成
    • US07749835B2
    • 2010-07-06
    • US12048263
    • 2008-03-14
    • Xi LiKangguo ChengJohnathan Faltermeier
    • Xi LiKangguo ChengJohnathan Faltermeier
    • H01L21/84H01L21/8242
    • H01L29/945H01L21/32137H01L21/76232H01L21/84H01L27/1087H01L29/66181
    • A semiconductor structure is described. The structure includes a trench opening formed in a semiconductor substrate having a semiconductor-on-insulator (SOI) layer and a buried insulating (BOX) layer; and a filling material formed in the trench opening, the filling material forming a “V” shape within the trench memory cell, wherein the “V” shape includes a top portion substantially adjacent to a top surface of the BOX layer. A method of fabricating the semiconductor structure is also described. The method includes forming a trench opening in a semiconductor substrate having an SOI layer and a BOX layer; laterally etching the BOX layer such that a portion of the trench opening associated with the BOX layer is substantially greater than a portion of the trench opening associated with the SOI layer; filling the trench opening with a filling material; and recessing the filling material.
    • 描述半导体结构。 该结构包括形成在具有绝缘体上半导体(SOI)层和掩埋绝缘(BOX)层的半导体衬底中的沟槽开口; 以及形成在所述沟槽开口中的填充材料,所述填充材料在所述沟槽存储单元内形成“V”形,其中所述“V”形包括基本上邻近所述BOX层的顶表面的顶部。 还描述了制造半导体结构的方法。 该方法包括在具有SOI层和BOX层的半导体衬底中形成沟槽开口; 横向蚀刻BOX层,使得与BOX层相关联的沟槽开口的一部分基本上大于与SOI层相关联的沟槽开口的一部分; 用填充材料填充沟槽开口; 并使填充材料凹陷。
    • 16. 发明授权
    • Trench capacitor with void-free conductor fill
    • 沟槽电容器,无空隙导体填充
    • US07494891B2
    • 2009-02-24
    • US11533928
    • 2006-09-21
    • Kangguo ChengJohnathan E. FaltermeierXi Li
    • Kangguo ChengJohnathan E. FaltermeierXi Li
    • H01L21/20
    • H01L29/945H01L29/66181
    • A method forms a node dielectric in a bottle shaped trench and then deposits an initial conductor within the lower portion of the bottle shaped trench, such that a void is formed within the initial conductor. Next, the method forms an insulating collar in the upper portion of the bottle shaped trench above the initial conductor. Then, the method simultaneously etches a center portion of the insulating collar and the initial conductor until the void is exposed. This etching process forms a center opening within the insulating collar and the initial conductor. Additional conductor is deposited in the center opening such that the additional conductor is formed at least to the level of the surface of the substrate.
    • 一种方法在瓶形沟槽中形成节点电介质,然后将初始导体沉积在瓶形沟槽的下部,使得在初始导体内形成空隙。 接下来,该方法在初始导体上方的瓶形沟槽的上部形成绝缘套环。 然后,该方法同时蚀刻绝缘套环的中心部分和初始导体,直到暴露出空隙。 该蚀刻工艺在绝缘环和初始导体内形成中心开口。 附加导体沉积在中心开口中,使得附加导体至少形成至基底表面的水平。