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11. 发明授权

US08065555B2 System and method for error correction in cache units 有权
标题翻译：高速缓存单元纠错系统及方法
公开(公告)号：US08065555B2
公开(公告)日：2011-11-22
申请号：US11363150
申请日：2006-02-28
申请人： Subramaniam Maiyuran , Varghese George , Vladimir Pentkovski , Sanjib Sarkar , Marina Sherman
发明人： Subramaniam Maiyuran , Varghese George , Vladimir Pentkovski , Sanjib Sarkar , Marina Sherman
IPC分类号： G06F11/00
CPC分类号： G06F11/1064
摘要： A method and a processor may include storing a first set of data in a data array in a cache unit substantially concurrently to reading a second set of data from the data array, and using the second set of data to generate error correction data corresponding to the first set of data. A method or processor may include reading an entry from a cache in a processor and executing two or more error detection mechanisms on the entry substantially concurrently.
摘要翻译：方法和处理器可以包括将数据阵列中的第一组数据存储在高速缓存单元中，基本上同时从数据阵列读取第二组数据，并且使用第二组数据来生成对应于第一组数据。方法或处理器可以包括从处理器中的高速缓存读取条目，并且基本同时地在条目上执行两个或更多个错误检测机制。

12. 发明申请

US20070226589A1 System and method for error correction in cache units 有权
标题翻译：高速缓存单元纠错系统及方法
公开(公告)号：US20070226589A1
公开(公告)日：2007-09-27
申请号：US11363150
申请日：2006-02-28
申请人： Subramaniam Maiyuran , Varghese George , Vladimir Pentkovski , Sanjib Sarkar , Marina Sherman
发明人： Subramaniam Maiyuran , Varghese George , Vladimir Pentkovski , Sanjib Sarkar , Marina Sherman
IPC分类号： G11C29/00
CPC分类号： G06F11/1064
摘要： A method and a processor may include storing a first set of data in a data array in a cache unit substantially concurrently to reading a second set of data from the data array, and using the second set of data to generate error correction data corresponding to the first set of data. A method or processor may include reading an entry from a cache in a processor and executing two or more error detection mechanisms on the entry substantially concurrently.
摘要翻译：方法和处理器可以包括将数据阵列中的第一组数据存储在高速缓存单元中，基本上同时从数据阵列读取第二组数据，并且使用第二组数据来生成对应于第一组数据。方法或处理器可以包括从处理器中的高速缓存读取条目，并且基本同时地在条目上执行两个或更多个错误检测机制。

13. 发明授权

US06223276B1 Pipelined processing of short data streams using data prefetching 失效
标题翻译：使用数据预取流水线处理短数据流
公开(公告)号：US06223276B1
公开(公告)日：2001-04-24
申请号：US09053376
申请日：1998-03-31
申请人： Hsien-Hsin Lee , Vladimir Pentkovski , Hsien-Cheng E. Hsieh
发明人： Hsien-Hsin Lee , Vladimir Pentkovski , Hsien-Cheng E. Hsieh
IPC分类号： G06F930
CPC分类号： G06F9/3875 , G06F9/383
摘要： The present invention discloses a method and apparatus for processing strips of data, each strip referencing a plurality of parameter sets stored in a memory. The method comprises: prefetching a plurality of parameter sets referenced in a first strip; performing an operation on each of the prefetched parameter sets; and concatenating a first strip and a second strip to eliminate a memory access latency in the second strip.
摘要翻译：本发明公开了一种用于处理数据条带的方法和装置，每个条带参考存储在存储器中的多个参数集。该方法包括：预取在第一条带中引用的多个参数集; 对每个预取参数集执行操作; 并且连接第一条带和第二条带以消除第二条带中的存储器访问等待时间。

14. 发明授权

US06369813B2 Processing polygon meshes using mesh pool window 失效
标题翻译：使用网格池窗口处理多边形网格
公开(公告)号：US06369813B2
公开(公告)日：2002-04-09
申请号：US09109257
申请日：1998-06-30
申请人： Vladimir Pentkovski , Deep Buch , Michael K. Dwyer , Hsien-Hsin Lee , Hsien-Cheng E. Hsieh
发明人： Vladimir Pentkovski , Deep Buch , Michael K. Dwyer , Hsien-Hsin Lee , Hsien-Cheng E. Hsieh
IPC分类号： G06T1500
CPC分类号： G06T17/20
摘要： The present invention is directed to a method and apparatus for processing normalized meshes. The normalized meshes are formed by N polygons which have M vertices. M vertex coordinates are stored in a vertex array corresponding to the M vertices of the N polygons. N polygon indices are stored in an index array. Each of the N polygon indices references a predetermined number of the M vertex coordinates. A first subset of the index array having N1 polygon indices is determined. A second subset of the vertex array is selected such that the second subset contains M1 vertex coordinates corresponding entirely to the N1 polygon indices in the first subset. The second subset defines a window having a small size relative to the vertex array. The M1 vertex coordinates in the second subset are processed to generate processed data. The processed data are then concurrently sent to a graphics processor in an on-line manner.
摘要翻译：本发明涉及一种用于处理归一化网格的方法和装置。归一化网格由具有M个顶点的N个多边形形成。 M顶点坐标存储在与N个多边形的M个顶点对应的顶点数组中。 N个多边形索引存储在索引数组中。 N个多边形索引中的每一个引用预定数量的M个顶点坐标。确定具有N1个多边形索引的索引阵列的第一子集。选择顶点阵列的第二子集，使得第二子集包含完全对应于第一子集中的N1多边形索引的M1顶点坐标。第二个子集定义相对于顶点数组具有小尺寸的窗口。处理第二个子集中的M1顶点坐标以产生处理后的数据。然后，处理的数据以在线方式同时发送到图形处理器。

15. 发明授权

US06978357B1 Method and apparatus for performing cache segment flush and cache segment invalidation operations 失效
标题翻译：用于执行高速缓存段刷新和缓存段无效操作的方法和装置
公开(公告)号：US06978357B1
公开(公告)日：2005-12-20
申请号：US09122349
申请日：1998-07-24
申请人： Lance Hacking , Shreekant Thakkar , Thomas Huff , Vladimir Pentkovski , Hsien-Cheng E. Hsieh
发明人： Lance Hacking , Shreekant Thakkar , Thomas Huff , Vladimir Pentkovski , Hsien-Cheng E. Hsieh
IPC分类号： G06F12/08
CPC分类号： G06F12/0891 , G06F12/0804
摘要： A method and apparatus for including in a computer system, instructions for performing cache memory invalidate and cache memory flush operations. In one embodiment, the computer system comprises a cache memory having a plurality of cache lines each of which stores data, and a storage area to store a data operand. An execution unit is coupled to the storage area, and operates on data elements in the data operand to invalidate data in a predetermined portion of the plurality of cache lines in response to receiving a single instruction.
摘要翻译：一种用于在计算机系统中包括用于执行高速缓存存储器无效的指令和高速缓存存储器刷新操作的方法和装置。在一个实施例中，计算机系统包括具有存储数据的多个高速缓存行和存储数据操作数的存储区域的高速缓冲存储器。执行单元耦合到存储区域，并且响应于接收到单个指令，对数据操作数中的数据元素进行操作以使多个高速缓存行的预定部分中的数据无效。

16. 发明申请

US20050216706A1 Executing partial-width packed data instructions 有权
标题翻译：执行部分宽度打包的数据指令
公开(公告)号：US20050216706A1
公开(公告)日：2005-09-29
申请号：US11126049
申请日：2005-05-09
申请人： Mohammad Abdallah , James Coke , Vladimir Pentkovski , Patrice Roussel , Shreekant Thakkar
发明人： Mohammad Abdallah , James Coke , Vladimir Pentkovski , Patrice Roussel , Shreekant Thakkar
IPC分类号： G06F9/30 , G06F9/302 , G06F9/318
CPC分类号： G06F9/3875 , G06F9/30014 , G06F9/30036 , G06F9/30112 , G06F9/3013 , G06F9/30134 , G06F9/30145 , G06F9/30167 , G06F9/3017 , G06F9/30181 , G06F9/30196 , G06F9/384 , G06F9/3885
摘要： A method and apparatus are provided for executing packed data instructions. According to one aspect of the invention, a processor includes registers, a register renaming unit coupled to the registers, a decoder coupled to the register renaming unit, and a partial-width execution unit coupled to the decoder. The register renaming unit provides an architectural register file to store packed data operands that include data elements. The decoder is to decode a first and second set of instructions that each specify one or more registers in the architectural register file. Each of the instructions in the first set specify operations to be performed on all of the data elements. In contrast, each of the instructions in the second set specify operations to be performed on only a subset of the data elements. The partial-width execution unit is to execute operations specified by either the first or second set of instructions.
摘要翻译：提供了一种用于执行打包数据指令的方法和装置。根据本发明的一个方面，处理器包括寄存器，耦合到寄存器的寄存器重命名单元，耦合到寄存器重命名单元的解码器以及耦合到解码器的部分宽度执行单元。寄存器重命名单元提供架构寄存器文件来存储包括数据元素的打包数据操作数。解码器是对第一和第二组指令进行解码，每组指令在架构寄存器文件中指定一个或多个寄存器。第一组中的每个指令指定要对所有数据元素执行的操作。相比之下，第二组中的每个指令指定仅对数据元素的子集执行的操作。部分宽度执行单元是执行由第一组或第二组指令指定的操作。

17. 发明授权

US6085312A Method and apparatus for handling imprecise exceptions 失效
标题翻译：处理不精确异常的方法和装置
公开(公告)号：US6085312A
公开(公告)日：2000-07-04
申请号：US052994
申请日：1998-03-31
申请人： Mohammad Abdallah , Vladimir Pentkovski
发明人： Mohammad Abdallah , Vladimir Pentkovski
IPC分类号： G06F9/30 , G06F9/302 , G06F9/38 , G06F9/40
CPC分类号： G06F9/30036 , G06F9/3001 , G06F9/30145 , G06F9/3017 , G06F9/3857 , G06F9/3861
摘要： A method and apparatus for updating the architectural state in a system implementing staggered execution with multiple micro-instructions. According to one aspect of the invention, a method is provided in which a macro-instruction is decoded into a first and second micro-instructions. The macro-instruction designates an operation on a pieced of data, and execution of the first and second micro-instructions separately cause the operation to be performed on different parts of the piece of data. The method also requires that the first micro-instruction is executed irrespective of the second micro-instructions (e.g., at a different time), and that it is detected that said second micro-instruction will not cause any non-recoverable exceptions. The results of the first micro-instruction are then used to update the architectural state in an earlier clock cycle than said second micro-instruction.
摘要翻译：一种用于利用多个微指令来实现交错执行的系统中的架构状态的更新的方法和装置。根据本发明的一个方面，提供一种方法，其中宏指令被解码为第一和第二微指令。宏指令指定对接头数据的操作，并且第一和第二微指令的执行分别导致在该数据段的不同部分上执行操作。该方法还要求与第二微指令（例如，在不同的时间）无论执行第一微指令，并且检测到所述第二微指令不会引起任何不可恢复的异常。然后，第一微指令的结果用于在比所述第二微指令更早的时钟周期内更新架构状态。

18. 发明授权

US06970994B2 Executing partial-width packed data instructions 有权
标题翻译：执行部分宽度打包的数据指令
公开(公告)号：US06970994B2
公开(公告)日：2005-11-29
申请号：US09852217
申请日：2001-05-08
申请人： Mohammad Abdallah , James Coke , Vladimir Pentkovski , Patrice Roussel , Shreekant S. Thakkar
发明人： Mohammad Abdallah , James Coke , Vladimir Pentkovski , Patrice Roussel , Shreekant S. Thakkar
IPC分类号： G06F9/30 , G06F9/302 , G06F9/318
CPC分类号： G06F9/3875 , G06F9/30014 , G06F9/30036 , G06F9/30112 , G06F9/3013 , G06F9/30134 , G06F9/30145 , G06F9/30167 , G06F9/3017 , G06F9/30181 , G06F9/30196 , G06F9/384 , G06F9/3885
摘要： A method and apparatus for executing partial-width packed data instructions are discussed. The processor may include a plurality of registers, a register renaming unit, a decoder, and a partial-width execution unit. The register renaming unit provides an architectural register file to store packed data operands each of which include a plurality of data elements. The decoder is to decode a first and second set of instructions that each specify one or more registers in the architectural register file. The first set of instructions specify operations to be performed on all of the data elements stored in the one or more specified registers. In contrast, the second set of instructions specify operations to be performed on only a subset of the data elements. The partial-width execution unit is to execute operations specified by either of the first or the second set of instructions.
摘要翻译：讨论了用于执行部分宽度打包数据指令的方法和装置。处理器可以包括多个寄存器，寄存器重命名单元，解码器和部分宽度执行单元。寄存器重命名单元提供架构寄存器文件以存储打包数据操作数，每个数据操作数包括多个数据元素。解码器是对第一和第二组指令进行解码，每组指令在架构寄存器文件中指定一个或多个寄存器。第一组指令指定要对存储在一个或多个指定寄存器中的所有数据元素执行的操作。相比之下，第二组指令指定仅对数据元素的子集执行的操作。部分宽度执行单元是执行由第一组或第二组指令指定的操作。

19. 发明授权

US5995122A Method and apparatus for parallel conversion of color values from a single precision floating point format to an integer format 失效
标题翻译：将颜色值从单精度浮点格式并行转换为整数格式的方法和装置
公开(公告)号：US5995122A
公开(公告)日：1999-11-30
申请号：US71468
申请日：1998-04-30
申请人： Hsien-Cheng E. Hsieh , Thomas R. Huff , Vladimir Pentkovski , Patrice Roussel , Shreekant S. Thakkar
发明人： Hsien-Cheng E. Hsieh , Thomas R. Huff , Vladimir Pentkovski , Patrice Roussel , Shreekant S. Thakkar
IPC分类号： H03M7/24 , G06F13/00 , G06F15/80
CPC分类号： H03M7/24
摘要： A method and apparatus for parallel processing of graphics data are described. A number of color components are stored in a floating point format in at least one register of a set of 128-bit registers in a packed format. The color components in the floating point format are converted to numbers in an integer format. The numbers in the integer format are placed in at least one register of a set of 64-bit registers in the packed format. Color components are assembled for image pixels from the numbers in the integer format.
摘要翻译：描述用于并行处理图形数据的方法和装置。多个颜色分量以压缩格式在一组128位寄存器的至少一个寄存器中以浮点格式存储。浮点格式的颜色分量将以整数格式转换为数字。整数格式的数字以打包格式放置在一组64位寄存器的至少一个寄存器中。从整数格式的数字组装图像像素的颜色分量。

20. 发明授权

US07467286B2 Executing partial-width packed data instructions 有权
标题翻译：执行部分宽度打包的数据指令
公开(公告)号：US07467286B2
公开(公告)日：2008-12-16
申请号：US11126049
申请日：2005-05-09
申请人： Mohammad Abdallah , James Coke , Vladimir Pentkovski , Patrice Roussel , Shreekant S. Thakkar
发明人： Mohammad Abdallah , James Coke , Vladimir Pentkovski , Patrice Roussel , Shreekant S. Thakkar
IPC分类号： H04Q3/00
CPC分类号： G06F9/3875 , G06F9/30014 , G06F9/30036 , G06F9/30112 , G06F9/3013 , G06F9/30134 , G06F9/30145 , G06F9/30167 , G06F9/3017 , G06F9/30181 , G06F9/30196 , G06F9/384 , G06F9/3885
摘要： A method and apparatus are provided for executing packed data instructions. According to one aspect of the invention, a processor includes registers, a register renaming unit coupled to the registers, a decoder coupled to the register renaming unit, and a partial-width execution unit coupled to the decoder. The register renaming unit provides an architectural register file to store packed data operands that include data elements. The decoder is to decode a first and second set of instructions that each specify one or more registers in the architectural register file. Each of the instructions in the first set specify operations to be performed on all of the data elements. In contrast, each of the instructions in the second set specify operations to be performed on only a subset of the data elements. The partial-width execution unit is to execute operations specified by either the first or second set of instructions.
摘要翻译：提供了一种用于执行打包数据指令的方法和装置。根据本发明的一个方面，处理器包括寄存器，耦合到寄存器的寄存器重命名单元，耦合到寄存器重命名单元的解码器以及耦合到解码器的部分宽度执行单元。寄存器重命名单元提供架构寄存器文件来存储包括数据元素的打包数据操作数。解码器是对第一和第二组指令进行解码，每组指令在架构寄存器文件中指定一个或多个寄存器。第一组中的每个指令指定要对所有数据元素执行的操作。相比之下，第二组中的每个指令指定仅对数据元素的子集执行的操作。部分宽度执行单元是执行由第一组或第二组指令指定的操作。

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