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11. 发明申请

WO2011056527A3 METHODS AND APPARATUS FOR LAYOUT OF THREE DIMENSIONAL MATRIX ARRAY MEMORY FOR REDUCED COST PATTERNING 审中-公开
标题翻译：用于降低成本花纹的三维矩阵阵列存储器的布局方法和装置
公开(公告)号：WO2011056527A3
公开(公告)日：2011-12-08
申请号：PCT/US2010054013
申请日：2010-10-26
申请人： SANDISK 3D LLC , SCHEUERLEIN ROY E , PETTI CHRISTOPHER J , TANAKA YOICHIRO
发明人： SCHEUERLEIN ROY E , PETTI CHRISTOPHER J , TANAKA YOICHIRO
IPC分类号： H01L27/02 , H01L21/033 , H01L27/06 , H01L27/10
CPC分类号： G11C5/06 , H01L21/0337 , H01L27/0207 , H01L27/0688 , H01L27/101 , H01L27/2481 , H01L2924/0002 , Y10S257/909 , H01L2924/00
摘要： The present invention provides apparatus, methods, and systems for a memory layer layout for a three-dimensional memory. The memory layer includes a plurality of memory array blocks; a plurality of memory lines coupled to the memory array blocks; and a plurality of zia contact areas for coupling the memory layer to other memory layers in a three-dimensional memory. The memory lines extend from the memory array blocks and are formed using a sidewall defined process. The memory lines have a half pitch dimension smaller than the nominal minimum feature size capability of a lithography tool used in forming the memory lines. The zia contact areas have a dimension that is approximately four times the half pitch dimension of the memory lines. The memory lines are arranged in a pattern adapted to allow a single memory line to intersect a single zia contact area and to provide area between other memory lines for other zia contact areas. Numerous additional aspects are disclosed.
摘要翻译：本发明提供了一种用于三维存储器的存储器层布局的装置，方法和系统。存储层包括多个存储器阵列块; 耦合到所述存储器阵列块的多个存储器线; 以及用于将存储器层耦合到三维存储器中的其它存储器层的多个zia接触区域。存储器线从存储器阵列块延伸并且使用侧壁限定的工艺形成。存储线具有小于用于形成存储器线的光刻工具的标称最小特征尺寸能力的半间距尺寸。 zia接触区域的尺寸约为存储器线的半间距尺寸的四倍。存储线被布置成适于允许单个存储器线与单个zia接触区域相交并且为其它zia接触区域提供其它存储器线路之间的区域的图案。公开了许多附加方面。

12. 发明申请

WO2009088922A3 METHODS AND APPARATUS FOR FORMING MEMORY LINES AND VIAS IN THREE DIMENSIONAL MEMORY ARRAYS USING DUAL DAMASCENE PROCESS AND IMPRINT LITHOGRAPHY 审中-公开
标题翻译：使用双重DAMASCENE过程和IMPRINT LITHOGRAPHY在三维存储器阵列中形成存储器线和VIAS的方法和装置
公开(公告)号：WO2009088922A3
公开(公告)日：2009-09-24
申请号：PCT/US2008088628
申请日：2008-12-31
申请人： SANDISK 3D LLC , SCHEUERLEIN ROY E
发明人： SCHEUERLEIN ROY E
IPC分类号： H01L21/8239 , H01L21/027 , H01L21/28
CPC分类号： H01L21/48 , B82Y10/00 , B82Y40/00 , G03F7/0002 , H01L21/31144 , H01L21/76807 , H01L21/76817 , H01L23/5384 , H01L27/10 , H01L27/101 , H01L2221/1021 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides systems, apparatus, and methods for forming three dimensional memory arrays using a multi-depth imprint lithography mask and a damascene process An imprint lithography mask for manufacturing a memory layer in a three dimensional memory is described. The mask includes a translucent material formed with features for making an imprint in a transfer material to be used in a damascene process, the mask having a plurality of imprint depths. At least one imprint depth corresponds to trenches for forming memory lines and at least one depth corresponds to holes for forming vias. Numerous other aspects are disclosed.
摘要翻译：本发明提供使用多深度压印光刻掩模和镶嵌工艺形成三维存储器阵列的系统，装置和方法。描述了用于在三维存储器中制造存储层的压印光刻掩模。掩模包括半透明材料，其形成有用于在用于镶嵌工艺中的转印材料中进行印记的特征，所述掩模具有多个印痕深度。至少一个压印深度对应于用于形成存储器线的沟槽，并且至少一个深度对应于用于形成通孔的孔。公开了许多其他方面。

13. 发明申请

WO2006130800A2 REWRITEABLE MEMORY CELL COMPRISING A TRANSISTOR AND RESISTANCE-SWITCHING MATERIAL IN SERIES 审中-公开
标题翻译：系列中包含晶体管和电阻切换材料的可记忆存储器单元
公开(公告)号：WO2006130800A2
公开(公告)日：2006-12-07
申请号：PCT/US2006021372
申请日：2006-06-01
申请人： SANDISK 3D LLC , PETTI CHRISTOPHER J , SCHEUERLEIN ROY E
发明人： PETTI CHRISTOPHER J , SCHEUERLEIN ROY E
IPC分类号： H01L27/00 , H01L45/00
CPC分类号： H01L27/2436 , H01L27/2454 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/1675
摘要： A nonvolatile memory cell is provided, the cell comprising a transistor in series with resistance- switching material, which can be switched between at least two stable resistance states, for example a high-resistance state and a low-resistance state. In preferred embodiments the transistor is a TFT, having a channel region not formed in a monocrystalline wafer substrate. In preferred embodiments the transistor may have' either a vertically oriented ch'annel or a laterally oriented channel. Either embodiment can be formed in a monolithic three dimensional memory array in which multiple memory levels can be formed above a single substrate, forming a highly dense nonvolatile memory array.
摘要翻译：提供了一种非易失性存储单元，该单元包括与电阻切换材料串联的晶体管，该晶体管可以在至少两个稳定的电阻状态之间切换，例如高电阻状态和低电阻状态。在优选实施例中，晶体管是TFT，其具有未形成在单晶晶片衬底中的沟道区。在优选实施例中，晶体管可以具有“垂直定向的ch”通道或横向定向的通道。任何一个实施例可以形成在单片三维存储器阵列中，其中可以在单个衬底上方形成多个存储器级，形成高密度非易失性存储器阵列。

14. 发明申请

WO2011056529A3 APPARATUS AND METHODS OF FORMING MEMORY LINES AND STRUCTURES USING DOUBLE SIDEWALL PATTERNING FOR FOUR TIMES HALF PITCH RELIEF PATTERNING 审中-公开
标题翻译：设备和形成记忆线和结构的方法使用双侧壁图案进行四次半间距螺旋图案
公开(公告)号：WO2011056529A3
公开(公告)日：2011-12-08
申请号：PCT/US2010054017
申请日：2010-10-26
申请人： SANDISK 3D LLC , SCHEUERLEIN ROY E , TANAKA YOICHIRO
发明人： SCHEUERLEIN ROY E , TANAKA YOICHIRO
IPC分类号： H01L21/033 , H01L27/02 , H01L27/06 , H01L27/10
CPC分类号： G11C5/06 , H01L21/0337 , H01L27/0207 , H01L27/0688 , H01L27/101 , H01L27/2481 , H01L2924/0002 , Y10S257/909 , H01L2924/00
摘要： The present invention provides apparatus, methods, and systems for fabricating memory lines and structures using double sidewall patterning for four times half pitch relief patterning. The invention includes forming features from a first template layer disposed above a substrate, forming half-pitch sidewall spacers adjacent the features, forming smaller features in a second template layer by using the half-pitch sidewall spacers as a hardmask, forming quarter-pitch sidewall spacers adjacent the smaller features, and forming conductor features from a conductor layer by using the quarter-pitch sidewall spacers as a hardmask. Numerous additional aspects are disclosed.
摘要翻译：本发明提供了用于制造存储线和结构的装置，方法和系统，该存储线和结构使用用于四倍半节距浮雕图案化的双侧壁图案化。本发明包括：从设置在衬底上方的第一模板层形成特征，在特征附近形成半节距侧壁间隔物，通过使用半节距侧壁间隔物作为硬掩模在第二模板层中形成较小特征，形成四分之一节距侧壁通过使用四分之一节距侧壁间隔物作为硬掩模来形成来自导体层的导体特征。披露了许多其他方面。

15. 发明申请

WO2009088914A3 STORAGE SUB-SYSTEM FOR A COMPUTER COMPRISING WRITE-ONCE MEMORY DEVICES AND WRITE-MANY MEMORY DEVICES AND RELATED METHOD 审中-公开
标题翻译：用于包含写入存储器件和写入多个存储器件的计算机的存储子系统及相关方法
公开(公告)号：WO2009088914A3
公开(公告)日：2009-09-03
申请号：PCT/US2008088616
申请日：2008-12-31
申请人： SANDISK 3D LLC , SCHEUERLEIN ROY E , THAKUR RANDHIR , MOORE CHISTOPHER
发明人： SCHEUERLEIN ROY E , THAKUR RANDHIR , MOORE CHISTOPHER
IPC分类号： G06F13/12 , G06F3/06 , G06F12/00 , G06F13/00
CPC分类号： G06F12/0638 , G06F11/1415 , G06F12/1425 , G06F2212/2142
摘要： Methods and apparatus for a solid state non-volatile storage sub-system of a computer is provided. The storage sub-system may include a write-once storage sub-system memory device and a write-many storage sub-system memory device. Numerous other aspects are provided.
摘要翻译：提供了一种计算机固态非易失性存储子系统的方法和装置。存储子系统可以包括一次写入存储子系统存储器设备和多写存储子系统存储器设备。提供了许多其他方面。

16. 发明申请

WO2008016946A3 METHOD AND APPARATUS FOR READING A MULTI-LEVEL PASSIVE ELEMENT MEMORY CELL ARRAY 审中-公开
标题翻译：用于读取多级被动元件存储单元阵列的方法和装置
公开(公告)号：WO2008016946A3
公开(公告)日：2009-01-08
申请号：PCT/US2007074899
申请日：2007-07-31
申请人： SANDISK 3D LLC , SCHEUERLEIN ROY E , THORP TYLER J , FASOLI LUCA G
发明人： SCHEUERLEIN ROY E , THORP TYLER J , FASOLI LUCA G
IPC分类号： G11C16/04
CPC分类号： G11C11/56 , G11C11/5642 , G11C13/004 , G11C13/0069 , G11C16/24 , G11C16/26 , G11C2013/0054 , G11C2013/009 , G11C2211/5634 , G11C2213/77
摘要： A four level passive element cell has memory states corresponding to decreasing resistance levels, which are preferably mapped respectively to data states 11, 01, 00, and 10. The LSB and MSB are preferably mapped as part of different pages. To discriminate between memory cell states, the selected bit line current is sensed for at least two different combinations of reference current level and read bias voltage. A mid-level reference is used to read the LSB. When reading the MSB, a first reference between the 10 and 00 data states, and a second reference between 01 and 11 data states may be used, and the mid-level reference need not be used. In certain embodiments, the bit line current may be simultaneously compared against the first and second references, without requiring a delay to stabilize the bit line current to a different value, and the MSB generated accordingly.
摘要翻译：四级无源元件单元具有对应于降低电阻电平的存储器状态，其优选地分别映射到数据状态11,01,00和10. LSB和MSB优选地被映射为不同页面的一部分。为了区分存储单元状态，对于参考电流电平和读取偏置电压的至少两种不同的组合来检测所选择的位线电流。中间级参考用于读取LSB。当读取MSB时，可以使用10和00数据状态之间的第一个参考，并且可以使用01和11数据状态之间的第二个参考，并且不需要使用中间级参考。在某些实施例中，位线电流可以同时与第一和第二参考值进行比较，而不需要延迟来将位线电流稳定到不同的值，并且相应地生成MSB。

17. 发明申请

WO2008016833A3 INCREASING WRITE VOLTAGE PULSE OPERATIONS IN NON-VOLATILE MEMORY 审中-公开
标题翻译：在非易失性存储器中增加写入电压脉冲运算
公开(公告)号：WO2008016833A3
公开(公告)日：2008-07-17
申请号：PCT/US2007074507
申请日：2007-07-26
申请人： SANDISK 3D LLC , SCHEUERLEIN ROY E , KUMAR TANMAY
发明人： SCHEUERLEIN ROY E , KUMAR TANMAY
IPC分类号： G11C13/00 , G11C11/56 , G11C17/16
CPC分类号： G11C13/0007 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C2013/009 , G11C2013/0092 , G11C2213/32 , G11C2213/33 , G11C2213/34 , G11C2213/72
摘要： A passive element memory device is provided that includes memory cells comprised of a state change element in series with a steering element. Controlled pulse operations are used to perform resistance changes associated with set and reset operations in an array of memory cells. Selected memory cells in an array are switched to a target resistance state in one embodiment by applying a positive voltage pulse to selected first array lines while applying a negative voltage pulse to selected second array lines. An amplitude of voltage pulses can be increased while being applied to efficiently and safely switch the resistance of cells having different operating characteristics. The cells are subjected to reverse biases in embodiments to lower leakage currents and increase bandwidth. The amplitude and duration of voltage pulses are controlled, along with the current applied to selected memory cells in some embodiments. These controlled pulse-based operations can be used to set memory cells to a lower resistance state or reset memory cells to a higher resistance state in various embodiments.
摘要翻译：提供了一种无源元件存储器件，其包括由与转向元件串联的状态改变元件构成的存储单元。受控脉冲操作用于执行与存储器单元阵列中的置位和复位操作相关的电阻变化。在一个实施例中，通过对所选择的第一阵列线施加正电压脉冲同时向所选择的第二阵列线施加负电压脉冲，将阵列中的选定存储单元切换到目标电阻状态。可以增加电压脉冲的幅度，同时施加以有效和安全地切换具有不同操作特性的电池的电阻。在实施例中，电池经受反向偏置以降低泄漏电流并增加带宽。在一些实施例中，电压脉冲的幅度和持续时间与在选择的存储器单元上施加的电流一起被控制。这些受控的基于脉冲的操作可以用于在各种实施例中将存储器单元设置为较低的电阻状态或将存储器单元重置为更高的电阻状态。

18. 发明申请

WO2008016844A3 NON-VOLATILE MEMORY CAPABLE OF CORRECTING OVERWRITTEN CELL 审中-公开
标题翻译：非易失性记忆能够修复过度细胞
公开(公告)号：WO2008016844A3
公开(公告)日：2008-03-27
申请号：PCT/US2007074564
申请日：2007-07-27
申请人： SANDISK 3D LLC , SCHEUERLEIN ROY E , KUMAR TANMAY
发明人： SCHEUERLEIN ROY E , KUMAR TANMAY
IPC分类号： G11C11/56 , G11C11/00 , G11C13/00 , G11C17/16
CPC分类号： G11C13/0007 , G11C5/02 , G11C11/5685 , G11C13/0069 , G11C16/3413 , G11C17/16 , G11C2013/009 , G11C2211/5641 , G11C2213/32 , G11C2213/33 , G11C2213/34 , G11C2213/71 , G11C2213/72
摘要： A reverse bias trim operation for the reset state of a non-volatile memory system is disclosed. Non-volatile memory cells including a resistance change element undergo a reverse bias reset operation to change their resistance from a set state at a first level of resistance to a reset state at a second level of resistance. Certain memory cells in a set of cells that was reset may be deeply reset to a level of resistance beyond a target level for the reset state. A second reverse bias is applied to the set of memory cells to move the resistance of each cell that was deeply reset toward the target level of the reset state. A smaller reverse bias than used for the reset operation can shift the resistance of the cells back toward the set level and out of their deeply reset condition. The operation is self-limiting in that cells stop their resistance shifts upon reaching the target level. Cells that were not deeply reset are not affected.
摘要翻译：公开了一种用于非易失性存储器系统的复位状态的反偏压调整操作。包括电阻变化元件的非易失性存储单元经历反向偏置复位操作，以将其电阻从第一电阻上的设定状态改变为第二电阻电平的复位状态。复位的一组单元格中的某些存储单元可以被重新设置为超出复位状态的目标电平的电阻水平。第二反向偏压被施加到该组存储器单元以将每个单元的电阻移动到复位状态的目标电平。与用于复位操作相比较小的反向偏压可以将电池的电阻转移回设定电平并且超出它们的深度复位状态。操作是自限制的，因为细胞在达到目标水平时停止其阻力位移。没有重新设置的单元格不受影响。

19. 发明申请

WO2007008903A3 MEMORY CELL COMPRISING A THIN FILM THREE-TERMINAL SWITCHING DEVICE HAVING A METAL SOURCE AND/OR DRAIN REGION 审中-公开
标题翻译：包含金属源和/或排水区域的薄膜三端开关装置的存储单元
公开(公告)号：WO2007008903A3
公开(公告)日：2007-06-21
申请号：PCT/US2006026898
申请日：2006-07-11
申请人： SANDISK 3D LLC , SCHEUERLEIN ROY E , PETTI CHRISTOPHER J
发明人： SCHEUERLEIN ROY E , PETTI CHRISTOPHER J
IPC分类号： H01L21/8247 , G11C11/34 , G11C11/56 , G11C13/02 , G11C16/02 , H01L21/84 , H01L27/06 , H01L27/07 , H01L27/112 , H01L27/115 , H01L27/12 , H01L27/24
CPC分类号： H01L27/1203 , G11C11/5614 , G11C11/5685 , G11C13/0007 , G11C13/0011 , G11C2213/31 , G11C2213/51 , G11C2213/56 , G11C2213/71 , G11C2213/79 , H01L21/84 , H01L27/101 , H01L27/112 , H01L27/11206 , H01L27/115 , H01L27/11502 , H01L27/11507 , H01L27/2436 , H01L27/2454 , H01L29/685 , H01L29/786 , H01L29/8605 , H01L45/085 , H01L45/1226 , H01L45/1233 , H01L45/1266 , H01L45/141 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/1675
摘要： A nonvolatile memory cell comprising a switchable resistor memory element ion reservoir (212) , chalcogenide (214) , silicided top electrode (216 and 202) and a thin-film three- terminal switching device, preferably a MOSFET source/drain regions (220) , channel (224) , gate dielectric (226) , gate (228) in series. The switchable resistor memory element has the property of having at least two stable resistance states, for example a high- resistance state and a low-resistance state. It is switched between the two states, and its resistance state (and thus the data state of the cell) is sensed by providing appropriate current through the three-terminal switching device . At least one source/drain region of the switching device is not formed by a doped semiconductor region but forms a schottky contact with the channel . Preferred embodiments of the present invention include a highly dense monolithic three dimensional memory array in which multiple memory levels of such memory cells are formed above a single substrate such as a monocrystalline silicon wafer.
摘要翻译：一种非易失性存储单元，包括可切换电阻器存储元件离子储存器（212），硫族化物（214），硅化顶部电极（216和202）和薄膜三端开关器件，优选MOSFET源极/漏极区域（220），通道（224），栅极电介质（226），栅极（228）。可切换电阻存储元件具有至少两个稳定的电阻状态的特性，例如高电阻状态和低电阻状态。它在两个状态之间切换，并且通过提供通过三端开关装置的适当电流来感测其电阻状态（以及因此的小区的数据状态）。开关器件的至少一个源极/漏极区域不是由掺杂半导体区域形成，而是形成与沟道的肖特基接触。本发明的优选实施例包括高密度单片三维存储器阵列，其中这种存储器单元的多个存储器级别形成在诸如单晶硅晶片的单个衬底上方。

20. 发明申请

WO2007008699A2 APPARATUS AND METHOD FOR READING AN ARRAY OF NONVOLATILE MEMORY CELLS INCLUDING SWITCHABLE RESISTOR MEMORY ELEMENTS 审中-公开
标题翻译：读取包含可切换电阻内存元件的非易失性存储器单元阵列的装置和方法
公开(公告)号：WO2007008699A2
公开(公告)日：2007-01-18
申请号：PCT/US2006026579
申请日：2006-07-10
申请人： SANDISK 3D LLC , SCHEUERLEIN ROY E
发明人： SCHEUERLEIN ROY E
IPC分类号： G11C7/10
CPC分类号： G11C13/0011 , G11C11/5685 , G11C13/004 , G11C2013/0054 , G11C2213/71 , G11C2213/79
摘要： A non-volatile memory cell includes a switchable resistor memory element in series with a switch device. An array of such cells may be programmed using only positive voltages. A method for programming such cells also supports a direct write of both 0 and 1 data states without requirement of a block erase operation, and is scalable for use with relatively low voltage power supplies. A method for reading such cells reduces read disturb of a selected memory cell by impressing a read bias voltage having a polarity opposite that of a set voltage employed to change the switchable resistor memory element to a low resistance state. Such programming and read methods are well suited for use in a three-dimensional memory array formed on multiple levels above a substrate, particularly those having extremely compact array line drivers on very tight layout pitch.
摘要翻译：非易失性存储单元包括与开关器件串联的可切换电阻器存储元件。可以仅使用正电压来编程这样的单元阵列。用于编程这样的单元的方法还支持直接写0和1数据状态，而不需要块擦除操作，并且可扩展以用于相对低电压的电源。用于读取这种单元的方法通过将具有极性与用于将可切换电阻器存储元件改变为低电阻状态的设定电压的极性相反的读取偏置电压来减小所选存储单元的读取干扰。这种编程和读取方法非常适用于形成在衬底上的多个层级上的三维存储器阵列，特别是在非常紧凑的布局间距上具有非常紧凑的阵列线驱动器的那些。

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