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11. 发明授权

US06890677B2 Fuel cell and membrane 失效
标题翻译：燃料电池和膜
公开(公告)号：US06890677B2
公开(公告)日：2005-05-10
申请号：US10056736
申请日：2002-01-24
申请人： Tom Klitsner , Alan P. Sylwester , Gail N. Ryba , Thomas E. Zipperian , Stanley H. Kravitz , Andrew Hecht
发明人： Tom Klitsner , Alan P. Sylwester , Gail N. Ryba , Thomas E. Zipperian , Stanley H. Kravitz , Andrew Hecht
IPC分类号： H01M4/86 , H01M4/88 , H01M4/90 , H01M4/92 , H01M8/02 , H01M8/10 , H01M8/12 , H01M8/18 , H01M8/24
CPC分类号： H01M4/881 , H01M4/8605 , H01M4/92 , H01M8/1016 , H01M8/1097 , H01M8/241 , H01M2300/0094 , Y02P70/56
摘要： Fuel cells and a novel membrane for use in fuel cells and manufacturing processes.
摘要翻译：燃料电池和用于燃料电池和制造工艺的新型膜。

12. 发明授权

US5479033A Complementary junction heterostructure field-effect transistor 失效
标题翻译：互补结异构结场场效应晶体管
公开(公告)号：US5479033A
公开(公告)日：1995-12-26
申请号：US250088
申请日：1994-05-27
申请人： Albert G. Baca , Timothy J. Drummond , Perry J. Robertson , Thomas E. Zipperian
发明人： Albert G. Baca , Timothy J. Drummond , Perry J. Robertson , Thomas E. Zipperian
IPC分类号： H01L27/06 , H01L29/80 , H01L31/0376 , H01L31/072
CPC分类号： H01L27/0605 , H01L29/802
摘要： A complimentary pair of compound semiconductor junction heterostructure field-effect transistors and a method for their manufacture are disclosed. The p-channel junction heterostructure field-effect transistor uses a strained layer to split the degeneracy of the valence band for a greatly improved hole mobility and speed. The n-channel device is formed by a compatible process after removing the strained layer. In this manner, both types of transistors may be independently optimized. Ion implantation is used to form the transistor active and isolation regions for both types of complimentary devices. The invention has uses for the development of low power, high-speed digital integrated circuits.
摘要翻译：公开了一对互补的化合物半导体结异质结场场效应晶体管及其制造方法。 p沟道结异质结场场效应晶体管使用应变层来分离价带的简并性，大大提高了空穴迁移率和速度。去除应变层后，n通道器件由兼容的工艺形成。以这种方式，可以独立优化两种类型的晶体管。离子注入用于形成两种类型的互补器件的晶体管有源和隔离区域。本发明用于开发低功率，高速数字集成电路。

13. 发明授权

US5358928A High temperature superconductor step-edge Josephson junctions using Ti-Ca-Ba-Cu-O 失效
标题翻译：使用Ti-Ca-Ba-Cu-O的高温超导体步进约瑟夫逊结
公开(公告)号：US5358928A
公开(公告)日：1994-10-25
申请号：US949098
申请日：1992-09-22
申请人： David S. Ginley , Vincent M. Hietala , Gert K. G. Hohenwarter , Jon S. Martens , Thomas A. Plut , Chris P. Tigges , Gregory A. Vawter , Thomas E. Zipperian
发明人： David S. Ginley , Vincent M. Hietala , Gert K. G. Hohenwarter , Jon S. Martens , Thomas A. Plut , Chris P. Tigges , Gregory A. Vawter , Thomas E. Zipperian
IPC分类号： H01L39/22 , H01B12/00 , H01L27/12
CPC分类号： H01L39/225 , Y10S505/702 , Y10S505/783 , Y10S505/832
摘要： A process for formulating non-hysteretic and hysteretic Josephson junctions using HTS materials which results in junctions having the ability to operate at high temperatures while maintaining high uniformity and quality. The non-hysteretic Josephson junction is formed by step-etching a LaAlO.sub.3 crystal substrate and then depositing a thin film of TlCaBaCuO on the substrate, covering the step, and forming a grain boundary at the step and a subsequent Josephson junction. Once the non-hysteretic junction is formed the next step to form the hysteretic Josephson junction is to add capacitance to the system. In the current embodiment, this is accomplished by adding a thin dielectric layer, LaA1O.sub.3, followed by a cap layer of a normal metal where the cap layer is formed by first depositing a thin layer of titanium (Ti) followed by a layer of gold (Au). The dielectric layer and the normal metal cap are patterned to the desired geometry.
摘要翻译：使用HTS材料制备非迟滞和滞后的约瑟夫逊结的方法，其导致具有在高温下操作并且保持高均匀性和质量的能力的结。通过对LaAlO 3晶体衬底进行步骤蚀刻，然后在衬底上沉积TlCaBaCuO的薄膜，覆盖该步骤，并在该步骤和随后的约瑟夫逊结处形成晶界而形成非滞后约瑟夫逊结。一旦形成非滞后结，形成滞后约瑟夫逊结的下一步就是向系统增加电容。在当前的实施例中，这是通过添加薄的电介质层LaAlO3，其次是正常金属的覆盖层，其中通过首先沉积钛（Ti）的薄层，随后是金层 Au）。电介质层和普通金属帽被图案化成所需的几何形状。

14. 发明授权

US5031007A SLS complementary logic devices with increase carrier mobility 失效
标题翻译： SLS互补逻辑器件增加载波移动性
公开(公告)号：US5031007A
公开(公告)日：1991-07-09
申请号：US604399
申请日：1990-10-26
申请人： Roger J. Chaffin , Gordon C. Osbourn , Thomas E. Zipperian
发明人： Roger J. Chaffin , Gordon C. Osbourn , Thomas E. Zipperian
IPC分类号： H01L27/095 , H01L29/15 , H01L29/778
CPC分类号： H01L29/7783 , H01L27/095 , H01L29/155
摘要： In an electronic device comprising a semiconductor material and having at least one performance characteristic which is limited by the mobility of holes in the semiconductor material, said mobility being limited because of a valence band degeneracy among high-mobility and low-mobility energy levels accessible to said holes at the energy-momentum space maximum, an improvement is provided wherein the semiconductor material is a strained layer superlattice (SLS) whose layer compositions and layer thicknesses are selected so that the strain on the layers predominantly containing said at least one carrier type splits said degeneracy and modifies said energy levels around said energy-momentum space maximum in a manner whereby said limitation on the mobility of said holes is alleviated.
摘要翻译：在包括半导体材料并且具有被半导体材料中的空穴的迁移率限制的至少一个性能特征的电子器件中，由于高迁移率和低迁移率能级之间的价带简并性而限制了所述迁移率，所述孔在能量动量空间最大时，提供了一种改进，其中半导体材料是其层组成和层厚度被选择的应变层超晶格（SLS），使得主要包含所述至少一种载流子类型的层上的应变分裂所述简并性并且以所述能量 - 动量空间最大值周围的所述能级改变，从而减轻所述孔的迁移率的所述限制。

15. 发明授权

US4868624A Channel collector transistor 失效
标题翻译：通道集电极晶体管
公开(公告)号：US4868624A
公开(公告)日：1989-09-19
申请号：US841012
申请日：1986-03-14
申请人： Bernard L. Grung , Raymond M. Warner, Jr. , Thomas E. Zipperian
发明人： Bernard L. Grung , Raymond M. Warner, Jr. , Thomas E. Zipperian
IPC分类号： H01L29/06 , H01L29/08 , H01L29/36 , H01L29/73 , H01L29/84
CPC分类号： H01L29/36 , H01L29/0692 , H01L29/0821 , H01L29/7302 , H01L29/7317 , H01L29/84
摘要： A monolithic semiconductor transistor structure is described wherein the active collector region of a bipolar-junction transistor is physically and operatively merged with the channel region of a junction field-effect transistor, providing a composite circuit which approximates a cascode configuration. By controlling the integral of the net impurity doping concentration to various active regions of the device, the active collector region of a bipolar-junction transistor configuration is made sufficiently thin so as to simultaneously function as an active collector region as well as a channel region of one or more field-effect transistors. The channel-collector transistor provides high breakdown voltage, high dynamic resistance and linearity over a wide voltage range, and is compatible with solid-state batch fabrication processes for direct incorporation into larger integrated circuits. The device is particularly suitable for linear applications. Improved operating current is obtained and current limiting constraints of the device are minimized by cooperative emitter and base configurations, topologically extended to maximize use of available circuit area. Interdigitated base and collector region layout further improves operating performance.
摘要翻译：描述了单片半导体晶体管结构，其中双极结晶体管的有源集电极区域物理地和可操作地与结型场效应晶体管的沟道区域合并，提供近似共源共栅配置的复合电路。通过控制器件的各种有源区域的净杂质掺杂浓度的积分，双极结晶体管结构的有源集电极区域被制成足够薄，以同时用作有源集电极区域以及沟道区域一个或多个场效应晶体管。通道集电极晶体管在宽电压范围内提供高击穿电压，高动态电阻和线性度，并且与固态批量制造工艺兼容，可直接并入大型集成电路。该器件特别适用于线性应用。获得了改进的工作电流，并通过协同发射器和基极配置来最小化器件的限流约束，拓扑拓展到最大限度地利用可用电路面积。交叉的基极和集电极区域布局进一步提高了操作性能。

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