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11. 发明申请

US20080307203A1 Scaling Instruction Intervals to Identify Collection Points for Representative Instruction Traces 失效
标题翻译：缩放指令间隔以识别代表性指令跟踪的收集点
公开(公告)号：US20080307203A1
公开(公告)日：2008-12-11
申请号：US11758031
申请日：2007-06-05
申请人： Robert H. Bell, JR. , Wen-Tzer T. Chen , Richard J. Eickemeyer , Venkat R. Indukuru , Pattabi M. Seshadri , Madhavi G. Valluri
发明人： Robert H. Bell, JR. , Wen-Tzer T. Chen , Richard J. Eickemeyer , Venkat R. Indukuru , Pattabi M. Seshadri , Madhavi G. Valluri
IPC分类号： G06F9/30
CPC分类号： G06F11/36
摘要： A method, system, and computer program product are provided for identifying instructions to obtain representative traces. A phase instruction budget is calculated for each phase in a set of phases. The phase instruction budget is based on a weight associated with each phase and a global instruction budget. A starting index and an ending index are identified for instructions within a set of intervals in each phase in order to meet the phase instruction budget for that phase, thereby forming a set of interval indices. A determination is made as to whether the instructions within the set of interval indices meet the global instruction budget. Responsive to the global instruction budget being met, the set of interval indices are output as collection points for the representative traces.
摘要翻译：提供方法，系统和计算机程序产品用于识别指令以获得代表性迹线。针对一组阶段中的每个阶段计算相位指令预算。相位指令预算基于与每个阶段相关联的权重和全局指令预算。为了满足该阶段的相位指令预算，为每个阶段的一组间隔内的指令识别开始索引和结束索引，从而形成一组间隔索引。确定区间指标集内的指令是否符合全球指令预算。响应于满足全球指令预算，间隔指数的集合作为代表性跟踪的收集点输出。

12. 发明申请

US20120198187A1 Technique for preserving memory affinity in a non-uniform memory access data processing system 审中-公开
标题翻译：在不均匀的存储器访问数据处理系统中保存记忆亲和性的技术
公开(公告)号：US20120198187A1
公开(公告)日：2012-08-02
申请号：US13015733
申请日：2011-01-28
申请人： Mathew Accapadi , Robert H. Bell, JR. , Men-Chow Chiang , Hong L. Hua
发明人： Mathew Accapadi , Robert H. Bell, JR. , Men-Chow Chiang , Hong L. Hua
IPC分类号： G06F12/12 , G06F12/08
CPC分类号： G06F9/5016 , G06F9/5088 , G06F2212/2542 , Y02D10/22 , Y02D10/32
摘要： Techniques for preserving memory affinity in a computer system is disclosed. In response to a request for memory access to a page within a memory affinity domain, a determination is made if the request is initiated by a processor associated with the memory affinity domain. If the request is not initiated by a processor associated with the memory affinity domain, a determination is made if there is a page ID match with an entry within a page migration tracking module associated with the memory affinity domain. If there is no page ID match, an entry is selected within the page migration tracking module to be updated with a new page ID and a new memory affinity ID. If there is a page ID match, then another determination is made whether or not there is a memory affinity ID match with the entry with the page ID field match. If there is no memory affinity ID match, the entry is updated with a new memory affinity ID; and if there is a memory affinity ID match, an access counter of the entry is incremented.
摘要翻译：公开了一种用于在计算机系统中保存记忆亲和性的技术。响应于对存储器相关域中的页面的存储器访问的请求，确定该请求是否由与存储器相关域相关联的处理器发起。如果请求不是由与存储器相关性域相关联的处理器发起，则确定是否存在与存储器相关域相关联的页面迁移跟踪模块内的条目的页面ID匹配。如果没有页面ID匹配，则在页面迁移跟踪模块中选择要更新新页面ID和新的内存关联ID的条目。如果存在页面ID匹配，则另外确定存储器相关性ID是否与页面ID字段匹配的条目匹配。如果没有内存关联ID匹配，则该条目将使用新的内存关联ID更新; 并且如果存在存储器相关性ID匹配，则增加该条目的访问计数器。

13. 发明申请

US20090186494A1 APPARATUS, SYSTEM, AND METHOD FOR A CONFIGURABLE BLADE CARD 有权
标题翻译：用于可配置刀片的设备，系统和方法
公开(公告)号：US20090186494A1
公开(公告)日：2009-07-23
申请号：US12016043
申请日：2008-01-17
申请人： Robert H. Bell, JR. , Jose R. Escalera , Octavian F. Herescu , Vernon W. Miller , Michael D. Roll
发明人： Robert H. Bell, JR. , Jose R. Escalera , Octavian F. Herescu , Vernon W. Miller , Michael D. Roll
IPC分类号： H01R12/00
CPC分类号： G06F13/409 , H05K7/1487
摘要： An apparatus, system, and method are disclosed for a configurable blade card. A base card is in physical and electrical communication with a blade connector. The blade connector is in physical and electrical communication with a blade enclosure connector. A secondary card is in physical and electrical communication with the base card to form a blade card. A coupler physically couples the base card and the secondary card. The base card and the secondary card are co-planar and compatible with a blade card form factor.
摘要翻译：公开了一种用于可配置的刀片卡的装置，系统和方法。基卡与刀片连接器物理和电气通信。刀片连接器与刀片机箱连接器物理和电气通信。辅助卡与基卡进行物理和电气通信以形成刀片卡。耦合器物理耦合基卡和辅助卡。基卡和辅助卡是共面的，与刀片卡形状兼容。

14. 发明申请

US20090138220A1 Power-aware line intervention for a multiprocessor directory-based coherency protocol 审中-公开
标题翻译：基于多处理器目录的一致性协议的功率感知线路干预
公开(公告)号：US20090138220A1
公开(公告)日：2009-05-28
申请号：US11946551
申请日：2007-11-28
申请人： Robert H. Bell, JR. , Louis B. Capps, JR. , Thomas E. Cook , Michael J. Shapiro , Naresh Nayar
发明人： Robert H. Bell, JR. , Louis B. Capps, JR. , Thomas E. Cook , Michael J. Shapiro , Naresh Nayar
IPC分类号： G01R21/02 , G06F12/08
CPC分类号： G06F12/0817 , Y02D10/13
摘要： A directory-based coherency method, system and program are provided for intervening a requested cache line from a plurality of candidate memory sources in a multiprocessor system on the basis of the sensed temperature or power dissipation value at each memory source. By providing temperature or power dissipation sensors in each of the candidate memory sources (e.g., at cores, cache memories, memory controller, etc.) that share a requested cache line, control logic may be used to determine which memory source should source the cache line by using the power sensor signals to signal only the memory source with acceptable power dissipation to provide the cache line to the requester.
摘要翻译：基于目录的一致性方法，系统和程序被提供用于基于每个存储器源处的感测温度或功率耗散值来在多处理器系统中从多个候选存储器源插入所请求的高速缓存行。通过在共享所请求的高速缓存行的每个候选存储器源（例如，在内核，高速缓冲存储器，存储器控制器等）中提供温度或功率耗散传感器，可以使用控制逻辑来确定哪个存储器源应该来源于高速缓存通过使用功率传感器信号仅以可接受的功率消耗信号通知存储器源，以向请求器提供高速缓存线。

15. 发明申请

US20120130928A1 EFFICIENT STORAGE OF INDIVIDUALS FOR OPTIMIZATION SIMULATION 有权
标题翻译：有效存储个人优化模拟
公开(公告)号：US20120130928A1
公开(公告)日：2012-05-24
申请号：US12948850
申请日：2010-11-18
申请人： Robert H. Bell, JR. , Jason F. Cantin
发明人： Robert H. Bell, JR. , Jason F. Cantin
IPC分类号： G06N3/12 , G06F15/18
CPC分类号： G06N3/126
摘要： Candidate solutions to an optimization problem comprise a set of potential values that can be applied to variables in a problem description. Candidate solutions can be large because of the complexity of optimization problems and large number of variables. The populations of candidate solutions may also be large to ensure diversity and effectiveness in computing a solution. When the populations and the candidate solutions are large for an optimization problem, computing a solution to the optimization problem consumes a large amount of memory. In some instances, several generations of candidate solutions are stored in memory. Compression of the candidate solutions can minimize the memory space consumed to compute a solution to an optimization problem.
摘要翻译：优化问题的候选解决方案包括可以应用于问题描述中的变量的一组潜在值。候选解决方案可能很大，因为优化问题和大量变量的复杂性。候选解决方案的人数也可能很大，以确保计算解决方案的多样性和有效性。当人口和候选解决方案对于优化问题很大时，计算优化问题的解决方案会消耗大量的内存。在某些情况下，几代候选解决方案存储在内存中。压缩候选解决方案可以最大限度地减少计算优化问题解决方案所消耗的内存空间。

16. 发明申请

US20120002812A1 DATA AND CONTROL ENCRYPTION 有权
标题翻译：数据和控制加密
公开(公告)号：US20120002812A1
公开(公告)日：2012-01-05
申请号：US12828080
申请日：2010-06-30
申请人： Robert H. Bell, JR. , Louis B. Capps, JR. , Michael J. Shapiro
发明人： Robert H. Bell, JR. , Louis B. Capps, JR. , Michael J. Shapiro
IPC分类号： H04L9/20 , H04L9/08 , H04K1/04 , H04L9/18
CPC分类号： H04L9/06 , H04L9/0618 , H04L2209/125
摘要： Secure communication of data between devices includes encrypting unencrypted data at a first device by reordering unencrypted bits provided in parallel on a device bus, including data and control bits, from an unencrypted order to form encrypted data including a plurality of encrypted bits in parallel in an encrypted order defined by a key. The encrypted data may be transmitted to another device where the encrypted data is decrypted by using the key to order the encrypted bits to restore the unencrypted order thereby to reform the unencrypted data.
摘要翻译：设备之间的数据的安全通信包括通过从未加密的顺序重新排序设备总线（包括数据和控制位）并行提供的未加密比特来在第一设备处对未加密的数据进行加密，以形成包括多个加密比特的加密数据由密钥定义的加密顺序。加密数据可以通过使用密钥来对加密数据进行解密的另一设备发送到另一个设备，以对加密的比特进行命令以恢复未加密的顺序，从而改变未加密的数据。

17. 发明申请

US20110271283A1 ENERGY-AWARE JOB SCHEDULING FOR CLUSTER ENVIRONMENTS 失效
标题翻译：集群环境能源考核工作安排
公开(公告)号：US20110271283A1
公开(公告)日：2011-11-03
申请号：US12917421
申请日：2010-11-01
申请人： Robert H. Bell, JR. , Luigi Brochard , Donald R. DeSota , Rajendra D. Panda , Francois Thomas
发明人： Robert H. Bell, JR. , Luigi Brochard , Donald R. DeSota , Rajendra D. Panda , Francois Thomas
IPC分类号： G06F9/46
CPC分类号： G06F9/5094 , Y02D10/22
摘要： A job scheduler can select a processor core operating frequency for a node in a cluster to perform a job based on energy usage and performance data. After a job request is received, an energy aware job scheduler accesses data that specifies energy usage and job performance metrics that correspond to the requested job and a plurality of processor core operating frequencies. A first of the plurality of processor core operating frequencies is selected that satisfies an energy usage criterion for performing the job based, at least in part, on the data that specifies energy usage and job performance metrics that correspond to the job. The job is assigned to be performed by a node in the cluster at the selected first of the plurality of processor core operating frequencies.
摘要翻译：作业调度器可以为集群中的节点选择处理器核心工作频率，以基于能量使用和性能数据执行作业。在接收到作业请求之后，能量感知作业调度器访问指定对应于所请求的作业和多个处理器核心操作频率的能量使用和作业性能度量的数据。至少部分地基于指定与作业相对应的能量使用和作业性能度量的数据，选择满足用于执行作业的能量使用准则的多个处理器核心操作频率中的第一个。该作业被分配为由多个处理器核心工作频率中所选择的第一个处理器核心工作频率中的簇中的节点执行。

18. 发明申请

US20100186018A1 OFF-LOADING OF PROCESSING FROM A PROCESSOR BADE TO STORAGE BLADES 失效
标题翻译：从加工板到加工刀片加工加工
公开(公告)号：US20100186018A1
公开(公告)日：2010-07-22
申请号：US12356030
申请日：2009-01-19
申请人： Robert H. Bell, JR. , Jose Raul Escalera , Octavian Florin Herescu , Vernon Walter Miller , Sergio Reyes , Michael Declan Roll
发明人： Robert H. Bell, JR. , Jose Raul Escalera , Octavian Florin Herescu , Vernon Walter Miller , Sergio Reyes , Michael Declan Roll
IPC分类号： G06F9/50 , G06F9/46 , G06F3/00 , G06F13/00 , G06F13/14
CPC分类号： G06F9/5088 , G06F9/4856
摘要： A processor blade determines whether a selected processing task is to be off-loaded to a storage blade for processing. The selected processing task is off-loaded to the storage blade via a planar bus communication path, in response to determining that the selected processing task is to be off-loaded to the storage blade. The off-loaded selected processing task is processed in the storage blade. The storage blade communicates the results of the processing of the off-loaded selected processing task to the processor blade.
摘要翻译：处理器刀片确定所选择的处理任务是否被卸载到存储刀片以进行处理。响应于确定所选择的处理任务被卸载到存储刀片，所选择的处理任务经由平面总线通信路径被卸载到存储刀片。在存储刀片中处理卸载的所选处理任务。存储刀片将处理卸载的所选处理任务的结果传送到处理器刀片。

19. 发明申请

US20090276191A1 Method And Apparatus For Integrated Circuit Design Model Performance Evaluation Using Basic Block Vector Clustering And Fly-By Vector Clustering 有权
标题翻译：使用基本块矢量聚类和飞行矢量聚类的集成电路设计模型性能评估的方法和装置
公开(公告)号：US20090276191A1
公开(公告)日：2009-11-05
申请号：US12112035
申请日：2008-04-30
申请人： Robert H. Bell, JR. , Wen-Tzer Thomas Chen , Venkat R. Indukuru , Pattabi M. Seshadri , Madhavi G. Valluri
发明人： Robert H. Bell, JR. , Wen-Tzer Thomas Chen , Venkat R. Indukuru , Pattabi M. Seshadri , Madhavi G. Valluri
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G01R31/318357 , G06F11/3428 , G06F11/3457 , G06F11/3664
摘要： A test system or simulator includes an enhanced IC test application sampling software program that executes test application software on a semiconductor die IC design model. The enhanced test application sampling software may include trace, simulation point, CPI error, clustering, instruction budgeting, and other programs. The enhanced test application sampling software generates basic block vectors (BBVs) and fly-by vectors (FBVs) from instruction trace analysis of test application software workloads. The enhanced test application sampling software utilizes the microarchitecture dependent information to generate the FBVs to select representative instruction intervals from the test application software. The enhanced test application sampling software generates a reduced representative test application software program from the BBV and FBV data utilizing a global instruction budgeting analysis method. Designers use the test system with enhanced test application sampling software to evaluate IC design models by using the representative test application software program.
摘要翻译：测试系统或模拟器包括在半导体芯片IC设计模型上执行测试应用软件的增强型IC测试应用采样软件程序。增强的测试应用程序采样软件可能包括跟踪，模拟点，CPI错误，聚类，指令预算和其他程序。增强的测试应用采样软件从测试应用软件工作负载的指令跟踪分析中生成基本块向量（BBV）和飞越向量（FBV）。增强的测试应用采样软件利用微架构依赖信息生成FBV，以从测试应用软件中选择代表性指令间隔。增强的测试应用采样软件利用全球指令预算分析方法，从BBV和FBV数据生成代表性测试应用软件程序。设计人员使用带有增强型测试应用程序采样软件的测试系统，通过使用代表性的测试应用软件程序来评估IC设计模型。

20. 发明申请

US20090164812A1 Dynamic processor reconfiguration for low power without reducing performance based on workload execution characteristics 失效
标题翻译：动态处理器重新配置为低功耗，而不会降低基于工作负载执行特性的性能
公开(公告)号：US20090164812A1
公开(公告)日：2009-06-25
申请号：US11960163
申请日：2007-12-19
申请人： Louis B. Capps, JR. , Robert H. Bell, JR. , Michael J. Shapiro
发明人： Louis B. Capps, JR. , Robert H. Bell, JR. , Michael J. Shapiro
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3243 , Y02D10/152 , Y02D50/20
摘要： A method, system and program are provided for dynamically reconfiguring a pipelined processor to operate with reduced power consumption without reducing existing performance. By monitoring or detecting the performance of individual units or stages in the processor as they execute a given workload, each stage may use high-performance circuitry until such time as a drop in the throughput performance is detected, at which point the stages are reconfigured to use lower-performance circuitry so as to meet the reduced performance throughput requirements using less power. By configuring the processor to back off from high-performance designs to low-performance designs to meet the detected performance characteristics of the executing workload warrant, power dissipation may be optimized.
摘要翻译：提供了一种方法，系统和程序，用于动态重新配置流水线处理器，以降低功耗进行操作，而不会降低现有性能。通过在处理器执行给定工作负载时监视或检测处理器中的各个单元或级的性能，每个级可以使用高性能电路，直到检测到吞吐量性能下降为止，此时将级重新配置为使用低性能电路，以便通过更少的功率来满足降低的性能吞吐量要求。通过将处理器配置为从高性能设计退回到低性能设计，以满足检测到的执行工作量保证的性能特征，可以优化功耗。

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