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11. 发明授权

US07829973B2 N cell height decoupling circuit 有权
标题翻译： N单元高度去耦电路
公开(公告)号：US07829973B2
公开(公告)日：2010-11-09
申请号：US11843768
申请日：2007-08-23
申请人： Richard T. Schultz , Thomas R. O'Brien , Viswanathan Lakshmanan , David M. Ratchkov , Stefan G. Block
发明人： Richard T. Schultz , Thomas R. O'Brien , Viswanathan Lakshmanan , David M. Ratchkov , Stefan G. Block
IPC分类号： H01G4/40
CPC分类号： H01G4/40
摘要： A decoupling circuit disposed between a first rail and a second rail, where a third power rail is disposed between the first and second rails. A resistor having a first electrode and a second electrode is disposed between the first and second rails. Two capacitors are disposed between the first and second rails. The resistor is connected to the third rail and the two capacitors. In this manner, the two capacitors are connected in series with respect to the resistor, and in parallel with respect to one another. A first of the two capacitors is connected to the first rail, and a second of the two capacitors is connected to the second rail. At least one of the resistor and the two capacitors is disposed at least in part beneath the third rail.
摘要翻译：设置在第一轨道和第二轨道之间的去耦电路，其中第三电力轨设置在第一和第二轨道之间。具有第一电极和第二电极的电阻器设置在第一和第二导轨之间。两个电容器设置在第一和第二导轨之间。电阻器连接到第三导轨和两个电容器。以这种方式，两个电容器相对于电阻器串联连接，并且彼此并联。两个电容器中的第一个连接到第一导轨，并且两个电容器中的第二个连接到第二导轨。电阻器和两个电容器中的至少一个至少部分地设置在第三导轨下方。

12. 发明授权

US07829466B2 Methods for fabricating FinFET structures having different channel lengths 有权
标题翻译：制造具有不同沟道长度的FinFET结构的方法
公开(公告)号：US07829466B2
公开(公告)日：2010-11-09
申请号：US12365300
申请日：2009-02-04
申请人： Frank S. Johnson , Richard T. Schultz
发明人： Frank S. Johnson , Richard T. Schultz
IPC分类号： H01L21/311
CPC分类号： H01L21/823431 , H01L29/66795 , H01L29/66818
摘要： Methods for fabricating FinFET structures having gate structures of different gate widths are provided. The methods include the formation of sidewall spacers of different thicknesses to define gate structures of the FinFET structures with different gate widths. The width of a sidewall spacer is defined by the height of the structure about which the sidewall spacer is formed, the thickness of the sidewall spacer material layer from which the spacer is formed, and the etch parameters used to etch the sidewall spacer material layer. By forming structures of varying height, forming the sidewall spacer material layer of varying thickness, or a combination of these, sidewall spacers of varying width can be fabricated and subsequently used as an etch mask so that gate structures of varying widths can be formed simultaneously.
摘要翻译：提供了制造具有不同栅极宽度的栅极结构的FinFET结构的方法。这些方法包括形成不同厚度的侧壁间隔物，以限定具有不同栅极宽度的FinFET结构的栅极结构。侧壁间隔物的宽度由形成侧壁间隔物的结构的高度，形成间隔物的侧壁间隔材料层的厚度和用于蚀刻侧壁间隔物材料层的蚀刻参数限定。通过形成不同高度的结构，形成不同厚度的侧壁间隔物材料层或这些的组合，可以制造不同宽度的侧壁间隔物，并随后用作蚀刻掩模，从而可以同时形成不同宽度的栅极结构。

13. 发明申请

US20100197096A1 METHODS FOR FABRICATING FINFET STRUCTURES HAVING DIFFERENT CHANNEL LENGTHS 有权
标题翻译：用于制作具有不同通道长度的FINFET结构的方法
公开(公告)号：US20100197096A1
公开(公告)日：2010-08-05
申请号：US12365300
申请日：2009-02-04
申请人： Frank S. JOHNSON , Richard T. Schultz
发明人： Frank S. JOHNSON , Richard T. Schultz
IPC分类号： H01L21/336
CPC分类号： H01L21/823431 , H01L29/66795 , H01L29/66818
摘要： Methods for fabricating FinFET structures having gate structures of different gate widths are provided. The methods include the formation of sidewall spacers of different thicknesses to define gate structures of the FinFET structures with different gate widths. The width of a sidewall spacer is defined by the height of the structure about which the sidewall spacer is formed, the thickness of the sidewall spacer material layer from which the spacer is formed, and the etch parameters used to etch the sidewall spacer material layer. By forming structures of varying height, forming the sidewall spacer material layer of varying thickness, or a combination of these, sidewall spacers of varying width can be fabricated and subsequently used as an etch mask so that gate structures of varying widths can be formed simultaneously.
摘要翻译：提供了制造具有不同栅极宽度的栅极结构的FinFET结构的方法。这些方法包括形成不同厚度的侧壁间隔物，以限定具有不同栅极宽度的FinFET结构的栅极结构。侧壁间隔物的宽度由形成侧壁间隔物的结构的高度，形成间隔物的侧壁间隔材料层的厚度和用于蚀刻侧壁间隔物材料层的蚀刻参数限定。通过形成不同高度的结构，形成不同厚度的侧壁间隔物材料层或这些的组合，可以制造不同宽度的侧壁间隔物，并随后用作蚀刻掩模，从而可以同时形成不同宽度的栅极结构。

14. 发明授权

US06625770B1 Method of automatically generating schematic and waveform diagrams for relevant logic cells of a circuit using input signal predictors and transition times 有权
标题翻译：使用输入信号预测器和转换时间自动生成电路相关逻辑单元的原理图和波形图的方法
公开(公告)号：US06625770B1
公开(公告)日：2003-09-23
申请号：US09597433
申请日：2000-06-20
申请人： Richard T. Schultz
发明人： Richard T. Schultz
IPC分类号： G01R3128
CPC分类号： G01R31/318357 , G01R31/31835 , G06F11/261 , G06F17/5022
摘要： Relevant logic cells and waveforms of a circuit are automatically identified, traced and displayed by using conventional simulation, schematic viewing and waveform viewing tools. The input and output waveforms to and from each logic cell and a transition and a transition time point of each waveform are derived. The output waveform and a selected transition time point identify a predictive input waveform and its transition time, which cause the output signal transition at the selected transition time point. The predictive input signal is the output signal of a preceding, predictive logic cell, thereby identifying the preceding predictive logic cell. Repetitions of this procedure are performed with each new identified predictive logic cell to automatically derive a series or cone of logic cells which cause the desired output signal at a selected output signal transition time.
摘要翻译：通过使用传统的仿真，原理图和波形查看工具自动识别，跟踪和显示电路的相关逻辑单元和波形。导出到每个逻辑单元的输入和输出波形以及每个波形的转换和转换时间点。输出波形和所选择的转换时间点识别预测输入波形及其转换时间，这导致所选转换时间点的输出信号转换。预测输入信号是前一预测逻辑单元的输出信号，由此识别先前的预测逻辑单元。对每个新识别的预测逻辑单元执行该过程的重复，以自动导出在所选择的输出信号转换时间引起所需输出信号的逻辑单元的串或锥。

15. 发明授权

US06388486B1 Load sensing, slew rate shaping, output signal pad cell driver circuit and method 有权
标题翻译：负载感测，压摆率整形，输出信号垫单元驱动电路和方法
公开(公告)号：US06388486B1
公开(公告)日：2002-05-14
申请号：US09596568
申请日：2000-06-19
申请人： Richard T. Schultz
发明人： Richard T. Schultz
IPC分类号： H03K512
CPC分类号： H03K17/167 , H03K5/135 , H03K17/164
摘要： The slew rate of a digital logic output signal delivered from an output pad of an integrated circuit is controlled relative to a load connected to the output pad. At least two pluralities of trigger signals at sequentially spaced time intervals are generated, and the time intervals between the first and second trigger signals or the temporal occurrence of the first and second trigger signals in relation to the load connected to the output pad is selected to change the slew rate of the output signal. The timing of the plurality of trigger signals is established in relation to an input signal to which the driver circuit responds and in relation to the change in the output signal with time as influenced by the load connected to the output pad.
摘要翻译：从集成电路的输出焊盘传送的数字逻辑输出信号的转换速率相对于连接到输出焊盘的负载进行控制。以顺序间隔的时间间隔产生至少两个多个触发信号，并且选择第一和第二触发信号之间的时间间隔或相对于连接到输出焊盘的负载的第一和第二触发信号的时间出现被选择为改变输出信号的转换速率。多个触发信号的定时相对于驱动器电路响应的输入信号和与连接到输出焊盘的负载的影响时相对于输出信号随时间的变化而建立。

16. 发明授权

US6111310A Radially-increasing core power bus grid architecture 有权
标题翻译：径向增加的核心电力总线电网架构
公开(公告)号：US6111310A
公开(公告)日：2000-08-29
申请号：US163683
申请日：1998-09-30
申请人： Richard T. Schultz
发明人： Richard T. Schultz
IPC分类号： H01L23/528 , H01L23/52 , H01L23/34 , H01L23/48
CPC分类号： H01L23/5286 , H01L2924/0002
摘要： A power bus grid architecture for an integrated circuit including a plurality of main bars assembled along the perimeter of the grid and a plurality of bus bars assembled within the perimeter of the grid. The bus bars are each composed of a plurality of segments with each segment having a substantially constant width. Each segment on certain bus bars has a different width from the next adjacent segment. The width of a particular segment is determined by the distance of the segment from the nearest main power bar. Because the current flow through the segments nearest to the main power bar tends to be greater than the current flow through the segments further from the main power bar, the segments nearest to the main power bar can be made much wider than the segments furthest from the main power bar without significant deleterious effects to the circuit from voltage drops or electromigration.
摘要翻译：一种用于集成电路的电力总线电网架构，包括沿着电网的周边组装的多个主棒，以及组装在电网的周边内的多个母线。汇流条各自由多个段构成，每个段具有基本恒定的宽度。某些母线上的每个片段与下一个相邻片段的宽度不同。特定片段的宽度由片段与最近的主电源条的距离确定。因为流过最靠近主功率条的段的电流往往大于远离主电源条的电流，所以最靠近主电源条的电流可以比最远离主电源条最远的部分宽得多主电源电压从电压降或电迁移不会对电路产生显着的有害影响。

17. 发明授权

US08563425B2 Selective local interconnect to gate in a self aligned local interconnect process 有权
标题翻译：在自对准局部互连过程中选择性的局部互连到门
公开(公告)号：US08563425B2
公开(公告)日：2013-10-22
申请号：US12475796
申请日：2009-06-01
申请人： Richard T. Schultz
发明人： Richard T. Schultz
IPC分类号： H01L21/4763
CPC分类号： H01L21/76897 , H01L21/76895 , H01L21/823437 , H01L21/823475
摘要： A semiconductor device fabrication process includes forming a gate of a transistor on a semiconductor substrate using a hard mask. The hard mask is selectively removed in one or more selected regions over the gate. The removal of the hard mask in the selected regions allows the gate to be connected to an upper metal layer through at least one insulating layer located substantially over the transistor. Conductive material is deposited in one or more trenches formed through the at least one insulating layer. The conductive material forms a local interconnect to the gate in at least one of the selected regions.
摘要翻译：半导体器件制造工艺包括使用硬掩模在半导体衬底上形成晶体管的栅极。在门上的一个或多个选定区域中选择性地去除硬掩模。在所选择的区域中去除硬掩模允许栅极通过位于晶体管基本上的至少一个绝缘层连接到上金属层。导电材料沉积在通过至少一个绝缘层形成的一个或多个沟槽中。导电材料在所选择的区域中的至少一个中形成与栅极的局部互连。

18. 发明申请

US20120037996A1 SRAM BIT CELL WITH SELF-ALIGNED BIDIRECTIONAL LOCAL INTERCONNECTS 审中-公开
标题翻译：具有自对准双向局部互连的SRAM位单元
公开(公告)号：US20120037996A1
公开(公告)日：2012-02-16
申请号：US13280848
申请日：2011-10-25
申请人： Richard T. Schultz , Donald R. Weiss
发明人： Richard T. Schultz , Donald R. Weiss
IPC分类号： H01L27/11
CPC分类号： H01L21/76895 , H01L21/845 , H01L27/11 , H01L27/1104 , H01L27/1211 , H01L2924/0002 , H01L2924/00
摘要： Improved SRAMs are formed with significantly reduced local interconnect to gate shorts, by a technique providing bidirectional, self-aligned local interconnects, employing a gate hard mask over portions of the gates not connected to the local interconnects. Embodiments include forming a gate hard mask over gates, forming bidirectional trenches overlying portions of the gate electrodes and active silicon regions, etching the hard mask layer to expose regions of the gate electrodes that are to connect to local interconnects, and filling the trenches with conductive material to form self-aligned local interconnects.
摘要翻译：通过提供双向，自对准局部互连的技术，通过在未连接到局部互连的栅极的部分上采用栅极硬掩模，技术来形成改进的SRAM，从而显着减少与栅极短路的局部互连。实施例包括在栅极上形成栅极硬掩模，形成覆盖栅极电极和有源硅区域的部分的双向沟槽，蚀刻硬掩模层以暴露栅极电极连接到局部互连的区域，以及用导电材料以形成自对准局部互连。

19. 发明授权

US07960287B2 Methods for fabricating FinFET structures having different channel lengths 有权
标题翻译：制造具有不同沟道长度的FinFET结构的方法
公开(公告)号：US07960287B2
公开(公告)日：2011-06-14
申请号：US12891365
申请日：2010-09-27
申请人： Frank Scott Johnson , Richard T. Schultz
发明人： Frank Scott Johnson , Richard T. Schultz
IPC分类号： H01L21/311
CPC分类号： H01L21/823431 , H01L29/66795 , H01L29/66818
摘要： Methods for fabricating FinFET structures having gate structures of different gate widths are provided. The methods include the formation of sidewall spacers of different thicknesses to define gate structures of the FinFET structures with different gate widths. The width of a sidewall spacer is defined by the height of the structure about which the sidewall spacer is formed, the thickness of the sidewall spacer material layer from which the spacer is formed, and the etch parameters used to etch the sidewall spacer material layer. By forming structures of varying height, forming the sidewall spacer material layer of varying thickness, or a combination of these, sidewall spacers of varying width can be fabricated and subsequently used as an etch mask so that gate structures of varying widths can be formed simultaneously.
摘要翻译：提供了制造具有不同栅极宽度的栅极结构的FinFET结构的方法。这些方法包括形成不同厚度的侧壁间隔物，以限定具有不同栅极宽度的FinFET结构的栅极结构。侧壁间隔物的宽度由形成侧壁间隔物的结构的高度，形成间隔物的侧壁间隔材料层的厚度和用于蚀刻侧壁间隔物材料层的蚀刻参数限定。通过形成不同高度的结构，形成不同厚度的侧壁间隔物材料层或这些的组合，可以制造不同宽度的侧壁间隔物，并随后用作蚀刻掩模，从而可以同时形成不同宽度的栅极结构。

20. 发明授权

US06653726B1 Power redistribution bus for a wire bonded integrated circuit 有权
标题翻译：电线再分配总线，用于导线接合集成电路
公开(公告)号：US06653726B1
公开(公告)日：2003-11-25
申请号：US09948190
申请日：2001-09-07
申请人： Richard T. Schultz , Roger D. Weir
发明人： Richard T. Schultz , Roger D. Weir
IPC分类号： H01L3252
CPC分类号： H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： The subject matter described herein involves a wire bonded integrated circuit (IC) that includes a power distribution grid, or power redistribution bus, within a single layer, e.g. the topmost metallization layer, of the IC chip. Electrical conductors in the power distribution grid are generally L-shaped. Thus, the electrical conductors are arranged generally in symmetrical quadrants within which the electrical conductors extend from one side edge of the IC chip to a generally right-angled corner and then to a second side edge that is adjacent to the first side edge.
摘要翻译：本文所述的主题涉及包括在单层内的配电网格或功率再分配总线的引线键合集成电路（IC），例如。 IC芯片的最顶层金属化层。配电网中的电气导体通常为L形。因此，电导体大致布置在对称象限中，电导体从IC芯片的一个侧边缘延伸到大致直角的角部，然后延伸到与第一侧边缘相邻的第二侧边缘。

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