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11. 发明授权

US06938138B2 Method and apparatus for managing access to memory 有权
标题翻译：用于管理存储器访问的方法和装置
公开(公告)号：US06938138B2
公开(公告)日：2005-08-30
申请号：US09758788
申请日：2001-01-11
申请人： Bruce Leroy Beukema , David Craddock , Ronald Edward Fuhs , Thomas Anthony Gregg , Gregory Francis Pfister , Renato John Recio , Steven L. Rogers
发明人： Bruce Leroy Beukema , David Craddock , Ronald Edward Fuhs , Thomas Anthony Gregg , Gregory Francis Pfister , Renato John Recio , Steven L. Rogers
IPC分类号： G06F12/14 , G06F15/16
CPC分类号： G06F12/145
摘要： A method and apparatus for accessing a memory. Access rights for a memory operation are verified using a first data structure in response to receiving a request to perform the operation, wherein the request includes a virtual address for the operation. Responsive to access rights being verified for the memory operation, the virtual address translated into a real address using a second data structure.
摘要翻译：一种访问存储器的方法和装置。响应于接收到执行操作的请求，使用第一数据结构来验证存储器操作的访问权限，其中所述请求包括用于操作的虚拟地址。响应于对存储器操作进行验证的访问权限，虚拟地址使用第二数据结构转换为实际地址。

12. 发明授权

US06691217B2 Method and apparatus for associating memory windows with memory regions in a data storage system 失效
标题翻译：用于将存储器窗口与数据存储系统中的存储器区域相关联的方法和装置
公开(公告)号：US06691217B2
公开(公告)日：2004-02-10
申请号：US09864116
申请日：2001-05-24
申请人： Bruce Leroy Beukema , David F. Craddock , Thomas Anthony Gregg , Renato John Recio
发明人： Bruce Leroy Beukema , David F. Craddock , Thomas Anthony Gregg , Renato John Recio
IPC分类号： G06F1200
CPC分类号： G06F12/0261 , G06F12/1081 , Y10S707/99953 , Y10S707/99956
摘要： A method, program and system for associating memory windows with memory regions in an infiniband data storage system are provided. The invention comprises registering a Memory Region, wherein the Memory Region is a set of virtually contiguous memory addresses defined by a virtual address and length. The system then establishes and maintains a Window Reference Count (WRC) for the Memory Region, which tracks the number of Memory Windows which are bound to the Memory Region. When the system binds a Memory Window to the Memory Region, the value of the WRC is incremented. When a Memory Window is unbound from the Memory Region, the value of the WRC is decremented. If no Memory Windows are bound to the Memory Region, the value of the WRC is zero. The Memory Region is not deregistered unless the value of the WRC equals zero.
摘要翻译：提供了一种用于将存储器窗口与无限数据存储系统中的存储器区域相关联的方法，程序和系统。本发明包括登记存储器区域，其中存储器区域是由虚拟地址和长度定义的一组虚拟连续的存储器地址。然后，系统建立并维护用于内存区域的窗口引用计数（WRC），该区域跟踪绑定到内存区域的内存窗口的数量。当系统将内存窗口绑定到内存区域时，WRC的值将增加。当存储器窗口从存储器区域中取消绑定时，WRC的值递减。如果没有内存Windows绑定到内存区域，则WRC的值为零。除非WRC的值等于零，否则内存区域不会被注销。

13. 发明授权

US06748499B2 Sharing memory tables between host channel adapters 有权
标题翻译：在主机通道适配器之间共享内存表
公开(公告)号：US06748499B2
公开(公告)日：2004-06-08
申请号：US09998403
申请日：2001-11-15
申请人： Bruce Leroy Beukema , David F. Craddock , Thomas Anthony Gregg , Renato John Recio
发明人： Bruce Leroy Beukema , David F. Craddock , Thomas Anthony Gregg , Renato John Recio
IPC分类号： G06F1214
CPC分类号： G06F12/1081 , G06F12/1475
摘要： A method, computer program product, and data processing system for sharing memory protection tables and address translation tables among multiple Host Channel Adapters are disclosed. The protection and address translation tables for a shared memory region are written in memory of the host. The Host Channel Adapters are registered with the memory region so that each adapter stores an address pointer to the tables. In this way, the tables need not be duplicated for each adapter.
摘要翻译：公开了一种用于在多个主机通道适配器之间共享存储器保护表和地址转换表的方法，计算机程序产品和数据处理系统。共享存储器区域的保护和地址转换表被写入主机的存储器中。主机通道适配器已在内存区域注册，以便每个适配器都存储一个地址指针给表。这样，每个适配器不需要重复表。

14. 发明授权

US06275876B1 Specifying wrap register for storing memory address to store completion status of instruction to external device 失效
标题翻译：指定用于存储存储器地址的包装寄存器，以将指令的完成状态存储到外部设备
公开(公告)号：US06275876B1
公开(公告)日：2001-08-14
申请号：US09316243
申请日：1999-05-21
申请人： Kenneth Michael Valk , Thomas Rembert Sand , Ronald Edward Fuhs , Gregory Michael Nordstrom , Bruce Leroy Beukema
发明人： Kenneth Michael Valk , Thomas Rembert Sand , Ronald Edward Fuhs , Gregory Michael Nordstrom , Bruce Leroy Beukema
IPC分类号： G06F1312
CPC分类号： G06F13/126
摘要： A computing system includes a processing system, at least a first register, and a control system. The processing system generates a first instruction set and a first address for storing a first completion status for the first instruction set. The first register receives the first address from the processing system. The control system communicates the first instruction set received from the processing system to an external device. The control system receives the first completion status from the external device, accesses the first register to determine the first address for the first instruction set, and stores the first completion status in the determined first address.
摘要翻译：计算系统包括处理系统，至少第一寄存器和控制系统。处理系统产生第一指令集和第一地址，用于存储第一指令集的第一完成状态。第一个寄存器从处理系统接收第一个地址。控制系统将从处理系统接收的第一指令集传送到外部设备。控制系统从外部设备接收第一完成状态，访问第一寄存器以确定第一指令集的第一地址，并将第一完成状态存储在所确定的第一地址中。

15. 发明授权

US06529991B1 Ordering mechanism, ordering method and computer program product for implementing PCI peer to functions 失效
标题翻译：用于实现PCI对等功能的订购机制，订购方法和计算机程序产品
公开(公告)号：US06529991B1
公开(公告)日：2003-03-04
申请号：US09310797
申请日：1999-05-12
申请人： Bruce Leroy Beukema , Ronald Edward Fuhs , Kenneth Claude Hinz
发明人： Bruce Leroy Beukema , Ronald Edward Fuhs , Kenneth Claude Hinz
IPC分类号： G06F1320
CPC分类号： G06F13/423 , G06F13/1621
摘要： An ordering mechanism, ordering method and computer program product are provided for implementing PCI local bus (PCI) peer to peer functions. When a read command is received, checking for available resource is performed. Responsive to not identifying available resource, a retry read command is sent. Responsive to sending the read command; checking for the retry read received command is provided. Responsive to identifying the retry read received command, the read command is resent.
摘要翻译：提供了一种用于实现PCI局部总线（PCI）对等功能的排序机制，排序方法和计算机程序产品。当接收到读命令时，执行检查可用资源。响应于不识别可用资源，发送重试读取命令。响应发送读命令; 提供检查重试读取命令。响应于识别重试读取命令，读取命令被重新发送。

16. 发明授权

US06185642B2 Bus for high frequency operation with backward compatibility and hot-plug ability 失效
标题翻译：高性能PCI总线，用于高频操作，具有向后兼容性和热插拔能力
公开(公告)号：US06185642B2
公开(公告)日：2001-02-06
申请号：US09116058
申请日：1998-07-15
申请人： Bruce Leroy Beukema , Ronald Edward Fuhs , Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
发明人： Bruce Leroy Beukema , Ronald Edward Fuhs , Richard Allen Kelley , Danny Marvin Neal , Steven Mark Thurber
IPC分类号： G06F1300
CPC分类号： G06F13/4081
摘要： A peripheral interconnect for a computer system comprising a bridge, a peripheral bus, and a peripheral device, wherein at least one of these components is adapted to selectively operate in either a high performance mode or a low performance mode, the high performance mode using a first operating speed and a first protocol, and the low performance mode using a second operating speed which is lower than said first operating speed, and a second protocol which is different from the first protocol. The disclosed embodiment provides a high performance mode with a 100 MHz speed and a protocol that disallows pacing, and a low performance mode that uses a 66 MHz or 33 MHz speed and a standard PCI protocol that allows pacing. The high performance operating speed can be twice the low performance operating speed, by doubling the clock frequency and clocking data on only one clock edge, or by clocking data on both a rising edge and a falling edge of a clock signal while operating at the lower clock frequency. High performance adapters can provide split transaction capability, with a high performance bridge having the ability to support split transactions or alias split transactions to delayed transactions. Backward compatibility may also be provided for optional features such as hot-pluggability.
摘要翻译：一种用于包括桥接器，外围总线和外围设备的计算机系统的外设互连，其中这些组件中的至少一个适于选择性地以高性能模式或低性能模式操作，高性能模式使用第一操作速度和第一协议，以及使用低于所述第一操作速度的第二操作速度的低性能模式，以及不同于第一协议的第二协议。所公开的实施例提供具有100MHz速度的高性能模式和不允许起搏的协议，以及使用66MHz或33MHz速度的低性能模式和允许起搏的标准PCI协议。高性能运行速度可以是低性能运行速度的两倍，通过在一个时钟沿将时钟频率和时钟数据加倍，或者在时钟信号的上升沿和下降沿同时处理数据，同时在较低的时钟时钟频率。高性能适配器可以提供拆分事务功能，具有支持拆分事务或别名拆分事务延迟事务的高性能网桥。也可以向后兼容性提供可选功能，如热插拔。

17. 发明授权

US06920519B1 System and method for supporting access to multiple I/O hub nodes in a host bridge 有权
标题翻译：用于支持访问主桥中的多个I / O中枢节点的系统和方法
公开(公告)号：US06920519B1
公开(公告)日：2005-07-19
申请号：US09569059
申请日：2000-05-10
申请人： Bruce Leroy Beukema , Timothy Carl Bronson , Ronald Edward Fuhs , Glenn David Gilda , Anthony J Bybell , Stefan Peter Jackowski , William Garrett Verdoorn, Jr. , Phillip G Williams
发明人： Bruce Leroy Beukema , Timothy Carl Bronson , Ronald Edward Fuhs , Glenn David Gilda , Anthony J Bybell , Stefan Peter Jackowski , William Garrett Verdoorn, Jr. , Phillip G Williams
IPC分类号： G06F3/00 , G06F12/00 , G06F12/02 , G06F12/10 , G06F13/36 , G06F13/40
CPC分类号： G06F13/404 , G06F12/0284 , G06F12/1027 , G06F2212/682
摘要： Dynamic routing of data to multiple processor complexes. PCI address space is subdivided among a plurality of processor complexes. Translation table entries at each processor complex determine which processor complex is to receive a DMA transfer, thereby enabling routing of DMA data to one I/O hub node while accessing translation table entries at another I/O hub node. Further, interrupt requests may be dynamically routed to multiple processor complexes.
摘要翻译：将数据动态路由到多个处理器复合体。 PCI地址空间被细分为多个处理器复合体。每个处理器复合体处的转换表条目确定哪个处理器复合体将接收DMA传输，从而在访问另一个I / O集线器节点处的转换表条目时，使DMA数据能够路由到一个I / O集线器节点。此外，中断请求可以被动态地路由到多个处理器复合体。

18. 发明授权

US06785759B1 System and method for sharing I/O address translation caching across multiple host bridges 失效
标题翻译：在多个主机桥上共享I / O地址转换缓存的系统和方法
公开(公告)号：US06785759B1
公开(公告)日：2004-08-31
申请号：US09569574
申请日：2000-05-10
申请人： Bruce Leroy Beukema , Timothy Carl Bronson , Ronald Edward Fuhs , Glenn David Gilda
发明人： Bruce Leroy Beukema , Timothy Carl Bronson , Ronald Edward Fuhs , Glenn David Gilda
IPC分类号： G06F100
CPC分类号： G06F12/0292 , G06F12/1027 , G06F2212/303 , G06F2213/0038
摘要： A processor system includes an I/O bus to host bridge in which I/O address translation elements are shared across multiple I/O bus bridges. A TCE manager is provided for retaining in cache a TCE entry associated with a discarded channel for association with a new channel responsive to a subsequent read request for a memory page referenced by the TCE entry.
摘要翻译：处理器系统包括一个主机桥的I / O总线，其中I / O地址转换元件在多个I / O总线桥上共享。提供TCE管理器，用于在缓存中保留与被丢弃的信道相关联的TTS条目，用于响应于对由TCE条目引用的存储器页面的后续读取请求与新信道相关联。

19. 发明授权

US07149220B2 System, method, and product for managing data transfers in a network 有权
公开(公告)号：US07149220B2
公开(公告)日：2006-12-12
申请号：US10132456
申请日：2002-04-25
申请人： Bruce Leroy Beukema , Thomas Anthony Gregg , Danny Marvin Neal , Renato John Recio
发明人： Bruce Leroy Beukema , Thomas Anthony Gregg , Danny Marvin Neal , Renato John Recio
IPC分类号： H04L12/56
CPC分类号： H04L29/06 , H04L49/90 , H04L69/326
摘要： A method, system, and product in a data processing system are disclosed for managing data transmitted from a first end node to a second end node included in the data processing system. A logical connection is established between the first end node and the second end node prior to transmitting data between the end nodes. An instance number is associated with this particular logical connection. The instance number is included in each packet transmitted between the end nodes while this logical connection remains established. The instance number remains constant during this logical connection. The instance number is altered, such as by incrementing it, each time a logical connection between these end nodes is reestablished. Thus, each packet is associated with a particular instance of the logical connection. When a packet is received, the instance number included in the packet may be used to determine whether the packet is a stale packet transmitted during a previous logical connection between these end nodes.

20. 发明授权

US6128674A Method of minimizing host CPU utilization in driving an adapter by residing in system memory a command/status block a soft interrupt block and a status block queue 失效
标题翻译：通过驻留在系统存储器中来最小化驱动适配器的主机CPU利用率的方法，命令/状态块软中断块和状态块队列
公开(公告)号：US6128674A
公开(公告)日：2000-10-03
申请号：US908888
申请日：1997-08-08
申请人： Bruce Leroy Beukema , Patrick Allen Buckland , Wen-Tzer Thomas Chen , David Arlen Elko , Ian David Judd , Renato John Recio
发明人： Bruce Leroy Beukema , Patrick Allen Buckland , Wen-Tzer Thomas Chen , David Arlen Elko , Ian David Judd , Renato John Recio
IPC分类号： G06F3/00 , G06F9/06 , G06F12/08 , G06F13/28
CPC分类号： G06F12/0835
摘要： The system I/O interface and its data structure are designed to minimize the host CPU utilization in driving an adapter. The interface is also designed to reduce the system interference in processing I/O requests. To eliminate the need of using PIO instructions, the command/status blocks for exchanging messages between the system and the adapter reside in the system memory. The data structure is designed to avoid "share write" entries in order to further minimize the overhead of maintaining each coherency when updating an entry in the cache either concurrently or sequentially by both adapter and system CPU. Further, the data structure of the control and status blocks is resided in the system memory. The system CPU uses STORE instruction to prepare control blocks and LOAD instruction to read from completion status blocks; while the adapter will rely on its DMA engine to move data to/from system memory in accessing control/status blocks.
摘要翻译：系统I / O接口及其数据结构旨在最大限度地减少驱动适配器时的主机CPU利用率。该接口还旨在减少处理I / O请求时的系统干扰。为了不需要使用PIO指令，系统和适配器之间交换消息的命令/状态块驻留在系统内存中。数据结构旨在避免“共享写入”条目，以便在适配器和系统CPU同时或顺序更新缓存中的条目时进一步最小化维护每个一致性的开销。此外，控制和状态块的数据结构驻留在系统存储器中。系统CPU使用STORE指令准备控制块和LOAD指令，从完成状态块读取; 而适配器将依靠其DMA引擎在访问控制/状态块时将数据移入/移出系统内存。

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