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11. 发明授权

US06518072B1 Deposited screen oxide for reducing gate edge lifting 有权
标题翻译：沉积的屏幕氧化物，用于减少门边缘提升
公开(公告)号：US06518072B1
公开(公告)日：2003-02-11
申请号：US09476906
申请日：2000-01-03
申请人： Carl Robert Huster , Daniel Sobek , Timothy Thurgate , Sameer S. Haddad
发明人： Carl Robert Huster , Daniel Sobek , Timothy Thurgate , Sameer S. Haddad
IPC分类号： H01L218247
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324
摘要： A method of manufacturing a flash memory device with a controllable amount of gate edge lifting including etching the ends of the tunnel oxide forming a cavity at each end of the tunnel oxide and anisotropically depositing and etching an oxide to form spacers on the sides of the gate stack. The spacers have a predetermined thickness that controls the amount of gate edge lifting. The predetermined thickness is determined during a characterization procedure that can be a computer modeling procedure or it can be determined empirically.
摘要翻译：一种制造具有可控量的栅极边缘提升的闪速存储器件的方法，包括蚀刻隧道氧化物的端部，在隧道氧化物的每一端处形成空腔，并各向异性沉积和蚀刻氧化物以在栅极的侧面上形成间隔物堆栈间隔物具有控制浇口边缘提升量的预定厚度。在可以是计算机建模过程的表征过程中确定预定厚度，或者可以凭经验确定。

12. 发明授权

US06268624B1 Method for inhibiting tunnel oxide growth at the edges of a floating gate during semiconductor device processing 有权
标题翻译：在半导体器件处理期间抑制浮栅的边缘处的隧道氧化物生长的方法
公开(公告)号：US06268624B1
公开(公告)日：2001-07-31
申请号：US09364982
申请日：1999-07-31
申请人： Daniel Sobek , Timothy Thurgate , Carl R. Huster , Tuan Duc Pham , Mark T. Ramsbey , Sameer S. Haddad
发明人： Daniel Sobek , Timothy Thurgate , Carl R. Huster , Tuan Duc Pham , Mark T. Ramsbey , Sameer S. Haddad
IPC分类号： H01L218247
CPC分类号： H01L21/28273
摘要： A method for making a ULSI MOSFET chip includes forming a MOSFET gate stack on a substrate, with a tunnel oxide layer being sandwiched between the gate stack and substrate. To prevent thickening of the tunnel oxide layer into a “gate edge lifting” profile during subsequent oxidation-causing steps, at least one protective barrier film is deposited or grown over the gate stack and tunnel oxide layer immediately after gate stack formation. Then, subsequent steps, including forming source and drain regions for the gate stack, can be undertaken without causing thickening of the tunnel oxide layer.
摘要翻译：制造ULSI MOSFET芯片的方法包括在衬底上形成MOSFET栅极叠层，其中隧道氧化层夹在栅叠层和衬底之间。为了防止隧道氧化物层在随后的氧化引发步骤期间增厚到“栅极边缘提升”轮廓中，在栅极堆叠形成之后立即沉积或生长至少一个保护性阻挡膜在栅极堆叠和隧道氧化物层上。然后，可以进行包括形成栅极堆叠的源极和漏极区域的后续步骤，而不会导致隧道氧化物层的增厚。

13. 发明授权

US06252803B1 Automatic program disturb with intelligent soft programming for flash cells 有权
标题翻译：自动程序干扰与闪存单元的智能软编程
公开(公告)号：US06252803B1
公开(公告)日：2001-06-26
申请号：US09692881
申请日：2000-10-23
申请人： Richard Fastow , Sameer S. Haddad , Lee E. Cleveland , Chi Chang
发明人： Richard Fastow , Sameer S. Haddad , Lee E. Cleveland , Chi Chang
IPC分类号： G11C1616
CPC分类号： G11C16/16
摘要： A method of erasing a flash electrically-erasable programmable read-only memory (EEPROM) device is provided which includes a plurality of memory cells. An erase pulse is applied to the plurality of memory cells. The plurality of memory cells is overerase verified and an overerase correction pulse is applied to the bitline to which the overerased memory cell is attached. This cycle is repeated until all cells verify as not being overerased. The plurality of memory cells is erase verified and another erase pulse is applied to the memory cells if there are undererased memory cells and the memory cells are again erase verified. This cycle is repeated until all cells verify as not being undererased. After erase verify is completed, the plurality of memory cells is soft program verified and a soft programming pulse is applied to the those memory cells in the plurality of memory cells which have a threshold voltage below a pre-defined minimum value. This cycle is repeated until all of those memory cells in the plurality of memory cells which have a threshold voltage below the pre-defined minimum value are brought above the pre-defined minimum value. The erase method is considered to be finished when there are no memory cells in the plurality of memory cells which have a threshold voltage below the pre-defined minimum value.
摘要翻译：提供擦除闪存电可擦除可编程只读存储器（EEPROM）设备的方法，其包括多个存储器单元。擦除脉冲被施加到多个存储单元。多个存储器单元被过度验证，并且过高修正脉冲被施加到被过度存储的存储单元附着的位线。重复此循环，直到所有的单元格都被验证为不被过高。多个存储器单元被擦除验证，并且如果存在未存储的存储器单元并且存储器单元再次被擦除验证，则另一个擦除脉冲被施加到存储器单元。重复此循环，直到所有单元格都被验证为不被忽略。在擦除验证完成之后，多个存储器单元被软件程序验证，并且将软编程脉冲施加到具有低于预定义最小值的阈值电压的多个存储单元中的那些存储单元。重复该循环，直到具有低于预定义最小值的阈值电压的多个存储器单元中的所有那些存储器单元高于预定义的最小值。当多个存储单元中没有存储单元的阈值电压低于预先定义的最小值时，擦除方法被认为是完成的。

14. 发明授权

US06400608B1 Accurate verify apparatus and method for NOR flash memory cells in the presence of high column leakage 有权
标题翻译：在存在高柱泄漏的情况下，NOR闪存单元的精确验证装置和方法
公开(公告)号：US06400608B1
公开(公告)日：2002-06-04
申请号：US09842288
申请日：2001-04-25
申请人： Richard Fastow , Sameer S. Haddad , Lee E. Cleveland
发明人： Richard Fastow , Sameer S. Haddad , Lee E. Cleveland
IPC分类号： G11C1134
CPC分类号： G11C16/3422 , G11C16/344 , G11C16/3445
摘要： A technique is provided for reducing column leakage in a flash EEPROM device during an erase verification process, thereby preventing false verifies. The technique has application in NOR arrays or other types of arrays in which a number of cells are connected in parallel. The technique operates by reducing the leakage of the unselected cells in parallel to the selected cell being verified, thereby preventing false verifies. The technique can also be used in conjunction with other techniques for reducing column leakage, such as soft programming, automatic programming disturb erase (APDE), or various other Vth compacting schemes.
摘要翻译：提供了一种在擦除验证过程中减少闪存EEPROM器件中的列泄漏的技术，从而防止虚假验证。该技术在NOR阵列或其他类型的阵列中的应用，其中多个单元并联连接。该技术通过减少未被选择的小区的泄漏与所验证的所选择的小区并行，从而防止虚假验证来进行操作。该技术还可以与减少列泄漏的其他技术结合使用，例如软编程，自动编程干扰擦除（APDE）或各种其他Vth压缩方案。

15. 发明授权

US06294430B1 Nitridization of the pre-ddi screen oxide 有权
标题翻译： ddi屏幕氧化物的氮化
公开(公告)号：US06294430B1
公开(公告)日：2001-09-25
申请号：US09495213
申请日：2000-01-31
申请人： Richard Fastow , Sameer S. Haddad , Daniel Sobek
发明人： Richard Fastow , Sameer S. Haddad , Daniel Sobek
IPC分类号： H01L21336
CPC分类号： H01L29/66825 , H01L21/28273 , H01L21/3144 , H01L29/511 , H01L29/7883 , Y10S438/923
摘要： A flash memory device and a method of manufacturing the flash memory device having high reliability in which a gate stack is formed on a tunnel oxide formed on a substrate and a layer of oxide is formed on the surfaces of the gate stack and exposed surfaces of the substrate. Nitrogen is diffused into the layer of oxide.
摘要翻译：闪存器件和制造具有高可靠性的闪速存储器件的方法，其中栅极堆叠形成在形成在衬底上的隧道氧化物上，并且氧化物层形成在栅极堆叠的表面上，基质。氮气扩散到氧化物层中。

16. 发明授权

US06172914B2 Concurrent erase verify scheme for flash memory applications 有权
标题翻译： Flash存储器应用程序的并发擦除验证方案
公开(公告)号：US06172914B2
公开(公告)日：2001-01-09
申请号：US09404078
申请日：1999-09-23
申请人： Sameer S. Haddad , Colin Bill , Michael Van BusKirk
发明人： Sameer S. Haddad , Colin Bill , Michael Van BusKirk
IPC分类号： G11C1604
CPC分类号： G11C16/3472 , G11C16/3468
摘要： A method for sensing the state of erasure of a flash (EEPROM) memory device. In one embodiment, the source voltage during erase is monitored and compared to a value determined during a characterization procedure. In a second embodiment, the rate of change of the source voltage during erase is determined and compared to a value determined during a characterization procedure. The characterization procedure correlates state of erasure with source voltages and slopes of the rate of change of source voltage versus time curve for the memory cells. The determination of the source voltage and the determination of the rate of change of the source voltage and the associated state of erasure allows modification of the erase procedure.
摘要翻译：一种用于检测闪存（EEPROM）存储器件擦除状态的方法。在一个实施例中，监视擦除期间的源电压并将其与在表征过程中确定的值进行比较。在第二实施例中，确定擦除期间的源电压的变化率并将其与表征过程中确定的值进行比较。表征过程将擦除状态与源电压和存储器单元的源电压与时间曲线的变化率的斜率相关联。源电压的确定和源电压的变化率的确定以及相关的擦除状态允许修改擦除过程。

17. 发明授权

US5790456A Multiple bits-per-cell flash EEPROM memory cells with wide program and erase V.sub.t window 失效
标题翻译：多个位单元闪存EEPROM存储单元，具有宽的程序和擦除Vt窗口
公开(公告)号：US5790456A
公开(公告)日：1998-08-04
申请号：US853185
申请日：1997-05-09
申请人： Sameer S. Haddad
发明人： Sameer S. Haddad
IPC分类号： G11C11/56 , G11C16/10 , G11C16/04
CPC分类号： G11C16/3427 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C16/10
摘要： There is provided an improved method for performing channel hot-carrier programming in an array of multiple bits-per-cell Flash EEPROM memory cells in a NOR memory architecture so as to eliminate program disturb during a programming operation. The array has a plurality of memory cells arranged in rows of word lines and columns of bit lines intersecting the rows of word lines. A programming current source is connected to the source of selected memory cells that are to be programmed in the corresponding columns of bit lines. A programming gate voltage is applied to control gates of the selected memory cells, and a programming drain voltage is applied simultaneously to the common array ground line connected to the drains of all of the memory cells. Further, a relatively low voltage is applied simultaneously to all of the control gates of non-selected memory cells in the array which are not to be programmed during the programming operation so as to eliminate the program disturb.
摘要翻译：提供了一种用于在NOR存储器架构中在多个每单元闪存EEPROM存储器单元的阵列中执行通道热载波编程的改进方法，以便在编程操作期间消除程序干扰。该阵列具有排列成字线行和与字线行相交的位线列的多个存储单元。编程电流源连接到要在相应列的位线中编程的所选存储单元的源。将编程栅极电压施加到所选择的存储单元的控制栅极，并且将编程漏极电压同时施加到连接到所有存储单元的漏极的公共阵列地线。此外，相对较低的电压同时施加到在编程操作期间不被编程的阵列中未选择的存储器单元的所有控制栅极，以消除编程干扰。

18. 发明授权

US5712815A Multiple bits per-cell flash EEPROM capable of concurrently programming and verifying memory cells and reference cells 失效
标题翻译：多位每单元闪存EEPROM能够同时编程和验证存储单元和参考单元
公开(公告)号：US5712815A
公开(公告)日：1998-01-27
申请号：US635995
申请日：1996-04-22
申请人： Colin S. Bill , Sameer S. Haddad
发明人： Colin S. Bill , Sameer S. Haddad
IPC分类号： G11C11/56 , G11C16/34 , G11C16/06
CPC分类号： G11C16/3486 , G11C11/5621 , G11C11/5628 , G11C16/3468 , G11C16/3481 , G11C2211/5621 , G11C2211/5622 , G11C2211/5624 , G11C2211/5642 , G11C2211/5645 , G11C2216/14
摘要： An improved programming structure for performing a program operation in an array of multiple bits-per-cell flash EEPROM memory cells is provided. A memory core array (12) includes a plurality of memory cells and a reference cell array (22) having a plurality of reference core cells which are selected together with a selected memory core cell. A precharge circuit (36a) is used to precharge all of the array bit lines and the reference bit lines to a predetermined potential prior to a program operation. A reference generator circuit (134) is used for selectively generating one of a plurality of target memory core cell bit line program-verify voltages, each one corresponding to one of a plurality of programmable memory states. A switching circuit (P1,N1) is used to selectively connect a program current source to the selected certain ones of the columns of array bit lines containing the selected memory core cells which are to be programmed. A sensing logic circuit (26,27) continuously compares a potential on one of the selected bit lines and one of the plurality of target program-verify voltages. The sensing logic circuit generates a logic signal which is switched to a low logic level when the potential on the selected bit line falls below the selected one of the plurality of target program-verify voltages. The switching circuit is responsive to the low logic level for disconnecting the program current source so as to inhibit further programming of the selected memory core cells.
摘要翻译：提供了一种改进的编程结构，用于执行多个比特单元闪存EEPROM存储单元阵列中的程序操作。存储器核心阵列（12）包括多个存储器单元和具有多个参考核心单元的参考单元阵列（22），所述参考单元阵列与选定的存储器核心单元一起选择。预充电电路（36a）用于在编程操作之前将所有阵列位线和参考位线预充电至预定电位。参考发生器电路（134）用于选择性地产生多个目标存储器核心单元位线程序验证电压中的一个，每一个对应于多个可编程存储器状态之一。切换电路（P1，N1）用于选择性地将程序电流源连接到包含要编程的所选择的存储器核心单元的阵列位线列中选定的某些列。感测逻辑电路（26,27）连续地比较所选位线之一上的电位和多个目标程序验证电压中的一个。感测逻辑电路产生逻辑信号，当所选位线上的电位低于多个目标程序验证电压中选定的一个时，逻辑信号被切换到低逻辑电平。开关电路响应于低逻辑电平以断开程序电流源，从而禁止进一步编程所选择的存储器核心单元。

19. 发明授权

US5708588A Flash EEPROM memory with improved discharged speed using substrate bias and method therefor 失效
标题翻译：闪存EEPROM存储器，使用衬底偏置改善放电速度及其方法
公开(公告)号：US5708588A
公开(公告)日：1998-01-13
申请号：US464024
申请日：1995-06-05
申请人： Sameer S. Haddad , Hao Fang
发明人： Sameer S. Haddad , Hao Fang
IPC分类号： G11C16/14 , H01L29/788 , G06F15/00 , G11C11/40
CPC分类号： H01L29/7885 , G11C16/14 , Y10S438/972
摘要： A floating gate cell memory device, such as an EPROM or flash EEPROM, with improved discharge speed. A negative bias is applied to the effective substrate during discharge. The negative bias increases the electric field near the junction, thereby increasing the number of hot holes which can be injected to the floating gate, improving discharge speed.
摘要翻译：具有改善的放电速度的浮动栅极单元存储器件，例如EPROM或快闪EEPROM。在放电期间，对有效衬底施加负偏压。负偏压增加了接点附近的电场，从而增加了可以注入到浮动栅极的热孔数量，从而提高了放电速度。

20. 发明授权

US06862221B1 Memory device having a thin top dielectric and method of erasing same 有权
标题翻译：具有薄顶电介质的存储器件及其擦除方法
公开(公告)号：US06862221B1
公开(公告)日：2005-03-01
申请号：US10459102
申请日：2003-06-11
申请人： Ashot Melik-Martirosian , Mark W. Randolph , Sameer S. Haddad
发明人： Ashot Melik-Martirosian , Mark W. Randolph , Sameer S. Haddad
IPC分类号： G11C16/04 , H01L21/28 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L21/28282 , G11C16/0475 , H01L29/42324 , H01L29/7887 , H01L29/7923
摘要： A non-volatile memory device includes a semiconductor substrate and a source and drain within the substrate. A dielectric stack is formed over the substrate. The dielectric stack includes a thin top dielectric layer. A gate electrode is formed over the dielectric stack. The memory device is operative to perform a direct tunneling channel erase operation in which a pair of charge storing cells within a charge storing layer are erased via direct tunneling through the thin top dielectric layer.
摘要翻译：非易失性存储器件包括半导体衬底和衬底内的源极和漏极。在衬底上形成电介质叠层。电介质堆叠包括薄的顶部电介质层。在电介质叠层上形成栅电极。存储器装置可操作以执行直接隧道通道擦除操作，其中电荷存储层内的一对电荷存储单元通过经由薄顶介电层的直接隧穿而被擦除。

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