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11. 发明申请

US20080248612A1 ASYMMETRIC ALIGNMENT OF SUBSTRATE INTERCONNECT TO SEMICONDUCTOR DIE 有权
标题翻译：基板与半导体芯片的非对称对准
公开(公告)号：US20080248612A1
公开(公告)日：2008-10-09
申请号：US12139185
申请日：2008-06-13
申请人： Gary S. Delp
发明人： Gary S. Delp
IPC分类号： H01L21/00
CPC分类号： H01L23/5386 , H01L24/81 , H01L25/0655 , H01L2224/24226 , H01L2224/81801 , H01L2224/82 , H01L2224/85 , H01L2224/86 , H01L2924/14 , H01L2924/00
摘要： An apparatus includes a first semiconductor die and at least one further semiconductor die. A substrate is attached to the first die and the further die and has an electrical interconnect pattern that interconnects contacts on the first die with respective contacts on the further die. Features of the interconnect pattern have positions on the substrate with smaller tolerances relative to positions of the contacts on the first die than to positions of the contacts on the further die.
摘要翻译：一种装置包括第一半导体管芯和至少一个另外的半导体管芯。衬底附接到第一裸片和另一裸片，并且具有将第一裸片上的触点与另一裸片上的相应触点互连的电互连图案。互连图案的特征在基板上具有相对于第一裸片上的触点的位置具有比在另一裸片上的触点的位置更小的公差的位置。

12. 发明授权

US07352748B1 Updating of routing data in a network element 有权
标题翻译：更新网络元素中的路由数据
公开(公告)号：US07352748B1
公开(公告)日：2008-04-01
申请号：US10291999
申请日：2002-11-12
申请人： Ranjit Rozario , Gary S. Delp
发明人： Ranjit Rozario , Gary S. Delp
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L45/00 , H04L12/4625 , H04L45/60 , H04L45/7453
摘要： In one embodiment, an apparatus comprises a logic coupled to receive a number of data packets. The logic comprises an execution unit to generate a request for routing data for a data packet of the number of data packets. The logic also includes a memory lookup engine coupled to the execution unit and a local memory. The local memory is to store routing data for the number of data packets. The memory lookup engine is to receive the request and to update the local memory upon determining that the routing data for the data packet is not found in the local memory. Additionally, the logic includes a communication logic coupled to the memory lookup engine. The communication logic is to transmit an update message to a remote logic. The update message is to cause the remote logic to update a remote memory, wherein the update message is transmitted based on a low priority update upon determining that a buffer for update messages of the remote memory is full when the local memory is updated.
摘要翻译：在一个实施例中，一种装置包括耦合以接收多个数据分组的逻辑。该逻辑包括一个执行单元，用于产生数据包数目的数据包路由数据的请求。逻辑还包括耦合到执行单元和本地存储器的存储器查找引擎。本地存储器是存储数据包数量的路由数据。存储器查找引擎在确定在本地存储器中没有发现数据分组的路由数据时，接收请求并更新本地存储器。此外，逻辑包括耦合到存储器查找引擎的通信逻辑。通信逻辑是向远程逻辑发送更新消息。所述更新消息是使所述远程逻辑更新远程存储器，其中，当更新所述本地存储器时，在确定所述远程存储器的更新消息的缓冲器已满之后，基于低优先级更新发送所述更新消息。

13. 发明授权

US5737638A System for determining plurality of data transformations to be performed upon single set of data during single transfer by examining communication data structure 失效
标题翻译：用于通过检查通信数据结构来确定在单次传送期间对单个数据集合执行的多个数据变换的系统
公开(公告)号：US5737638A
公开(公告)日：1998-04-07
申请号：US502782
申请日：1995-07-14
申请人： Jonathan W. Byrn , Gary S. Delp , Philip L. Leichty , Robert J. Manulik , Arthur J. Meyer, III , Albert A. Slane
发明人： Jonathan W. Byrn , Gary S. Delp , Philip L. Leichty , Robert J. Manulik , Arthur J. Meyer, III , Albert A. Slane
IPC分类号： G06F13/40 , G06F3/00 , G06F15/16
CPC分类号： G06F13/4027
摘要： A method and apparatus are disclosed for providing an inline data service within a data processing system coupled to a communications network. The data processing system includes a host memory. According to the present invention, the apparatus comprises an adapter memory for temporarily storing data communicated between the data processing system and the communications network and a memory access controller, which controls transfers of data between the adapter memory and the host memory. The apparatus further includes means for selectively performing a data transformation on data transferred between the adapter memory and the host memory, wherein the data transformation is performed during a transfer of the data such that data communication latency is reduced. In a second preferred embodiment of the present invention, a multibus data processing system has a processor and a first memory coupled to a first bus and a second memory coupled to a second bus. A bridge adapter, including means for transferring data from the first memory to the second memory and means for selectively performing a data transformation, is coupled between the first and second buses. During transfers of data from the first memory to the second memory, the bridge adapter selectively performs data transformations on the data, such that data processing latency is reduced.
摘要翻译：公开了用于在耦合到通信网络的数据处理系统内提供在线数据服务的方法和装置。数据处理系统包括主机存储器。根据本发明，该装置包括用于临时存储在数据处理系统和通信网络之间传送的数据的适配器存储器和控制适配器存储器和主机存储器之间的数据传输的存储器访问控制器。该装置还包括用于选择性地对在适配器存储器和主机存储器之间传送的数据执行数据变换的装置，其中在数据传送期间执行数据变换，使得数据通信等待时间减少。在本发明的第二优选实施例中，多位数据处理系统具有耦合到第一总线的处理器和第一存储器，以及耦合到第二总线的第二存储器。包括用于将数据从第一存储器传送到第二存储器的装置和用于选择性地执行数据变换的装置的桥接器耦合在第一和第二总线之间。在从第一存储器传输到第二存储器的数据传输期间，桥接器适配器有选择地对数据进行数据转换，从而减少数据处理等待时间。

14. 发明授权

US5634015A Generic high bandwidth adapter providing data communications between diverse communication networks and computer system 失效
标题翻译：通用高带宽适配器提供不同通信网络和计算机系统之间的数据通信
公开(公告)号：US5634015A
公开(公告)日：1997-05-27
申请号：US317894
申请日：1994-10-04
申请人： Paul Chang , Gary S. Delp , Hanafy E.-S. Meleis , Rafael M. Montalvo , David I. Seidman , Ahmed N.-E.-D. Tantawy , Dominick A. Zumbo
发明人： Paul Chang , Gary S. Delp , Hanafy E.-S. Meleis , Rafael M. Montalvo , David I. Seidman , Ahmed N.-E.-D. Tantawy , Dominick A. Zumbo
IPC分类号： G06F13/00 , G06F5/06 , G06F13/12 , G06F13/38 , H04L12/18 , H04L12/56 , H04L29/10
CPC分类号： H04L49/9026 , G06F13/128 , G06F13/387 , G06F5/06 , H04L49/90 , H04L49/901 , H04L49/9021 , H04L49/9047 , H04L12/18 , H04L49/205 , H04L49/3027 , H04L49/351
摘要： A generic high bandwidth adapter providing a unified architecture for data communications between buses, channels, processors, switch fabrics and/or communication networks. Data is carried by data stream packets of variable lengths, and each packet includes a header control information portion required by communication protocols used to mediate the information exchange, and normally a data portion for the data which is to be communicated. A packet memory stores data packets arriving at a plurality of generic adapter input/output ports. The packet memory is segmented into a plurality of buffers, and each data packet is stored in one or more buffers as required by the length thereof. A generic adapter manager is provided for performing and synchronizing generic adapter management functions, including implementing data structures in the packet memory by organizing data packets in buffers, and organizing data packets into queues for processing by the processor subsystem or transfer to or from generic adapter input/output ports. The generic adapter manager prepares future response to anticipated requests for communications services which are functions of the current requests for communication services, such as preparing a response for an anticipated request for a next buffer by a current request for a receipt of data. The generic adapter manager stores the future responses at specified addresses in memory which can be read by a requester. Each generic adapter input/output port has associated therewith a packet memory interface providing for the transfer of data packets into and out of the packet memory, such that when a data packet is received at an input/output port, the data packet is transferred into the adapter packet memory and queued for processing.
摘要翻译：通用高带宽适配器，为总线，通道，处理器，交换结构和/或通信网络之间的数据通信提供统一架构。数据由可变长度的数据流分组携带，每个分组包括用于调停信息交换的通信协议所需的报头控制信息部分，通常是要传送的数据的数据部分。分组存储器存储到达多个通用适配器输入/输出端口的数据分组。分组存储器被分割成多个缓冲器，并且每个数据分组根据其长度的要求存储在一个或多个缓冲器中。提供通用适配器管理器，用于执行和同步通用适配器管理功能，包括通过在缓冲器中组织数据分组来实现分组存储器中的数据结构，以及将数据分组组织成队列以供处理器子系统处理或从通用适配器输入传送 /输出端口。通用适配器管理器准备对作为通信服务的当前请求的功能的通信服务的预期请求的未来响应，诸如通过当前接收数据的请求准备对下一个缓冲区的预期请求的响应。通用适配器管理器将将来的响应存储在可由请求者读取的存储器中的指定地址处。每个通用适配器输入/输出端口具有与其相关联的分组存储器接口，用于将数据分组传入和传出分组存储器，使得当在输入/输出端口处接收到数据分组时，将数据分组转移到适配器包内存并排队处理。

15. 发明授权

US5367643A Generic high bandwidth adapter having data packet memory configured in three level hierarchy for temporary storage of variable length data packets 失效
标题翻译：通用高带宽适配器具有配置在三级层级中的数据分组存储器，用于临时存储可变长度数据分组
公开(公告)号：US5367643A
公开(公告)日：1994-11-22
申请号：US651894
申请日：1991-02-06
申请人： Paul Chang , Gary S. Delp , Hanafy E. Meleis , Rafael M. Montalvo , David I. Seidman , Ahmed N. Tantawy , Dominick A. Zumbo
发明人： Paul Chang , Gary S. Delp , Hanafy E. Meleis , Rafael M. Montalvo , David I. Seidman , Ahmed N. Tantawy , Dominick A. Zumbo
IPC分类号： G06F13/00 , G06F5/06 , G06F13/12 , G06F13/38 , H04L12/18 , H04L12/56 , H04L29/10
CPC分类号： H04L49/9026 , G06F13/128 , G06F13/387 , G06F5/06 , H04L49/90 , H04L49/901 , H04L49/9021 , H04L49/9047 , H04L12/18 , H04L49/205 , H04L49/3027 , H04L49/351
摘要： A generic high bandwidth adapter providing a unified architecture for data communications between buses, channels, processors, switch fabrics and/or communication networks. Data is carried by data stream packets of variable lengths, and each packet includes a header control information portion required by communication protocols used to mediate the information exchange, and normally a data portion for the data which is to be communicated. The generic high bandwidth adapter comprises a processor subsystem including a processor for processing the header control information portions of data packets. The processor has access to data packets stored in a packet memory which stores data packets arriving at four generic adapter input/output ports. The packet memory is segmented into a plurality of buffers, and each data packet is stored in one or more buffers as required by the length thereof. A generic adapter manager is provided for performing and synchronizing generic adapter management functions, including implementing data structures in the packet memory by organizing data packets in buffers, and organizing data packets into queues for processing by the processor subsystem or transfer to or from generic adapter input/output ports. Each generic adapter input/output port has associated therewith a packet memory interface providing for the transfer of data packets into and out of the packet memory, such that when a data packet is received at an input/output port, the data packet is transferred into the adapter packet memory and queued for processing.
摘要翻译：通用高带宽适配器，为总线，通道，处理器，交换结构和/或通信网络之间的数据通信提供统一架构。数据由可变长度的数据流分组携带，每个分组包括用于调停信息交换的通信协议所需的报头控制信息部分，通常是要传送的数据的数据部分。通用高带宽适配器包括处理器子系统，其包括用于处理数据分组的报头控制信息部分的处理器。处理器可以访问存储在分组存储器中的数据分组，其存储到达四个通用适配器输入/输出端口的数据分组。分组存储器被分割成多个缓冲器，并且每个数据分组根据其长度的要求存储在一个或多个缓冲器中。提供通用适配器管理器，用于执行和同步通用适配器管理功能，包括通过在缓冲器中组织数据分组来实现分组存储器中的数据结构，以及将数据分组组织成队列以供处理器子系统处理或从通用适配器输入传送 /输出端口。每个通用适配器输入/输出端口具有与其相关联的分组存储器接口，用于将数据分组传入和传出分组存储器，使得当在输入/输出端口处接收到数据分组时，将数据分组转移到适配器包内存并排队处理。

16. 发明授权

US5260942A Method and apparatus for batching the receipt of data packets 失效
标题翻译：批量接收数据包的方法和装置
公开(公告)号：US5260942A
公开(公告)日：1993-11-09
申请号：US847470
申请日：1992-03-06
申请人： Richard A. Auerbach , Jerry A. Blades , Jonathan W. Byrn , Gary S. Delp
发明人： Richard A. Auerbach , Jerry A. Blades , Jonathan W. Byrn , Gary S. Delp
IPC分类号： H04L12/56 , H04L29/06 , H04J3/14
CPC分类号： H04L12/56 , H04L29/06 , H04L69/22
摘要： A method and a system in a distributed data processing network for enhancing the processing of a plurality of related data packets received at a receiving station within the distributed data processing network, each of the data packets having a header associated herewith includes sequentially receiving a number of data packets at the receiving station. Next, the header associated with a first data packet is examined and predicted profile is generated for comparison with a related subsequent data packet. The next data packet received is then compared with the predicted profile to determine whether or not the two data packets may be consolidated.

17. 发明授权

US07620924B2 Base platforms with combined ASIC and FPGA features and process of using the same 有权
标题翻译：具有ASIC和FPGA组合的基本平台功能及其使用过程
公开(公告)号：US07620924B2
公开(公告)日：2009-11-17
申请号：US11079439
申请日：2005-03-14
申请人： Gary S. Delp , George Wayne Nation
发明人： Gary S. Delp , George Wayne Nation
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5054
摘要： A process is disclosed for configuring a base platform having ASIC and FPGA modules to perform a plurality of functions. A verified RTL hardware description of a circuit is mapped and annotated to identify memory programmable functions. The memory programmable functions are grouped for assignment to FPGA modules. The non-memory programmable functions are synthesized to ASIC modules, and the memory programmable functions are synthesized to FPGA modules. Placement, signal routing and boundary timing closure are completed and the platform is configured by adding metallization layer(s) to configure the ASIC modules and creating a firmware memory to configure the FPGA modules. An over-provisioning feature in the FPGA modules permits post-fabrication alteration of logic functions.
摘要翻译：公开了一种用于配置具有ASIC和FPGA模块以执行多个功能的基础平台的过程。对电路的验证RTL硬件描述进行映射和注释，以识别存储器可编程功能。存储器可编程功能被分组以分配给FPGA模块。非存储器可编程功能被合成到ASIC模块，并且存储器可编程功能被合成到FPGA模块。完成放置，信号路由和边界定时关闭，并通过添加金属化层来配置ASIC模块并创建固件存储器来配置FPGA模块来配置平台。 FPGA模块中的过度供应功能允许逻辑功能的后制造改变。

18. 发明授权

US07496861B2 Method for generalizing design attributes in a design capture environment 失效
标题翻译：在设计捕获环境中概括设计属性的方法
公开(公告)号：US07496861B2
公开(公告)日：2009-02-24
申请号：US11290186
申请日：2005-11-30
申请人： George W. Nation , Gary Lippert , Gary S. Delp
发明人： George W. Nation , Gary Lippert , Gary S. Delp
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method for generalizing design attributes in a design capture environment comprising the steps of (A) defining a procedure for adding one or more auxiliary configurators to a tool or suite of tools, (B) linking the auxiliary configurators to predetermined object points in an abstracted design and (C) defining a procedure for the tool or suite of tools to reference the one or more auxiliary configurators, wherein the auxiliary configurators are neither referenced by a core nor built into the tool or suite of tools.
摘要翻译：一种用于在设计捕获环境中概括设计属性的方法，包括以下步骤：（A）定义用于将一个或多个辅助配置器添加到工具或工具套件的过程，（B）将辅助配置器链接到抽象的预定对象点设计和（C）定义用于参考一个或多个辅助配置器的工具或工具套件的过程，其中辅助配置器既不被核心引用也不内置在工具或工具套件中。

19. 发明授权

US07043611B2 Reconfigurable memory controller 有权
标题翻译：可重构内存控制器
公开(公告)号：US07043611B2
公开(公告)日：2006-05-09
申请号：US10316510
申请日：2002-12-11
申请人： Gary P. McClannahan , Gary S. Delp , George W. Nation
发明人： Gary P. McClannahan , Gary S. Delp , George W. Nation
IPC分类号： G06F12/00
CPC分类号： G06F13/1694
摘要： A reconfigurable memory controller includes a plurality of communicatively coupled memory controllers. The plurality of memory controllers may be configured into a first configuration based on a grouping of memory controllers and then reconfigured into a second configuration based on a different grouping of memory controllers, where the first and second configurations have different performance bandwidths for accessing memory.
摘要翻译：可重构存储器控制器包括多个通信耦合的存储器控制器。可以基于存储器控制器的分组将多个存储器控制器配置为第一配置，然后基于存储器控制器的不同组合重新配置成第二配置，其中第一和第二配置具有用于访问存储器的不同的性能带宽。

20. 发明授权

US5537408A apparatus and method for segmentation and time synchronization of the transmission of multimedia data 失效
标题翻译：多媒体数据传输的分段和时间同步的装置和方法
公开(公告)号：US5537408A
公开(公告)日：1996-07-16
申请号：US463207
申请日：1995-06-05
申请人： Mark W. Branstad , Jonathan W. Byrn , Gary S. Delp , Phillip L. Leichty , Jeffrey J. Lynch , Kevin G. Plotz , Lee A. Sendelbach , Albert A. Slane
发明人： Mark W. Branstad , Jonathan W. Byrn , Gary S. Delp , Phillip L. Leichty , Jeffrey J. Lynch , Kevin G. Plotz , Lee A. Sendelbach , Albert A. Slane
IPC分类号： H04N7/26 , G06F17/30 , G06F19/00 , H04J3/06 , H04L12/56 , H04L29/06 , H04L29/08 , H04N7/24 , H04N7/52 , H04N21/2343 , H04N21/2368 , H04N21/2381 , H04N21/242 , H04N21/2543 , H04N21/262 , H04N21/43 , H04N21/434 , H04N21/4363 , H04N21/438 , H04N21/472 , H04N21/643 , H04N21/845 , H04N21/8547 , H04Q3/00 , H04Q11/04 , H04N5/04
CPC分类号： H04Q11/0478 , H04L29/06 , H04L65/607 , H04N21/234318 , H04N21/2368 , H04N21/2381 , H04N21/242 , H04N21/2543 , H04N21/262 , H04N21/26208 , H04N21/4307 , H04N21/4341 , H04N21/4363 , H04N21/4381 , H04N21/47202 , H04N21/64307 , H04N21/8456 , H04N21/8547 , H04J3/0632 , H04L2012/5616 , H04L2012/565 , H04L2012/5652 , H04L2012/5664 , H04L2012/5674 , H04L2012/5679 , H04L29/06027 , H04L69/324 , H04L69/326
摘要： Method and apparatus are provided for transmitting a stream of multimedia digital data over a distribution communications network. A multimedia stream server segments the multimedia digital data stream into data blocks on a first boundary and a second boundary. The first boundary is a set number of transport system data packets and the second boundary is a transport system data packet including a timestamp. A scheduler schedules the segmented data blocks for transmission. The multimedia stream server decodes the segmented data blocks to locate the timestamps and matches the transmission of the located timestamp data block with a time value indicated by the timestamp. The set number of transport system data packets can be determined at connection setup and is not a predetermined value for all sessions. At the receiver, batch processing of received multimedia data can be provided.
摘要翻译：提供了用于通过分发通信网络发送多媒体数字数据流的方法和装置。多媒体流服务器将多媒体数字数据流分割成第一边界和第二边界上的数据块。第一边界是一组传输系统数据分组，第二边界是包括时间戳的传输系统数据分组。调度器调度分段数据块进行传输。多媒体流服务器解码分段的数据块以定位时间戳，并将所定位的时间戳数据块的传输与由时间戳指示的时间值进行匹配。可以在连接建立时确定传送系统数据包的设定数量，而不是所有会话的预定值。在接收机处，可以提供接收到的多媒体数据的批量处理。

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