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11. 发明授权

US07325024B2 Adder circuit with sense-amplifier multiplexer front-end 有权
标题翻译：加法器电路带有读出放大器多路复用器前端
公开(公告)号：US07325024B2
公开(公告)日：2008-01-29
申请号：US10728127
申请日：2003-12-04
申请人： Sanu K. Mathew , Mark A. Anders , Ram K. Krishnamurthy , Sapumal Wijeratne
发明人： Sanu K. Mathew , Mark A. Anders , Ram K. Krishnamurthy , Sapumal Wijeratne
IPC分类号： G06F7/50
CPC分类号： G06F7/507 , G06F7/506
摘要： An adder circuit includes a number of selectors and an adder. The selectors feed the adder with multiple input data bits. Each of the selectors includes a combination of a multiplexing network and a sense amplifier to select from a number of input values to generate the multiple input data bits. The combination of the multiplexing network and the sense amplifier acts as the state-holding element at the input of the adder, avoiding the overheads of an explicit latch stage.
摘要翻译：一个加法器电路包括多个选择器和一个加法器。选择器为加法器提供多个输入数据位。每个选择器包括复用网络和读出放大器的组合，以从多个输入值中选择以产生多个输入数据位。复用网络和读出放大器的组合在加法器的输入端作为状态保持元件，避免显式锁存级的开销。

12. 发明授权

US07188134B2 High-performance adder 有权
标题翻译：高性能加法器
公开(公告)号：US07188134B2
公开(公告)日：2007-03-06
申请号：US09967240
申请日：2001-09-28
申请人： Sanu K. Mathew , Ram K. Krishnamurthy
发明人： Sanu K. Mathew , Ram K. Krishnamurthy
IPC分类号： G06F7/50
CPC分类号： G06F7/506 , G06F7/507
摘要： An adder for use in summing two binary numbers in an arithmetic logic unit of a processor. The adder includes a sparse carry-merge circuit adapted to generate a first predetermined number of carries and a plurality of intermediate carry generators coupled to the sparse carry merge circuit and adapted to generate a second predetermined number of carry signals. The adder further includes a plurality of conditional sum generators coupled to the intermediate carry generators and to the sparse carry-merge circuit to provide the sum of the two binary numbers. The adder may also include a multiplexer recovery circuit that enables a single rail dynamic implementation of the adder core.
摘要翻译：一种加法器，用于对处理器的算术逻辑单元中的两个二进制数进行求和。加法器包括适于生成第一预定数量的进位的稀疏进位合并电路和耦合到稀疏进位合并电路并适于产生第二预定数量进位信号的多个中间进位发生器。加法器还包括耦合到中间进位发生器和稀疏进位合并电路的多个条件和发生器，以提供两个二进制数的和。加法器还可以包括多路复用器恢复电路，其实现加法器核的单轨动态实现。

13. 发明授权

US09262256B2 Using dark bits to reduce physical unclonable function (PUF) error rate without storing dark bits location 有权
标题翻译：使用暗位来减少物理不可克隆功能（PUF）错误率，而不存储暗位置
公开(公告)号：US09262256B2
公开(公告)日：2016-02-16
申请号：US14140243
申请日：2013-12-24
申请人： Sanu K. Mathew , Sudhir K. Satpathy , Patrick Koeberl , Jiangtao Li , Ram K. Krishnamurthy , Anand Rajan
发明人： Sanu K. Mathew , Sudhir K. Satpathy , Patrick Koeberl , Jiangtao Li , Ram K. Krishnamurthy , Anand Rajan
IPC分类号： G06F21/00 , H04L29/06 , G06F11/07 , G11C7/24 , G11C7/00 , G06F7/58 , H04L9/34
CPC分类号： G06F11/0793 , G06F7/00 , G06F7/588 , G06F11/0745 , G11C7/24 , H04L9/3278 , H04L9/34
摘要： Dark-bit masking technologies for physically unclonable function (PUF) components are described. A computing system includes a processor core and a secure key manager component coupled to the processor core. The secure key manager includes the PUF component, and a dark-bit masking circuit coupled to the PUF component. The dark-bit masking circuit is to measure a PUF value of the PUF component multiple times during a dark-bit window to detect whether the PUF value of the PUF component is a dark bit. The dark bit indicates that the PUF value of the PUF component is unstable during the dark-bit window. The dark-bit masking circuit is to output the PUF value as an output PUF bit of the PUF component when the PUF value is not the dark bit and set the output PUF bit to be a specified value when the PUF value of the PUF component is the dark bit.
摘要翻译：描述了用于物理不可克隆功能（PUF）组件的暗位掩蔽技术。计算系统包括处理器核心和耦合到处理器核心的安全密钥管理器组件。安全密钥管理器包括PUF组件和耦合到PUF组件的暗位屏蔽电路。暗位掩蔽电路是在暗位窗口期间多次测量PUF分量的PUF值，以检测PUF分量的PUF值是否为暗位。暗位表示PUF组件的PUF值在暗位窗口期间不稳定。当PUF值不是暗位时，暗位屏蔽电路将输出PUF值作为PUF分量的输出PUF位，并且当PUF分量的PUF值为黑暗的一点

14. 发明申请

US20150023500A1 APPARATUS AND METHOD FOR SKEIN HASHING 有权
标题翻译：装置和方法进行滑雪
公开(公告)号：US20150023500A1
公开(公告)日：2015-01-22
申请号：US14507427
申请日：2014-10-06
申请人： Farhana Sheikh , Jesse Walker , Sanu K. Mathew , Ram K. Krishnamurthy
发明人： Farhana Sheikh , Jesse Walker , Sanu K. Mathew , Ram K. Krishnamurthy
IPC分类号： H04L9/08
CPC分类号： H04L9/0861 , H04L9/0618 , H04L9/0625 , H04L9/0631 , H04L9/0637 , H04L9/0643 , H04L9/0816 , H04L2209/125 , H04L2209/24 , H04N1/32277
摘要： Described herein are an apparatus and method for Skein hashing. The apparatus comprises a block cipher operable to receive an input data and to generate a hashed output data by applying Unique Block Iteration (UBI) modes, the block cipher comprising at least two mix and permute logic units which are pipelined by registers; and a counter, coupled to the block cipher, to determine a sequence of the UBI modes and to cause the block cipher to process at least two input data simultaneously for generating the hashed output data.
摘要翻译：这里描述了用于Skein散列的装置和方法。该装置包括可以用于接收输入数据并通过应用唯一块迭代（UBI）模式来产生散列输出数据的块密码，所述块密码包括由寄存器流水线化的至少两个混合和置换逻辑单元; 以及耦合到所述块密码的计数器，以确定所述UBI模式的序列，并且使所述块密码同时处理至少两个输入数据以产生所述散列输出数据。

15. 发明授权

US06404234B1 Variable virtual ground domino logic with leakage control 有权
标题翻译：具有泄漏控制的可变虚拟地面多米诺逻辑
公开(公告)号：US06404234B1
公开(公告)日：2002-06-11
申请号：US09851917
申请日：2001-05-09
申请人： Steven K. Hsu , Sanu K. Mathew , Ram K. Krishnamurthy
发明人： Steven K. Hsu , Sanu K. Mathew , Ram K. Krishnamurthy
IPC分类号： H03K19096
CPC分类号： H03K19/0963
摘要： A domino logic circuit and method comprise at least two series-connected domino logic stages with each domino logic stage comprising a dynamic stage and a static stage. A variable virtual ground of the first domino logic's static stage is switched to a voltage level below a circuit ground level when a received clock signal and a second domino logic stage's dynamic output are both high, indicating the second domino logic circuit stage is in the evaluation phase.
摘要翻译：多米诺逻辑电路和方法包括至少两个串联连接的多米诺逻辑级，每个多米诺逻辑级包括动态级和静态级。当接收到的时钟信号和第二多米诺逻辑级的动态输出均为高电平时，第一多米诺逻辑逻辑静态级的可变虚拟接地切换到低于电路接地电平的电压电平，表明第二多米诺逻辑电路级处于评估状态相。

16. 发明申请

US20140266297A1 HARDWARE-EMBEDDED KEY BASED ON RANDOM VARIATIONS OF A STRESS-HARDENED INEGRATED CIRCUIT 有权
标题翻译：基于应力硬化电路的随机变化的硬件嵌入式键
公开(公告)号：US20140266297A1
公开(公告)日：2014-09-18
申请号：US13889849
申请日：2013-05-08
申请人： Sanu K. Mathew , Rachael J. Parker , Ram K. Krishnamurthy
发明人： Sanu K. Mathew , Rachael J. Parker , Ram K. Krishnamurthy
IPC分类号： H03K19/003
CPC分类号： H03K19/00369 , H03K19/00315
摘要： An IC cell designed to assert one of multiple possible output states, each with equal probability, implemented to assert a pre-determined one of the multiple output states based on random variations within the IC cell, such as random process variations. An array of IC cells is configurable to provide a hardware-embedded key upon power-up that is unique to the combination of random variations of selected IC cells, resistant to tampering prior to and during manufacture, and tolerant to aging, instantaneous thermal noise, and environmental variations, such as voltage and temperature fluctuations. The key may be used as, without limitation, a Platform Root Key, a High-Bandwidth Digital Content Protection (HDCP) key, an Enhanced Privacy Identification (EPID) key, and/or an Advanced Access Content System (AACS) key. Also disclosed are techniques to measure stability and stress-harden an IC cell based on output states of the IC cell.
摘要翻译：被设计成用于断言多个可能的输出状态之一（每个具有相等的概率）的IC单元被实现为基于IC单元内的随机变化来断言多个输出状态中的预定的一个，例如随机过程变化。 IC单元阵列可配置为在上电时提供硬件嵌入式密钥，该特征是选择的IC单元的随机变化的组合，在制造之前和之后都能够防止篡改，并且能够耐老化，瞬时热噪声，和环境变化，如电压和温度波动。该密钥可以用作但不限于平台根密钥，高带宽数字内容保护（HDCP）密钥，增强型隐私标识（EPID）密钥和/或高级访问内容系统（AACS）密钥）。还公开了基于IC电池的输出状态来测量IC电池的稳定性和应力硬化的技术。

17. 发明授权

US07840885B2 Distributed ring control circuits for Viterbi traceback 有权
标题翻译：用于维特比回溯的分布式环形控制电路
公开(公告)号：US07840885B2
公开(公告)日：2010-11-23
申请号：US11860493
申请日：2007-09-24
申请人： Mark A. Anders , Sanu K. Mathew , Ram K. Krishnamurthy
发明人： Mark A. Anders , Sanu K. Mathew , Ram K. Krishnamurthy
IPC分类号： H03M13/41
CPC分类号： H03M13/6505 , H03M13/41 , H03M13/4169
摘要： Shift resister rings are used to provide column access in a traceback memory during Viterbi decoding.
摘要翻译：移位电阻环用于在维特比解码期间在追溯存储器中提供列访问。

18. 发明授权

US06628143B2 Full-swing source-follower leakage tolerant dynamic logic 有权
标题翻译：全摆动源跟踪器泄漏容错动态逻辑
公开(公告)号：US06628143B2
公开(公告)日：2003-09-30
申请号：US09965360
申请日：2001-09-26
申请人： Steven K. Hsu , Mark A. Anders , Sanu K. Mathew , Ram K. Krishnamurthy
发明人： Steven K. Hsu , Mark A. Anders , Sanu K. Mathew , Ram K. Krishnamurthy
IPC分类号： H03K19096
CPC分类号： H03K19/0963
摘要： An embodiment of a full-swing, source-follower leakage tolerant dynamic logic gate comprises an nMOSFET logic to conditionally charge a node during an evaluation phase, and to charge the node to a relatively small voltage during the pre-charge phase so that the nMOSFET logic becomes reverse-biased.
摘要翻译：全驱动，源极跟随器泄漏容限动态逻辑门的实施例包括nMOSFET逻辑，用于在评估阶段对节点进行有条件充电，并且在预充电阶段期间将节点充电至相对小的电压，使得nMOSFET 逻辑变为反向偏置。

19. 发明授权

US08923510B2 Method and apparatus for efficiently implementing the advanced encryption standard 有权
标题翻译：有效实施高级加密标准的方法和装置
公开(公告)号：US08923510B2
公开(公告)日：2014-12-30
申请号：US11966658
申请日：2007-12-28
申请人： Shay Gueron , Michael E. Kounavis , Ram Krishnamurthy , Sanu K. Mathew
发明人： Shay Gueron , Michael E. Kounavis , Ram Krishnamurthy , Sanu K. Mathew
IPC分类号： H04L9/00 , G06F7/00
CPC分类号： H04L9/0631 , G06F7/00 , G06F9/30007 , G06F9/30112 , G06F9/30145 , G06F9/30149 , G06F9/30196 , G06F9/3887 , G06F21/602 , H04L2209/34
摘要： Implementations of Advanced Encryption Standard (AES) encryption and decryption processes are disclosed. In one embodiment of S-box processing, a block of 16 byte values is converted, each byte value being converted from a polynomial representation in GF(256) to a polynomial representation in GF((22)4). Multiplicative inverse polynomial representations in GF((22)4) are computed for each of the corresponding polynomial representations in GF((22)4). Finally corresponding multiplicative inverse polynomial representations in GF((22)4) are converted and an affine transformation is applied to generate corresponding polynomial representations in GF(256). In an alternative embodiment of S-box processing, powers of the polynomial representations are computed and multiplied together in GF(256) to generate multiplicative inverse polynomial representations in GF(256). In an embodiment of inverse-columns-mixing, the 16 byte values are converted from a polynomial representation in GF(256) to a polynomial representation in GF((24)2). A four-by-four matrix is applied to the transformed polynomial representation in GF((24)2) to implement the inverse-columns-mixing.
摘要翻译：公开了高级加密标准（AES）加密和解密过程的实现。在S盒处理的一个实施例中，转换16字节值的块，每个字节值从GF（256）中的多项式表示转换为GF（（22）4）中的多项式表示。对于GF（（22）4）中的每个对应多项式表示，计算GF（（22）4）中的乘法逆多项式表示。最后，对GF（（22）4）中的相应的乘法逆多项式表示进行转换，并应用仿射变换以在GF（256）中生成对应的多项式表示。在S盒处理的替代实施例中，计算多项式表示的幂并在GF（256）中相乘，以在GF（256）中生成乘法逆多项式表示。在反列混合的实施例中，将16字节值从GF（256）中的多项式表示转换为GF（（24）2）中的多项式表示。将四乘四矩阵应用于GF（（24）2）中的变换多项式表示，以实现反列混合。

20. 发明申请

US20090172068A1 METHOD AND APPARATUS FOR EFFICIENTLY IMPLEMENTING THE ADVANCED ENCRYPTION STANDARD 有权
标题翻译：有效执行高级加密标准的方法和设备
公开(公告)号：US20090172068A1
公开(公告)日：2009-07-02
申请号：US11966658
申请日：2007-12-28
申请人： MICHAEL E. KOUNAVIS , Shay Gueron , Ram Krishnamurthy , Sanu K. Mathew
发明人： MICHAEL E. KOUNAVIS , Shay Gueron , Ram Krishnamurthy , Sanu K. Mathew
IPC分类号： G06F7/38
CPC分类号： H04L9/0631 , G06F7/00 , G06F9/30007 , G06F9/30112 , G06F9/30145 , G06F9/30149 , G06F9/30196 , G06F9/3887 , G06F21/602 , H04L2209/34
摘要： Implementations of Advanced Encryption Standard (AES) encryption and decryption processes are disclosed. In one embodiment of S-box processing, a block of 16 byte values is converted, each byte value being converted from a polynomial representation in GF(256) to a polynomial representation in GF((22)4). Multiplicative inverse polynomial representations in GF((22)4) are computed for each of the corresponding polynomial representations in GF((22)4). Finally corresponding multiplicative inverse polynomial representations in GF((22)4) are converted and an affine transformation is applied to generate corresponding polynomial representations in GF(256). In an alternative embodiment of S-box processing, powers of the polynomial representations are computed and multiplied together in GF(256) to generate multiplicative inverse polynomial representations in GF(256). In an embodiment of inverse-columns-mixing, the 16 byte values are converted from a polynomial representation in GF(256) to a polynomial representation in GF((24)2). A four-by-four matrix is applied to the transformed polynomial representation in GF((24)2) to implement the inverse-columns-mixing.
摘要翻译：公开了高级加密标准（AES）加密和解密过程的实现。在S盒处理的一个实施例中，转换16字节值的块，每个字节值从GF（256）中的多项式表示转换为GF（（22）4）中的多项式表示。对于GF（（22）4）中的每个对应多项式表示，计算GF（（22）4）中的乘法逆多项式表示。最后，对GF（（22）4）中的相应的乘法逆多项式表示进行转换，并应用仿射变换以在GF（256）中生成对应的多项式表示。在S盒处理的替代实施例中，计算多项式表示的幂并在GF（256）中相乘，以在GF（256）中生成乘法逆多项式表示。在反列混合的实施例中，将16字节值从GF（256）中的多项式表示转换为GF（（24）2）中的多项式表示。将四乘四矩阵应用于GF（（24）2）中的变换多项式表示，以实现反列混合。

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