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11. 发明授权

US07390749B2 Self-aligned pitch reduction 有权
标题翻译：自对准螺距减小
公开(公告)号：US07390749B2
公开(公告)日：2008-06-24
申请号：US11558238
申请日：2006-11-09
申请人： Ji Soo Kim , Sangheon Lee , Daehan Choi , S. M. Reza Sadjadi
发明人： Ji Soo Kim , Sangheon Lee , Daehan Choi , S. M. Reza Sadjadi
IPC分类号： H01L21/311
CPC分类号： H01L21/0338 , H01L21/0337 , H01L21/31144
摘要： A method for providing features in an etch layer with a memory region and a peripheral region is provided. A memory patterned mask is formed over a first sacrificial layer. A first set of sacrificial layer features is etched into the first sacrificial layer and a second sacrificial layer. Features of the first set of sacrificial layer features are filled with filler material. The first sacrificial layer is removed. The spaces are shrunk with a shrink sidewall deposition. A second set of sacrificial layer features is etched into the second sacrificial layer. The filler material and shrink sidewall deposition are removed. A peripheral patterned mask is formed over the memory region and peripheral region. The second sacrificial layer is etched through the peripheral patterned mask. The peripheral patterned mask is removed. Features are etched into the etch layer from the second sacrificial layer.
摘要翻译：提供了一种用于在具有存储区域和周边区域的蚀刻层中提供特征的方法。存储器图案化掩模形成在第一牺牲层上。第一组牺牲层特征被蚀刻到第一牺牲层和第二牺牲层中。第一组牺牲层特征的特征填充有填充材料。第一牺牲层被去除。这些空间随着收缩侧壁沉积而收缩。第二组牺牲层特征被蚀刻到第二牺牲层中。去除填充材料和收缩侧壁沉积。在存储器区域和外围区域上形成周边图案化掩模。通过外围图案化掩模蚀刻第二牺牲层。去除周边图案掩模。特征从第二牺牲层蚀刻到蚀刻层中。

12. 发明申请

US20080146032A1 GLUE LAYER FOR HYDROFLUOROCARBON ETCH 有权
标题翻译：石油醚水合物
公开(公告)号：US20080146032A1
公开(公告)日：2008-06-19
申请号：US11610953
申请日：2006-12-14
申请人： Ji Soo Kim , Sangheon Lee , Deepak K. Gupta , S. M. Reza Sadjadi
发明人： Ji Soo Kim , Sangheon Lee , Deepak K. Gupta , S. M. Reza Sadjadi
IPC分类号： H01L21/3105
CPC分类号： H01L21/31144 , H01L21/30655 , H01L21/31116 , H01L21/312
摘要： A method for etching features in an etch layer disposed below a mask on a process wafer is provided. A hydrocarbon based glue layer is deposited. The etch layer on the process wafer is etched with at least one cycle, wherein each cycle comprises depositing a hydrofluorocarbon layer over the mask and on the hydrocarbon based glue layer, wherein the hydrocarbon based glue layer increases adhesion of the hydrofluorocarbon layer and etching the etch layer.
摘要翻译：提供了一种用于蚀刻设置在处理晶片上的掩模下方的蚀刻层中的特征的方法。沉积烃基胶层。用至少一个循环蚀刻处理晶片上的蚀刻层，其中每个循环包括在掩模上和基于烃的胶层上沉积氢氟烃层，其中基于烃的胶层增加氢氟烃层的粘附和蚀刻蚀刻层。

13. 发明授权

US06972524B1 Plasma processing system control 有权
公开(公告)号：US06972524B1
公开(公告)日：2005-12-06
申请号：US10808795
申请日：2004-03-24
申请人： Alexei M. Marakhtanov , Eric Allen Hudson , S. M. Reza Sadjadi
发明人： Alexei M. Marakhtanov , Eric Allen Hudson , S. M. Reza Sadjadi
IPC分类号： H01J37/32 , H05H1/00
CPC分类号： H01J37/32935 , H01J37/32091
摘要： A method of approximating an ion energy distribution function (IEDF) at a substrate surface of a substrate, the substrate being processed in a plasma processing chamber. There is included providing a first voltage value, the first voltage value representing a value of a first voltage that represents a DC potential (VDC) at the substrate surface. There is also included providing a peak low frequency RF voltage value (VLFRF(PEAK)) during plasma processing, the peak low frequency RF voltage (VLFRF(PEAK)) value representing a peak value of a low frequency RF voltage (VLFRF) supplied to the plasma processing chamber. There is further included providing a computing device configured to compute the IEDF from the first voltage value and the peak low frequency RF voltage value (VLFRF(PEAK)) in accordance with f ⁡ ( E ) ≡ ( ⅆ V LF ⅆ t ) - 1 , wherein V LF ⁡ ( t ) = [ ( V LFRF ⁡ ( PEAK ) - V dc 2 ) 1 / 2 - ( V LFRF ⁡ ( PEAK ) - V dc 8 ) 1 / 2 ⁢ sin ⁢ ⁢ ω ⁢ ⁢ t ] 2 .

14. 发明授权

US06794293B2 Trench etch process for low-k dielectrics 有权
标题翻译：低k电介质的沟槽蚀刻工艺
公开(公告)号：US06794293B2
公开(公告)日：2004-09-21
申请号：US09972765
申请日：2001-10-05
申请人： SiYi Li , S. M. Reza Sadjadi , David R. Pirkle , Steve Lassig , Sean Kang , Vinay Pohray , Peter Cirigliano
发明人： SiYi Li , S. M. Reza Sadjadi , David R. Pirkle , Steve Lassig , Sean Kang , Vinay Pohray , Peter Cirigliano
IPC分类号： H01L21302
CPC分类号： H01L21/31116 , H01L21/02126 , H01L21/31138 , H01L21/312 , H01L21/3124 , H01L21/3127 , H01L21/31629 , H01L21/31695 , H01L21/76804 , H01L21/76808
摘要： The present inventions is a method of trench formation within a dielectric layer, comprising, first, etching a via within the dielectric layer. After the via is etched, an organic plug is used to fill a portion of the via. After the desired amount of organic plug has been etched from the via, a trench is etched with a first gas mixture to a first depth, and a second gas mixture is used to further etch the trench to the final desired trench depth. Preferably, the method is used for low-k dielectrics that do not have an intermediate etch stop layer. Additionally, it is preferable that the first gas mixture is a polymeric gas mixture and the second gas mixture is a non-polymeric gas mixture. As a result of using this method, an interconnect structure for a low-k dielectric without an intermediate etch stop layer having a trench with trench edges that are substantially orthogonal and a via with via edges that are substantially orthogonal is generated.
摘要翻译：本发明是一种在电介质层内形成沟槽的方法，包括：首先蚀刻电介质层内的通孔。在蚀刻通孔之后，使用有机插塞来填充通孔的一部分。在从通孔蚀刻所需量的有机插塞之后，用第一气体混合物蚀刻沟槽至第一深度，并且使用第二气体混合物来进一步将沟槽蚀刻到最终期望的沟槽深度。优选地，该方法用于不具有中间蚀刻停止层的低k电介质。另外，优选地，第一气体混合物是聚合气体混合物，第二气体混合物是非聚合气体混合物。作为使用该方法的结果，产生用于低k电介质的互连结构，而不具有中间蚀刻停止层，该中间蚀刻停止层具有沟槽边缘，其基本上正交，并且具有基本正交的通孔边缘的通孔。

15. 发明授权

US08866202B2 Device with gaps for capacitance reduction 有权
标题翻译：具有间隙的器件，用于降低电容
公开(公告)号：US08866202B2
公开(公告)日：2014-10-21
申请号：US13457147
申请日：2012-04-26
申请人： S. M. Reza Sadjadi , Zhi-Song Huang
发明人： S. M. Reza Sadjadi , Zhi-Song Huang
IPC分类号： H01L21/70 , H01L23/48 , H01L23/52 , H01L21/768 , H01L23/482 , H01L21/033 , H01L21/311
CPC分类号： H01L21/7682 , H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/76802 , H01L21/76843 , H01L23/4821 , H01L2924/0002 , H01L2924/00
摘要： A method for reducing capacitances between semiconductor devices is provided. A plurality of contact structures is formed in a dielectric layer. A mask is formed to cover the contact structures wherein the mask has mask features for exposing parts of the dielectric layer wherein the mask features have widths. The widths of the mask features are shrunk with a sidewall deposition. Gaps are etched into the dielectric layer through the sidewall deposition. The gaps are closed to form pockets in the gaps.
摘要翻译：提供一种降低半导体器件之间的电容的方法。在电介质层中形成多个接触结构。形成掩模以覆盖接触结构，其中掩模具有用于暴露电介质层的部分的掩模特征，其中掩模特征具有宽度。掩模特征的宽度随着侧壁沉积而收缩。间隙通过侧壁沉积蚀刻到介电层中。间隙封闭以形成间隙中的凹坑。

16. 发明授权

US08614149B2 Critical dimension reduction and roughness control 有权
标题翻译：关键尺寸减小和粗糙度控制
公开(公告)号：US08614149B2
公开(公告)日：2013-12-24
申请号：US13586571
申请日：2012-08-15
申请人： Sangheon Lee , Dae-Han Choi , Jisoo Kim , Peter Cirigliano , Zhisong Huang , Robert Charatan , S. M. Reza Sadjadi
发明人： Sangheon Lee , Dae-Han Choi , Jisoo Kim , Peter Cirigliano , Zhisong Huang , Robert Charatan , S. M. Reza Sadjadi
IPC分类号： H01L21/311
CPC分类号： C23F4/00 , H01L21/31116 , H01L21/31144 , H01L21/76816 , Y10S438/947
摘要： A method for forming a feature in an etch layer is provided. A photoresist layer is formed over the etch layer. The photoresist layer is patterned to form photoresist features with photoresist sidewalls. A control layer is formed over the photoresist layer and bottoms of the photoresist features. A conformal layer is deposited over the sidewalls of the photoresist features and control layer to reduce the critical dimensions of the photoresist features. Openings in the control layer are opened with a control layer breakthrough chemistry. Features are etched into the etch layer with an etch chemistry, which is different from the control layer break through chemistry, wherein the control layer is more etch resistant to the etch with the etch chemistry than the conformal layer.
摘要翻译：提供了一种在蚀刻层中形成特征的方法。在蚀刻层上形成光致抗蚀剂层。图案化光致抗蚀剂层以形成具有光致抗蚀剂侧壁的光致抗蚀剂特征。在光致抗蚀剂层和光致抗蚀剂特征的底部上形成控制层。在光致抗蚀剂特征和控制层的侧壁上沉积保形层以减少光刻胶特征的临界尺寸。控制层的开口打开，控制层突破性化学。特征被蚀刻到蚀刻层中，其蚀刻化学性质不同于控制层突破化学，其中控制层比蚀刻化学性质比保形层蚀刻更耐腐蚀。

17. 发明授权

US08361564B2 Protective layer for implant photoresist 有权
标题翻译：植入光刻胶的保护层
公开(公告)号：US08361564B2
公开(公告)日：2013-01-29
申请号：US12339514
申请日：2008-12-19
申请人： Andrew R. Romano , S. M. Reza Sadjadi
发明人： Andrew R. Romano , S. M. Reza Sadjadi
IPC分类号： C23C14/04 , C23C14/14 , C23C14/00
CPC分类号： H01L21/266 , G03F7/40 , H01L21/0273 , H01L21/26513
摘要： A method for implanting a dopant in a substrate is provided. A patterned photoresist mask is formed over the substrate, wherein the patterned photoresist mask has patterned photoresist mask features. A protective layer is deposited on the patterned photoresist mask by performing a cyclical deposition, wherein each cycle, comprises a depositing phase for depositing a deposition layer over surfaces of the patterned mask of photoresist material and a profile shaping phase for providing vertical sidewalls. A dopant is implanted into the substrate using an ion beam. The protective layer and photoresist mask are removed.
摘要翻译：提供了一种用于在衬底中注入掺杂剂的方法。图案化的光致抗蚀剂掩模形成在衬底上，其中图案化的光刻胶掩模具有图案化的光刻胶掩模特征。通过执行循环沉积，在图案化的光致抗蚀剂掩模上沉积保护层，其中每个循环包括用于在光致抗蚀剂材料的图案化掩模的表面上沉积沉积层的沉积相和用于提供垂直侧壁的轮廓成形阶段。使用离子束将掺杂剂注入到衬底中。去除保护层和光刻胶掩模。

18. 发明申请

US20120298301A1 MINIMIZATION OF MASK UNDERCUT ON DEEP ETCH 审中-公开
标题翻译：深层蚀刻掩蔽最小化
公开(公告)号：US20120298301A1
公开(公告)日：2012-11-29
申请号：US13572061
申请日：2012-08-10
申请人： Tamarak Pandhumsoporn , Patrick Chung , Jackie Seto , S. M. Reza Sadjadi
发明人： Tamarak Pandhumsoporn , Patrick Chung , Jackie Seto , S. M. Reza Sadjadi
IPC分类号： C23F1/08
CPC分类号： H01L21/3086 , H01L21/31138
摘要： A method for forming features in a silicon layer is provided. A mask is formed with a plurality of mask openings over the silicon layer. A polymer layer is deposited over the mask by flowing a hydrogen free deposition gas comprising C4F8, forming a plasma from the deposition gas, depositing a polymer from the plasma for at least 20 seconds, and stopping the depositing the polymer after the at least 20 seconds. The deposited polymer layer is opened by flowing an opening gas, forming a plasma from the opening gas which selectively removes the deposited polymer on bottoms of the plurality of mask openings with respect to deposited polymer on sides of the plurality of mask openings, and stopping the opening when at least some of the plurality of mask features are opened. The silicon layer is etched through the mask and deposited polymer layer.
摘要翻译：提供了一种在硅层中形成特征的方法。在硅层上形成有多个掩模开口的掩模。通过使包含C4F8的无氢沉积气体从沉积气体形成等离子体，从等离子体沉积聚合物至少20秒，并在至少20秒后停止沉积聚合物，沉积聚合物层。沉积的聚合物层通过流动开口气体而打开，从开口气体形成等离子体，其在多个掩模开口的侧面上相对于沉积的聚合物选择性地去除多个掩模开口的底部上沉积的聚合物，并且停止当多个掩模特征中的至少一些被打开时打开。通过掩模蚀刻硅层并沉积聚合物层。

19. 发明授权

US08187412B2 Apparatus for providing device with gaps for capacitance reduction 有权
标题翻译：用于为器件提供间隙以减少电容的装置
公开(公告)号：US08187412B2
公开(公告)日：2012-05-29
申请号：US12341568
申请日：2008-12-22
申请人： S. M. Reza Sadjadi , Zhi-Song Huang
发明人： S. M. Reza Sadjadi , Zhi-Song Huang
IPC分类号： C23F1/00 , H01L21/306 , C23C16/00
CPC分类号： H01L21/7682 , H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/76802 , H01L21/76843 , H01L23/4821 , H01L2924/0002 , H01L2924/00
摘要： A method for reducing capacitances between semiconductor devices is provided. A plurality of contact structures is formed in a dielectric layer. A mask is formed to cover the contact structures wherein the mask has mask features for exposing parts of the dielectric layer wherein the mask features have widths. The widths of the mask features are shrunk with a sidewall deposition. Gaps are etched into the dielectric layer through the sidewall deposition. The gaps are closed to form pockets in the gaps.
摘要翻译：提供一种用于降低半导体器件之间的电容的方法。在电介质层中形成多个接触结构。形成掩模以覆盖接触结构，其中掩模具有用于暴露电介质层的部分的掩模特征，其中掩模特征具有宽度。掩模特征的宽度随着侧壁沉积而收缩。间隙通过侧壁沉积蚀刻到介电层中。间隙封闭，形成缝隙。

20. 发明申请

US20090286397A1 SELECTIVE INDUCTIVE DOUBLE PATTERNING 审中-公开
标题翻译：选择性电感双重图案
公开(公告)号：US20090286397A1
公开(公告)日：2009-11-19
申请号：US12121711
申请日：2008-05-15
申请人： S. M. Reza Sadjadi
发明人： S. M. Reza Sadjadi
IPC分类号： H01L21/44 , C23C16/00
CPC分类号： C23C16/45523 , C23C16/505 , H01J37/321 , H01J37/3244 , H01J37/32449 , H01L21/0337 , H01L21/32139
摘要： An inductively coupled power (ICP) plasma processing chamber for forming semiconductor features is provided. A plasma processing chamber is provided, comprising a vacuum chamber, at least one antenna adjacent to the vacuum chamber for providing inductively coupled power in the vacuum chamber, a substrate support for supporting a silicon substrate within the plasma processing chamber, a pressure regulator, a gas inlet for providing gas into the plasma processing chamber, and a gas outlet for exhausting gas from the plasma processing chamber. A gas distribution system is in fluid connection with the gas inlet for providing a first gas and a second gas, wherein the gas distribution system can substantially replace one of the first gas and the second gas in the plasma zone with the other of the first gas and the second gas within a period of less than 5 seconds.
摘要翻译：提供一种用于形成半导体特征的电感耦合功率（ICP）等离子体处理室。提供了一种等离子体处理室，包括真空室，与真空室相邻的至少一个天线，用于在真空室中提供电感耦合功率，用于在等离子体处理室内支撑硅衬底的衬底支架，压力调节器，用于向等离子体处理室提供气体的气体入口和用于从等离子体处理室排出气体的气体出口。气体分配系统与气体入口流体连接，用于提供第一气体和第二气体，其中气体分配系统可以基本上替换等离子体区域中的第一气体和第二气体中的另一个，而第一气体和第二气体在小于5秒的时间内。

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