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11. 发明申请

US20060044057A1 Class-D amplifier having high order loop filtering 审中-公开
标题翻译：具有高阶环路滤波的D类放大器
公开(公告)号：US20060044057A1
公开(公告)日：2006-03-02
申请号：US10928528
申请日：2004-08-26
申请人： Rahmi Hezar , Baher Haroun , Brett Forejt , Srinath Ramaswamy
发明人： Rahmi Hezar , Baher Haroun , Brett Forejt , Srinath Ramaswamy
IPC分类号： H03F3/38
CPC分类号： H03F3/2173 , H03F1/34 , H03F3/217 , H03F2200/331
摘要： An amplifier having an active and passive gain stage connect to a load for driving a load according to a system analog input. A first embodiment of the amplifier in accordance with the present invention includes a logic network connected between a comparator network and a switching system, wherein the comparator network connects to the passive gain stage. Specifically, the active gain stage may include an active filter connected to receive an analog or digital input and provide a difference between the analog or digital input and the feedback signal relative to the gain factor of a gain unit connected to the active filter. The passive gain stage includes a passive filter. The logic network generates at least one switching signal which controls the switching system that includes at least one switching device to selectively provide power to the load. An output signal from the switching system provides output for the amplifier and is fed back to the active gain stage. In another embodiment, the output is a two-level signal and the passive and active filters are second order low pass filters, where the gain factor is about 25 or more. In yet another embodiment, the gain factor is approximately 250. Moreover, the amplifier may include a digital delta-sigma modulator connected to supply a two level input.
摘要翻译：具有有源和无源增益级的放大器根据系统模拟输入连接到用于驱动负载的负载。根据本发明的放大器的第一实施例包括连接在比较器网络和交换系统之间的逻辑网络，其中比较器网络连接到被动增益级。具体地，有源增益级可以包括连接到接收模拟或数字输入的有源滤波器，并且相对于连接到有源滤波器的增益单元的增益因子，提供模拟或数字输入与反馈信号之间的差异。被动增益级包括无源滤波器。逻辑网络生成至少一个切换信号，其控制包括至少一个开关装置的开关系统以选择性地向负载提供电力。来自开关系统的输出信号为放大器提供输出并反馈到有源增益级。在另一个实施例中，输出是两电平信号，无源和有源滤波器是二阶低通滤波器，其中增益因子约为25或更大。在另一个实施例中，增益因子为大约250.此外，放大器可以包括连接以提供两级输入的数字Δ-Σ调制器。

12. 发明授权

US06998910B2 Amplifier using delta-sigma modulation 有权
标题翻译：使用Δ-Σ调制的放大器
公开(公告)号：US06998910B2
公开(公告)日：2006-02-14
申请号：US10762819
申请日：2004-01-22
申请人： Rahmi Hezar , Baher Haroun
发明人： Rahmi Hezar , Baher Haroun
IPC分类号： H03F3/38
CPC分类号： H03F3/217 , H03F2200/331
摘要： An amplifier and a driver circuit therefor are presented for driving a load according to a system analog input. The amplifier comprises a passive delta-sigma modulator with a passive filter providing a first filtered signal according to a passive filter input and according to a feedback signal, a quantizer coupled with the passive filter and providing a quantized output according to the first filtered signal, and a switching system coupled with the the passive filter and the quantizer. The switching system selectively providing power to a load according to the quantized output and provides the feedback signal to the passive input, wherein a gain amplifier is provided in a feedback loop around the passive delta-sigma modulator.
摘要翻译：介绍放大器及其驱动电路，用于根据系统模拟输入驱动负载。该放大器包括无源Δ-Σ调制器，无源滤波器根据无源滤波器输入提供第一滤波信号，并根据反馈信号，与无源滤波器耦合的量化器，并根据第一滤波信号提供量化输出，以及与无源滤波器和量化器耦合的开关系统。开关系统根据量化的输出选择性地向负载提供电力，并将反馈信号提供给无源输入，其中增益放大器设置在无源Δ-Σ调制器周围的反馈回路中。

13. 发明授权

US08842046B2 Loop antenna 有权
标题翻译：环形天线
公开(公告)号：US08842046B2
公开(公告)日：2014-09-23
申请号：US13189135
申请日：2011-07-22
申请人： Eunyoung Seok , Brian P. Ginsburg , Baher Haroun , Srinath Ramaswamy , Vijay B. Rentala
发明人： Eunyoung Seok , Brian P. Ginsburg , Baher Haroun , Srinath Ramaswamy , Vijay B. Rentala
IPC分类号： H01Q7/00 , H01Q23/00 , H01Q1/38
CPC分类号： H01Q7/00 , H01Q23/00
摘要： A loop antenna is provided. The apparatus comprises a substrate, a first metallization layer, and a second metallization layer. The substrate has first and second feed terminals and a ground terminal. The first metallization layer is disposed over the substrate and includes a first window conductive region, a first conductive region, a second conductive region, and a third conductive region. The first conductive region is disposed over and is in electrical contact with the first feed terminal; it is also is substantially circular and located within the first window region. The second conductive region is disposed over and is in electrical contact with the second feed terminal; it is also substantially circular and is located within the first window region. The a third conductive region is disposed over and is in electrical contact with the ground terminal, and the third conductive region substantially surrounds the first window region. The second metallization layer is disposed over and is in electrical contact with the first, second, and third conductive regions of the first metallization layer, and the second metallization layer includes a second window region that is at least partially aligned with the first window region.
摘要翻译：提供环形天线。该装置包括基底，第一金属化层和第二金属化层。基板具有第一和第二馈电端子和接地端子。第一金属化层设置在衬底上，并且包括第一窗口导电区域，第一导电区域，第二导电区域和第三导电区域。第一导电区域设置在第一馈电端子上并与第一馈电端子电接触; 它也是基本圆形的并且位于第一窗口区域内。第二导电区域设置在第二馈电端子上并与第二馈电端子电接触; 它也基本上是圆形的并且位于第一窗口区域内。第三导电区域设置在接地端子之上并与接地端子电接触，并且第三导电区域基本上围绕第一窗口区域。第二金属化层设置在第一金属化层的第一，第二和第三导电区域之上并与第一金属化层的第一，第二和第三导电区域电接触，并且第二金属化层包括至少部分地与第一窗口区域对准的第二窗口区域。

14. 发明申请

US20130063291A1 EXCESS LOOP DELAY COMPENSATION FOR A CONTINUOUS TIME SIGMA DELTA MODULATOR 有权
标题翻译：用于连续时间信号调制器的循环延迟补偿
公开(公告)号：US20130063291A1
公开(公告)日：2013-03-14
申请号：US13229462
申请日：2011-09-09
申请人： Venkatesh Srinivasan , Patrick Satarzadeh , Victoria W. Limetkai , Baher Haroun , Marco Corsi
发明人： Venkatesh Srinivasan , Patrick Satarzadeh , Victoria W. Limetkai , Baher Haroun , Marco Corsi
IPC分类号： H03M3/02 , H03M1/00
CPC分类号： H03M3/37 , H03M3/424 , H03M3/454
摘要： A method and corresponding apparatus are provided. In operation, an analog signal is integrated with an integrator to generate an integrated analog signal. The integrated analog signal is compared, in synchronization with a first clock signal and a second clock signal, to a reference voltage with a plurality of comparators to generate a comparator output signal. A feedback current is then generated, in synchronization with the second clock signal, from the comparator output signal. The feedback current is fed back to at least one of the comparators, and the comparator output signal is latched in synchronization with the first clock signal to generate a latched output signal. This latched output signal is converted to a feedback analog signal, and a difference between the analog signal and the feedback analog signal is determined.
摘要翻译：提供了一种方法和相应的装置。在操作中，模拟信号与积分器集成以产生集成的模拟信号。将集成模拟信号与第一时钟信号和第二时钟信号同步地与多个比较器进行参考电压的比较，以产生比较器输出信号。然后与比较器输出信号产生与第二时钟信号同步的反馈电流。反馈电流被反馈到比较器中的至少一个，并且比较器输出信号与第一时钟信号同步地锁存以产生锁存的输出信号。该锁存的输出信号被转换为反馈模拟信号，并且确定模拟信号和反馈模拟信号之间的差。

15. 发明申请

US20130058329A1 WIRELESS ROUTER SYSTEM 有权
标题翻译：无线路由器系统
公开(公告)号：US20130058329A1
公开(公告)日：2013-03-07
申请号：US13226133
申请日：2011-09-06
申请人： Nirmal C. Warke , Brad Kramer , Hassan Ali , Swaminathan Sankaran , Baher Haroun , Srinath Hosur , Martin J. Izzard
发明人： Nirmal C. Warke , Brad Kramer , Hassan Ali , Swaminathan Sankaran , Baher Haroun , Srinath Hosur , Martin J. Izzard
IPC分类号： H04L12/50
CPC分类号： H04L12/50 , G06F13/4022 , Y02D10/14 , Y02D10/151
摘要： Conventional routers employ a wired backplane that employs “long reach” serializer/deserializer (SerDes) links, but this type of architecture is complicated, costly, and uses a considerable amount of power. To address some of these issues, a new wireless backplane architecture is provided here. This wireless backplane employs direct millimeter wave links between line cards that replaces the convention, wired switching fabric.
摘要翻译：常规路由器采用使用长距离串行器/解串器（SerDes）链路的有线背板，但是这种类型的架构是复杂的，昂贵的并且使用相当大的功率。为了解决其中的一些问题，这里提供了一种新的无线背板架构。该无线背板在线路卡之间采用直接毫米波链接，取代了常规，有线交换结构。

16. 发明申请

US20110092246A1 Asymmetric ESD Protection for FM Transmitter 有权
标题翻译： FM发射机的非对称ESD保护
公开(公告)号：US20110092246A1
公开(公告)日：2011-04-21
申请号：US12579451
申请日：2009-10-15
申请人： Brian P. Ginsburg , Yuanying Deng , Mehmet Ozgun , Baher Haroun , Francisco Ledesma
发明人： Brian P. Ginsburg , Yuanying Deng , Mehmet Ozgun , Baher Haroun , Francisco Ledesma
IPC分类号： H04M1/00 , H02H9/00
CPC分类号： H01L27/0255
摘要： Various apparatuses and methods for protecting a transmitter from electrostatic discharge are disclosed herein. For example, some embodiments provide an apparatus including a first ESD clamp connected to an antenna input, a first reactive component connected to the first ESD clamp, a second ESD clamp connected to the first reactive component, and a second reactive component connected between the second ESD clamp and the transmitter.
摘要翻译：本文公开了用于保护发射机免受静电放电的各种装置和方法。例如，一些实施例提供了一种装置，其包括连接到天线输入的第一ESD钳位，连接到第一ESD钳位的第一无功分量，连接到第一无功分量的第二ESD钳位，以及连接在第二ESD ESD钳位和变送器。

17. 发明授权

US07764210B2 System and method for converting an input signal 有权
标题翻译：用于转换输入信号的系统和方法
公开(公告)号：US07764210B2
公开(公告)日：2010-07-27
申请号：US11642133
申请日：2006-12-20
申请人： Vijaya B. Rentala , Baher Haroun , Bo Xia
发明人： Vijaya B. Rentala , Baher Haroun , Bo Xia
IPC分类号： H03M1/66
CPC分类号： H03H11/30 , H04N5/148
摘要： A video driver includes a current-to-voltage converter circuit that converts an analog input current to a corresponding analog voltage. Active termination circuitry is configured to synthesize an output impedance at an output thereof that substantially matches a load impedance to which the output is coupled, the active termination circuitry buffering the analog voltage to the output.
摘要翻译：视频驱动器包括将模拟输入电流转换为对应的模拟电压的电流 - 电压转换器电路。有源终端电路被配置为在其输出处合成输出阻抗，其基本上匹配输出耦合到的负载阻抗，有源终端电路将模拟电压缓冲到输出。

18. 发明申请

US20100148844A1 System And Method For Common Mode Translation 审中-公开
公开(公告)号：US20100148844A1
公开(公告)日：2010-06-17
申请号：US12711035
申请日：2010-02-23
申请人： Ayman A. Fayad , Russell Byrd , Baher Haroun
发明人： Ayman A. Fayad , Russell Byrd , Baher Haroun
IPC分类号： H03L5/00
CPC分类号： H03M3/488
摘要： System and method for common mode translation in continuous-time sigma-delta analog-to-digital converters. An embodiment includes a loop filter having an RC network coupled to a differential signal input, a Gm-C/Quantizer/DAC circuit (GQD) coupled to the loop filter, a common-mode level adjust circuit coupled to signal inputs of the GQD, and a tuning circuit coupled to the GQD and the common-mode level adjust circuit. The GQD evaluates an input signal provided by the RC network, computes a difference between a filtered input signal and the feedback quantization signal to generate an error signal, measures the error signal, and compensates for the error signal with sigma-delta noise-shaping. The common-mode level adjust circuit alters a common-mode level of a differential input signal to be substantially equal to a desired common-mode level and the tuning circuit provides a compensation voltage to the common-mode level adjust circuit based on a difference between the common-mode levels.

19. 发明授权

US07586357B2 Systems for providing a constant resistance 有权
标题翻译：提供恒定电阻的系统
公开(公告)号：US07586357B2
公开(公告)日：2009-09-08
申请号：US11653037
申请日：2007-01-12
申请人： Vijaya B. Rentala , Baher Haroun
发明人： Vijaya B. Rentala , Baher Haroun
IPC分类号： H03K5/08
CPC分类号： H03H11/24
摘要： A system for providing a desired substantially constant resistance includes a first transistor interconnected between a first node and a second node. The system also includes a second transistor, the second transistor being diode connected, the first transistor and the second transistor forming a current mirror. A voltage divider is coupled to provide a portion of a voltage associated with the first transistor to the second transistor, the voltage divider being configured parallel to the first transistor to provide a substantially constant resistance between the first node and the second node. A current source is coupled to the second transistor, the current source being controlled to draw an amount of current through the second transistor to set the substantially constant resistance substantially equal to the desired substantially constant resistance.
摘要翻译：用于提供期望的基本上恒定的电阻的系统包括在第一节点和第二节点之间互连的第一晶体管。该系统还包括第二晶体管，第二晶体管被二极管连接，第一晶体管和第二晶体管形成电流镜。耦合分压器以将与第一晶体管相关联的电压的一部分提供给第二晶体管，该分压器被配置成与第一晶体管并联，以在第一节点和第二节点之间提供基本恒定的电阻。电流源耦合到第二晶体管，电流源被控制以画出通过第二晶体管的电流量，以将基本上恒定的电阻设置为基本上等于期望的基本上恒定的电阻。

20. 发明申请

US20070180341A1 TAP AND LINKING MODULE FOR SCAN ACCESS OF MULTIPLE CORES WITH IEEE 1149.1 TEST ACCESS PORTS 有权
标题翻译：用于IEEE 1149.1测试访问端口的多个光纤扫描接入的TAP和链接模块
公开(公告)号：US20070180341A1
公开(公告)日：2007-08-02
申请号：US11691600
申请日：2007-03-27
申请人： Baher Haroun , Lee Whetsel
发明人： Baher Haroun , Lee Whetsel
IPC分类号： G01R31/28
CPC分类号： G01R31/3177 , G01R31/2851 , G01R31/318536 , G01R31/318544 , G01R31/318555 , G01R31/318558 , G11C29/46
摘要： An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.
摘要翻译：描述了用于在集成电路上测试多个电路的架构。该架构包括位于集成电路的测试引脚之间的TAP链接模块和待测试的多个电路的1149.1测试访问端口（TAP）。 TAP链接模块响应来自连接到测试引脚的测试仪的1149.1扫描操作，以选择性地在1149.1 TAP之间切换，以使测试仪和多个电路之间能够进行测试。 TAP链接模块的1149.1 TAP切换操作基于增加1149.1指令模式，以附加TAP链接模块用于执行TAP切换操作的附加位或位信息。

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