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1. 发明申请

US20130058329A1 WIRELESS ROUTER SYSTEM 有权
标题翻译：无线路由器系统
公开(公告)号：US20130058329A1
公开(公告)日：2013-03-07
申请号：US13226133
申请日：2011-09-06
申请人： Nirmal C. Warke , Brad Kramer , Hassan Ali , Swaminathan Sankaran , Baher Haroun , Srinath Hosur , Martin J. Izzard
发明人： Nirmal C. Warke , Brad Kramer , Hassan Ali , Swaminathan Sankaran , Baher Haroun , Srinath Hosur , Martin J. Izzard
IPC分类号： H04L12/50
CPC分类号： H04L12/50 , G06F13/4022 , Y02D10/14 , Y02D10/151
摘要： Conventional routers employ a wired backplane that employs “long reach” serializer/deserializer (SerDes) links, but this type of architecture is complicated, costly, and uses a considerable amount of power. To address some of these issues, a new wireless backplane architecture is provided here. This wireless backplane employs direct millimeter wave links between line cards that replaces the convention, wired switching fabric.
摘要翻译：常规路由器采用使用长距离串行器/解串器（SerDes）链路的有线背板，但是这种类型的架构是复杂的，昂贵的并且使用相当大的功率。为了解决其中的一些问题，这里提供了一种新的无线背板架构。该无线背板在线路卡之间采用直接毫米波链接，取代了常规，有线交换结构。

2. 发明授权

US09240900B2 Wireless router system 有权
标题翻译：无线路由器系统
公开(公告)号：US09240900B2
公开(公告)日：2016-01-19
申请号：US13226133
申请日：2011-09-06
申请人： Nirmal C. Warke , Brad Kramer , Hassan Ali , Swaminathan Sankaran , Baher Haroun , Srinath Hosur , Martin J. Izzard
发明人： Nirmal C. Warke , Brad Kramer , Hassan Ali , Swaminathan Sankaran , Baher Haroun , Srinath Hosur , Martin J. Izzard
IPC分类号： H04L12/50
CPC分类号： H04L12/50 , G06F13/4022 , Y02D10/14 , Y02D10/151
摘要： Conventional routers employ a wired backplane that employs “long reach” serializer/deserializer (SerDes) links, but this type of architecture is complicated, costly, and uses a considerable amount of power. To address some of these issues, a new wireless backplane architecture is provided here. This wireless backplane employs direct millimeter wave links between line cards that replaces the convention, wired switching fabric.
摘要翻译：常规路由器采用采用“长距离”串行器/解串器（SerDes）链路的有线背板，但是这种类型的架构是复杂的，昂贵的并且使用相当大的功率。为了解决其中的一些问题，这里提供了一种新的无线背板架构。该无线背板在线路卡之间采用直接毫米波链接，取代了常规，有线交换结构。

3. 发明授权

US08842046B2 Loop antenna 有权
标题翻译：环形天线
公开(公告)号：US08842046B2
公开(公告)日：2014-09-23
申请号：US13189135
申请日：2011-07-22
申请人： Eunyoung Seok , Brian P. Ginsburg , Baher Haroun , Srinath Ramaswamy , Vijay B. Rentala
发明人： Eunyoung Seok , Brian P. Ginsburg , Baher Haroun , Srinath Ramaswamy , Vijay B. Rentala
IPC分类号： H01Q7/00 , H01Q23/00 , H01Q1/38
CPC分类号： H01Q7/00 , H01Q23/00
摘要： A loop antenna is provided. The apparatus comprises a substrate, a first metallization layer, and a second metallization layer. The substrate has first and second feed terminals and a ground terminal. The first metallization layer is disposed over the substrate and includes a first window conductive region, a first conductive region, a second conductive region, and a third conductive region. The first conductive region is disposed over and is in electrical contact with the first feed terminal; it is also is substantially circular and located within the first window region. The second conductive region is disposed over and is in electrical contact with the second feed terminal; it is also substantially circular and is located within the first window region. The a third conductive region is disposed over and is in electrical contact with the ground terminal, and the third conductive region substantially surrounds the first window region. The second metallization layer is disposed over and is in electrical contact with the first, second, and third conductive regions of the first metallization layer, and the second metallization layer includes a second window region that is at least partially aligned with the first window region.
摘要翻译：提供环形天线。该装置包括基底，第一金属化层和第二金属化层。基板具有第一和第二馈电端子和接地端子。第一金属化层设置在衬底上，并且包括第一窗口导电区域，第一导电区域，第二导电区域和第三导电区域。第一导电区域设置在第一馈电端子上并与第一馈电端子电接触; 它也是基本圆形的并且位于第一窗口区域内。第二导电区域设置在第二馈电端子上并与第二馈电端子电接触; 它也基本上是圆形的并且位于第一窗口区域内。第三导电区域设置在接地端子之上并与接地端子电接触，并且第三导电区域基本上围绕第一窗口区域。第二金属化层设置在第一金属化层的第一，第二和第三导电区域之上并与第一金属化层的第一，第二和第三导电区域电接触，并且第二金属化层包括至少部分地与第一窗口区域对准的第二窗口区域。

4. 发明授权

US08483856B2 System and method for correcting phase noise in digital-to-analog converter or analog-to-digital converter 有权
标题翻译：用于校正数模转换器或模数转换器中的相位噪声的系统和方法
公开(公告)号：US08483856B2
公开(公告)日：2013-07-09
申请号：US12783290
申请日：2010-05-19
申请人： Rahmi Hezar , Baher Haroun
发明人： Rahmi Hezar , Baher Haroun
IPC分类号： G06F17/00
CPC分类号： H03M3/372 , H03M3/50
摘要： A circuit includes a digital oscillator, a phase lock loop (PLL), a digital signal generator, a correction circuit and a digital-to-analog converter DAC (DAC). The digital oscillator can output a reference clock signal. The PLL can output a system clock signal based on the reference clock signal. The digital signal generator can output a digital signal based on the system clock signal. The correction circuit can output a pre-distorted signal based on the reference clock signal, the system clock signal and the digital signal. The DAC can output an analog signal based on the pre-distorted signal and the system clock signal.
摘要翻译：电路包括数字振荡器，锁相环（PLL），数字信号发生器，校正电路和数模转换器DAC（DAC）。数字振荡器可以输出参考时钟信号。 PLL可以基于参考时钟信号输出系统时钟信号。数字信号发生器可以根据系统时钟信号输出数字信号。校正电路可以基于参考时钟信号，系统时钟信号和数字信号输出预失真信号。 DAC可以根据预失真信号和系统时钟信号输出模拟信号。

5. 发明申请

US20130063291A1 EXCESS LOOP DELAY COMPENSATION FOR A CONTINUOUS TIME SIGMA DELTA MODULATOR 有权
标题翻译：用于连续时间信号调制器的循环延迟补偿
公开(公告)号：US20130063291A1
公开(公告)日：2013-03-14
申请号：US13229462
申请日：2011-09-09
申请人： Venkatesh Srinivasan , Patrick Satarzadeh , Victoria W. Limetkai , Baher Haroun , Marco Corsi
发明人： Venkatesh Srinivasan , Patrick Satarzadeh , Victoria W. Limetkai , Baher Haroun , Marco Corsi
IPC分类号： H03M3/02 , H03M1/00
CPC分类号： H03M3/37 , H03M3/424 , H03M3/454
摘要： A method and corresponding apparatus are provided. In operation, an analog signal is integrated with an integrator to generate an integrated analog signal. The integrated analog signal is compared, in synchronization with a first clock signal and a second clock signal, to a reference voltage with a plurality of comparators to generate a comparator output signal. A feedback current is then generated, in synchronization with the second clock signal, from the comparator output signal. The feedback current is fed back to at least one of the comparators, and the comparator output signal is latched in synchronization with the first clock signal to generate a latched output signal. This latched output signal is converted to a feedback analog signal, and a difference between the analog signal and the feedback analog signal is determined.
摘要翻译：提供了一种方法和相应的装置。在操作中，模拟信号与积分器集成以产生集成的模拟信号。将集成模拟信号与第一时钟信号和第二时钟信号同步地与多个比较器进行参考电压的比较，以产生比较器输出信号。然后与比较器输出信号产生与第二时钟信号同步的反馈电流。反馈电流被反馈到比较器中的至少一个，并且比较器输出信号与第一时钟信号同步地锁存以产生锁存的输出信号。该锁存的输出信号被转换为反馈模拟信号，并且确定模拟信号和反馈模拟信号之间的差。

6. 发明申请

US20120286868A1 CLASS D POWER AMPLIFIER 有权
标题翻译： CLASS D功率放大器
公开(公告)号：US20120286868A1
公开(公告)日：2012-11-15
申请号：US13106611
申请日：2011-05-12
申请人： Baher Haroun , Joonhoi Hur , Lei Ding , Rahmi Hezar
发明人： Baher Haroun , Joonhoi Hur , Lei Ding , Rahmi Hezar
IPC分类号： H03F3/217
CPC分类号： H03F3/2173 , H03F1/26 , H03F2200/267 , H03F2200/297
摘要： A class D power amplifier (PA) is provided. The PA generally comprises a driver, output capacitor, a matching network, and a cancellation circuit. The driver has an input, an output, and a parasitic capacitance, and the input of the driver is configured to receive complementary first and second radio frequency (RF) signals, where there is a free-fly interval between consecutive pulses from the first and second RF signals. The output capacitor and cancellation circuit are each coupled to the output of the driver such that the cancellation circuit provides harmonic restoration at least during the free-fly interval, and the matching network is coupled to the output capacitor.
摘要翻译：提供D类功率放大器（PA）。 PA通常包括驱动器，输出电容器，匹配网络和消除电路。驱动器具有输入，输出和寄生电容，并且驱动器的输入被配置为接收互补的第一和第二射频（RF）信号，其中在来自第一和第二射频的连续脉冲之间存在自由间隔第二RF信号。输出电容器和消除电路各自耦合到驱动器的输出，使得消除电路至少在空闲间隔期间提供谐波恢复，并且匹配网络耦合到输出电容器。

7. 发明申请

US20110285433A1 SYSTEM AND METHOD FOR CORRECTING PHASE NOISE IN DIGITAL-TO-ANALOG CONVERTER OR ANALOG-TO-DIGITAL CONVERTER 有权
标题翻译：用于校正数字到模拟转换器或模拟数字转换器中的相位噪声的系统和方法
公开(公告)号：US20110285433A1
公开(公告)日：2011-11-24
申请号：US12783290
申请日：2010-05-19
申请人： Rahmi Hezar , Baher Haroun
发明人： Rahmi Hezar , Baher Haroun
IPC分类号： H03L7/08
CPC分类号： H03M3/372 , H03M3/50
摘要： A circuit includes a digital oscillator, a phase lock loop (PLL), a digital signal generator, a correction circuit and a digital-to-analog converter DAC (DAC). The digital oscillator can output a reference clock signal. The PLL can output a system clock signal based on the reference clock signal. The digital signal generator can output a digital signal based on the system clock signal. The correction circuit can output a pre-distorted signal based on the reference clock signal, the system clock signal and the digital signal. The DAC can output an analog signal based on the pre-distorted signal and the system clock signal.
摘要翻译：电路包括数字振荡器，锁相环（PLL），数字信号发生器，校正电路和数模转换器DAC（DAC）。数字振荡器可以输出参考时钟信号。 PLL可以基于参考时钟信号输出系统时钟信号。数字信号发生器可以根据系统时钟信号输出数字信号。校正电路可以基于参考时钟信号，系统时钟信号和数字信号输出预失真信号。 DAC可以根据预失真信号和系统时钟信号输出模拟信号。

8. 发明申请

US20110092246A1 Asymmetric ESD Protection for FM Transmitter 有权
标题翻译： FM发射机的非对称ESD保护
公开(公告)号：US20110092246A1
公开(公告)日：2011-04-21
申请号：US12579451
申请日：2009-10-15
申请人： Brian P. Ginsburg , Yuanying Deng , Mehmet Ozgun , Baher Haroun , Francisco Ledesma
发明人： Brian P. Ginsburg , Yuanying Deng , Mehmet Ozgun , Baher Haroun , Francisco Ledesma
IPC分类号： H04M1/00 , H02H9/00
CPC分类号： H01L27/0255
摘要： Various apparatuses and methods for protecting a transmitter from electrostatic discharge are disclosed herein. For example, some embodiments provide an apparatus including a first ESD clamp connected to an antenna input, a first reactive component connected to the first ESD clamp, a second ESD clamp connected to the first reactive component, and a second reactive component connected between the second ESD clamp and the transmitter.
摘要翻译：本文公开了用于保护发射机免受静电放电的各种装置和方法。例如，一些实施例提供了一种装置，其包括连接到天线输入的第一ESD钳位，连接到第一ESD钳位的第一无功分量，连接到第一无功分量的第二ESD钳位，以及连接在第二ESD ESD钳位和变送器。

9. 发明授权

US07764210B2 System and method for converting an input signal 有权
标题翻译：用于转换输入信号的系统和方法
公开(公告)号：US07764210B2
公开(公告)日：2010-07-27
申请号：US11642133
申请日：2006-12-20
申请人： Vijaya B. Rentala , Baher Haroun , Bo Xia
发明人： Vijaya B. Rentala , Baher Haroun , Bo Xia
IPC分类号： H03M1/66
CPC分类号： H03H11/30 , H04N5/148
摘要： A video driver includes a current-to-voltage converter circuit that converts an analog input current to a corresponding analog voltage. Active termination circuitry is configured to synthesize an output impedance at an output thereof that substantially matches a load impedance to which the output is coupled, the active termination circuitry buffering the analog voltage to the output.
摘要翻译：视频驱动器包括将模拟输入电流转换为对应的模拟电压的电流 - 电压转换器电路。有源终端电路被配置为在其输出处合成输出阻抗，其基本上匹配输出耦合到的负载阻抗，有源终端电路将模拟电压缓冲到输出。

10. 发明申请

US20100148844A1 System And Method For Common Mode Translation 审中-公开
公开(公告)号：US20100148844A1
公开(公告)日：2010-06-17
申请号：US12711035
申请日：2010-02-23
申请人： Ayman A. Fayad , Russell Byrd , Baher Haroun
发明人： Ayman A. Fayad , Russell Byrd , Baher Haroun
IPC分类号： H03L5/00
CPC分类号： H03M3/488
摘要： System and method for common mode translation in continuous-time sigma-delta analog-to-digital converters. An embodiment includes a loop filter having an RC network coupled to a differential signal input, a Gm-C/Quantizer/DAC circuit (GQD) coupled to the loop filter, a common-mode level adjust circuit coupled to signal inputs of the GQD, and a tuning circuit coupled to the GQD and the common-mode level adjust circuit. The GQD evaluates an input signal provided by the RC network, computes a difference between a filtered input signal and the feedback quantization signal to generate an error signal, measures the error signal, and compensates for the error signal with sigma-delta noise-shaping. The common-mode level adjust circuit alters a common-mode level of a differential input signal to be substantially equal to a desired common-mode level and the tuning circuit provides a compensation voltage to the common-mode level adjust circuit based on a difference between the common-mode levels.

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