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11. 发明申请

WO2015113046A1 IMPLEMENTING ACCESS CONTROL BY SYSTEM-ON-CHIP 审中-公开
标题翻译：通过系统芯片实现访问控制
公开(公告)号：WO2015113046A1
公开(公告)日：2015-07-30
申请号：PCT/US2015/013095
申请日：2015-01-27
申请人： RAMBUS INC.
发明人： HAMPEL, Craig, E. , CIORANESCO, Jean-Michel , PORTELLA DO CANTO, Rodrigo , OZARI DE ALMEIDA, Guilherme
IPC分类号： G06F21/44
CPC分类号： G06F21/6218 , G06F21/44 , G06F21/57 , G06F21/755 , G06F21/85 , H04L63/0227 , H04L63/06 , H04L63/08 , H04L63/0876 , H04L63/101 , H04L63/123
摘要： Systems and methods for implementing access control by systems-on-chip (SoCs). An example SoC may comprise: an access control unit comprising a secure memory for storing access control data, the access control unit to: receive a message comprising an access control data item; store the access control data item in the secure memory; perform at least one of: authenticating the message using a message digest function, or validating contents of the secure memory by comparing a stored reference value with a calculated value of a message digest function of the contents of the secure memory; and control, in view of the access control data item, access by an initiator device to a target device.
摘要翻译：通过片上系统（SoC）实现访问控制的系统和方法。示例SoC可以包括：访问控制单元，包括用于存储访问控制数据的安全存储器，所述访问控制单元用于：接收包括访问控制数据项的消息; 将访问控制数据项存储在安全存储器中; 执行以下至少之一：使用消息摘要功能认证所述消息，或者通过将所存储的参考值与所述安全存储器的内容的消息摘要功能的计算值进行比较来验证所述安全存储器的内容; 并且鉴于访问控制数据项，控制启动器设备到目标设备的访问。

12. 发明申请

WO2016089563A1 HIGH PERFORMANCE, HIGH CAPACITY MEMORY SYSTEMS AND MODULES 审中-公开
标题翻译：高性能，高容量存储系统和模块
公开(公告)号：WO2016089563A1
公开(公告)日：2016-06-09
申请号：PCT/US2015/060057
申请日：2015-11-11
申请人： RAMBUS INC.
发明人： WARE, Frederick, A. , TSERN, Ely , LINSTADT, John, Eric , GIOVANNINI, Thomas, J. , HAMPEL, Craig, E. , BEST, Scott, C. , YAN, John
IPC分类号： G06F13/16 , G11C7/10
CPC分类号： G06F13/1678 , G06F13/1673 , G06F13/1694
摘要： Described are motherboards with memory-module sockets that accept legacy memory modules for backward compatibility, or accept a greater number of configurable modules in support of increased memory capacity. The configurable modules can be backward compatible with legacy motherboards. Equipped with the configurable modules, the motherboards support memory systems with high signaling rates and capacities.
摘要翻译：描述的是具有内存模块插槽的主板，它们接受传统内存模块以实现向后兼容，或接受更多数量的可配置模块以支持增加的内存容量。可配置模块可以与传统主板向后兼容。配有可配置模块，主板支持高信令速率和容量的内存系统。

13. 发明申请

WO2003084067A2 SYSTEM WITH DUAL RAIL REGULATED LOCKED LOOP 审中-公开
标题翻译：具有双轨调节闭环的系统
公开(公告)号：WO2003084067A2
公开(公告)日：2003-10-09
申请号：PCT/US2003/008873
申请日：2003-03-20
申请人： RAMBUS, INC.
发明人： KIZER, Jade, M. , LAU, Benedict, C. , HAMPEL, Craig, E.
IPC分类号： H03L7/099
CPC分类号： H03L7/0805 , G06F1/10 , H03K5/135 , H03K2005/00052 , H03L7/07 , H03L7/0814

14. 发明申请

WO2003036445A1 TIMING CALIBRATION APPARATUS AND METHOD FOR A MEMORY DEVICE SIGNALING SYSTEM 审中-公开
标题翻译：用于记忆装置信号系统的时序校准装置和方法
公开(公告)号：WO2003036445A1
公开(公告)日：2003-05-01
申请号：PCT/US2002/033707
申请日：2002-10-22
申请人： RAMBUS INC.
发明人： HAMPEL, Craig, E. , PEREGO, Richard, E. , SIDIROPOULOS, Stephanos, S. , TSERN, Ely, K. , WARE, Fredrick, A.
IPC分类号： G06F1/12
CPC分类号： G11C11/4076 , G06F3/061 , G06F3/0629 , G06F3/0671 , G06F12/0246 , G11C7/10 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C7/22 , G11C7/222 , G11C11/40611 , G11C11/4072 , G11C11/4078 , G11C11/4093 , G11C21/00 , G11C2207/2254 , H04L7/0025 , H04L7/0079 , H04L7/0091
摘要： A memory system includes a memory controller (405) and a memory component (410) coupled to each other. An interface of the memory component (410) is configured to receive a first signal from the memory controller (410) with read request information, retrieve the read data information (410) from the memory core in response to the request information, and transmit to the memory controller (410) a second signal containing the read data information. The read data information includes read data symbols, where the average duration of the read data symbols, measured at the interface, defines a symbol time interval. A first external access time is measured at the interface between a first read request and read data transmitted by the interface in response to the first read request. A second external access time interval is measured at the interface between a second read request and read data transmitted by the interface in response to the second read request. The difference between the first external access time and the second external access time is greater than one-half of the symbol time interval.
摘要翻译：存储器系统包括彼此耦合的存储器控制器（405）和存储器组件（410）。存储器组件（410）的接口被配置为用读取请求信息从存储器控制器（410）接收第一信号，响应于请求信息从存储器核心检索读取的数据信息（410），并且发送到存储器控制器（410）包含读取的数据信息的第二信号。读数据信息包括读数据符号，其中在接口处测量的读数据符号的平均持续时间定义符号时间间隔。在第一读取请求和由接口响应于第一读取请求而发送的读取数据之间的接口处测量第一外部访问时间。第二外部访问时间间隔在响应于第二读取请求的第二读取请求和由接口发送的读取数据之间的接口处被测量。第一外部访问时间和第二外部访问时间之间的差异大于符号时间间隔的一半。

15. 发明申请

WO2022187089A1 MODULE AUTHENTICATION 审中-公开
公开(公告)号：WO2022187089A1
公开(公告)日：2022-09-09
申请号：PCT/US2022/017883
申请日：2022-02-25
申请人： RAMBUS INC.
发明人： BEST, Scott, C. , VOGELSANG, Thomas , HAMBURG, Michael, Alexander , MARSON, Mark, Evan , HANDSCHUH, Helena , HAMPEL, Craig, E. , WRIGHT, Kenneth, Lee
IPC分类号： G06F21/72 , G06F21/78 , G06F21/79
摘要： An asymmetric key cryptographic system is used to generate a cryptographic certificate for authenticating a memory module. This certificate is generated based on information, readable by the authenticator (e.g., host system), from at least one device on the memory module that is not read in order to obtain the certificate. For example, the certificate for authenticating a module may be stored in the nonvolatile memory of a serial presence detect device. The certificate itself, however, is based at least in part on information read from at least one other device on the memory module. Examples of this other device include a registering clock driver, DRAM device(s), and/or data buffer device(s). In an embodiment, the information read from a device (e.g., DRAM) may be based on one or more device fmgerprint(s) derived from physical variations that occur naturally, and inevitably, during integrated circuit manufacturing.

16. 发明申请

WO2020197925A1 MULTIPLE PRECISION MEMORY SYSTEM 审中-公开
公开(公告)号：WO2020197925A1
公开(公告)日：2020-10-01
申请号：PCT/US2020/023584
申请日：2020-03-19
申请人： RAMBUS INC.
发明人： VOGELSANG, Thomas , HAMPEL, Craig, E.
IPC分类号： G06F13/14 , G06F13/28 , G06F13/16 , G06F12/02
摘要： Space in a memory is allocated based on the highest used precision. When the maximum used precision is not being used, the bits required for that particular precision level (e.g., floating point format) are transferred between the processor and the memory while the rest are not. A given floating point number is distributed over non-contiguous addresses. Each portion of the given floating point number is located at the same offset within the access units, groups, and/or memory arrays. This allows a sequencer in the memory device to successively access a precision dependent number of access units, groups, and/or memory arrays without receiving additional requests over the memory channel.

17. 发明申请

WO2003084066A2 SYSTEM WITH PHASE JUMPING LOCKED LOOP CIRCUIT 审中-公开
标题翻译：具有相位锁定环路电路的系统
公开(公告)号：WO2003084066A2
公开(公告)日：2003-10-09
申请号：PCT/US2003/008872
申请日：2003-03-20
申请人： RAMBUS, INC
发明人： KIZER, Jade, M. , LAU, Benedict, C. , VU, Roxanne, T. , HAMPEL, Craig, E. , NGUYEN, Huy, M. , YU, Leung , CHOU, Adam, Chuen-Huei
IPC分类号： H03L7/099
CPC分类号： H03L7/0805 , G06F1/10 , H03L7/07 , H03L7/0814

18. 发明申请

WO2003036850A1 PHASE ADJUSTMENT APPARATUS AND METHOD FOR A MEMORY DEVICE SIGNALING SYSTEM 审中-公开
标题翻译：用于存储器件信号系统的相位调整装置和方法
公开(公告)号：WO2003036850A1
公开(公告)日：2003-05-01
申请号：PCT/US2002/033706
申请日：2002-10-22
申请人： RAMBUS INC.
发明人： HAMPEL, Craig, E. , PEREGO, Richard, E. , SIDIROPOULOS, Stephanos, S. , TSERN, Ely, K. , WARE, Fredrick, A.
IPC分类号： H04L5/16
CPC分类号： G11C11/4076 , G06F3/061 , G06F3/0629 , G06F3/0671 , G06F12/0246 , G11C7/10 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C7/22 , G11C7/222 , G11C11/40611 , G11C11/4072 , G11C11/4078 , G11C11/4093 , G11C21/00 , G11C2207/2254 , H04L7/0025 , H04L7/0079 , H04L7/0091
摘要： Apparatus and methods are disclosed for adjusting phase of data signals to compensate for phase offset variations between devices during normal operation. The phase of data signals are adjusted individually in each transmit data unit and receive data unit across multiple data slices with a common set of phase vector clock signals and a corresponding clock cycle count signal. The transmission of signal information between a first device (such as a memory controller) (205) and a second device (such as a memory component) (210) occurs without errors even when the accumulated delays between the first device and second device change by a half symbol time interval or more during operation of the system. The apparatus reduces the circuitry required, such as phase-lock-loops (255), for individually adjusting the phase of each transmit data unit and receive data unit across multiple data slices, which in turn results in reduction in complexity and cost of the system.
摘要翻译：公开了用于调整数据信号的相位以补偿正常操作期间设备之间的相位偏移变化的装置和方法。数据信号的相位在每个发送数据单元中单独调整，并且通过一组公共的相位矢量时钟信号和相应的时钟周期计数信号在多个数据切片之间接收数据单元。即使当第一设备和第二设备之间的累积延迟在半符号时间间隔期间或更长时间期间，在诸如存储器控制器205的第一设备和诸如存储器组件210的第二设备之间的信号信息的传输也不会发生错误系统的操作。该装置减少了所需的电路，例如锁相环255，用于单独调整每个发射数据单元的相位并在多个数据片之间接收数据单元，这又导致系统的复杂性和成本的降低。

19. 发明申请

WO1997042557A2 ASYNCHRONOUS REQUEST/SYNCHRONOUS DATA DYNAMIC RANDOM ACCESS MEMORY 审中-公开
标题翻译：异步请求/同步数据动态随机存取
公开(公告)号：WO1997042557A2
公开(公告)日：1997-11-13
申请号：PCT/US1997007463
申请日：1997-05-01
申请人： RAMBUS, INC.
发明人： RAMBUS, INC. , BARTH, Richard, M. , HOROWITZ, Mark, A. , HAMPEL, Craig, E. , WARE, Frederick, A.
IPC分类号： G06F00/00
CPC分类号： G11C7/222 , G06F13/16 , G11C7/1045 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/22 , G11C8/18 , Y02D10/14
摘要： A method and system for transferring information within a computer system is provided. The system includes a memory device that has a lower power mode in which data transfer circuitry is not driven by a clock signal, and a higher power mode in which data transfer circuitry is driven by a clock signal. The system further includes a memory controller that sends control signals to the memory device to initiate a data transfer transaction. The memory device receives the control signals asynchronously, and assumes the second mode in response to one of the control signals. While the memory device is in the second mode, the memory controller sends a control signal to identify a particular clock cycle. The memory device synchronously transfers the data. The memory device determines when to begin the data transfer based on the identified clock cycle and the type of data transfer that has been specified.
摘要翻译：提供了一种用于在计算机系统内传送信息的方法和系统。该系统包括具有较低功率模式的存储器件，其中数据传输电路不由时钟信号驱动，并且其中数据传输电路由时钟信号驱动的较高功率模式。该系统还包括存储器控制器，其向控制信号发送控制信号以发起数据传输交易。存储器装置异步地接收控制信号，并且响应于一个控制信号而呈现第二模式。当存储器件处于第二模式时，存储器控制器发送控制信号以识别特定的时钟周期。存储设备同步传输数据。存储器件基于所识别的时钟周期和指定的数据传输的类型确定何时开始数据传输。

20. 发明授权

EP1151387B2 APPARATUS AND METHOD FOR TOPOGRAPHY DEPENDENT SIGNALING 有权
标题翻译： GERÄTUND VERFAHREN UM VON DER TOPOGRAFIEABHÄNGIGZU SIGNALISIEREN
公开(公告)号：EP1151387B2
公开(公告)日：2014-07-23
申请号：EP00975263.5
申请日：2000-10-16
申请人： Rambus Inc.
发明人： HOROWITZ, Mark, A. , BARTH, Richard M. , HAMPEL, Craig, E. , MONCAYO, Alfredo , DONNELLY, Kevin, S. , ZERBE, Jared, L.
IPC分类号： G06F13/14 , H03K19/0175
CPC分类号： G06F13/4291 , G06F3/061 , G06F3/0611 , G06F3/0619 , G06F3/0658 , G06F3/0661 , G06F3/0679 , G06F3/0688 , G06F12/0246 , G06F12/1081 , G06F13/102 , G06F13/1689 , G06F13/364 , G06F13/4072 , G06F13/4086 , G06F13/4234 , G06F13/4243 , G06F2206/1014 , G06F2212/7201 , G11C5/04 , G11C5/063 , G11C7/1048 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C16/32 , G11C19/00 , H03K19/00384 , H03K19/018585
摘要： Bus communications are optimized by adjusting signal characteristics in accordance with one or more topography dependent parameters. In a bus transmitter a transmit signal characteristic is adjusted in accordance with a topography dependent parameter. A port in the bus transmitter receives the topograpy dependent parameter for later use by the parameter adjustment circuitry. The parameter adjustment circuitry adjusts a parameter control signal in accordance with the topography dependent parameter, which is coupled to the out-put driver. Prior to driving an output signal onto a bus, the output driver adjusts the transmit signal characteristics in accordance with the parameter control signal. In a bus receiver, a receive signal characteristic is also adjusted in accordance with a topography dependent parameter. A port associated with the bus receiver receives the topography dependent parameter and stores it in a register. Parameter adjustment circuitry adjusts a control signal in accordance with the stored topography dependent parameter. An input buffer receives an input signal from a bus coupling the receiver to a transmitter of the input signal. The input buffer generates a first signal from the input signal by adjusting a parameter of the input signal in accordance with the control signal.
摘要翻译：通过根据一个或多个地形相关参数调整信号特性来优化总线通信。在总线发射机中，发射信号特性根据地形相关参数进行调整。总线发射机中的一个端口接收参数调整电路以供以后使用的地理学依赖参数。参数调整电路根据与输出驱动器耦合的地形相关参数来调整参数控制信号。在将输出信号驱动到总线之前，输出驱动器根据参数控制信号调整发送信号特性。在总线接收机中，接收信号特性也根据地形相关参数进行调整。与总线接收器相关联的端口接收地形相关参数并将其存储在寄存器中。参数调整电路根据所存储的地形相关参数调整控制信号。输入缓冲器接收来自将接收器耦合到输入信号的发射器的总线的输入信号。输入缓冲器根据控制信号通过调节输入信号的参数从输入信号产生第一信号。

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