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11. 发明授权

US07842554B2 VLSI hot-spot minimization using nanotubes 失效
标题翻译：使用纳米管的VLSI热点最小化
公开(公告)号：US07842554B2
公开(公告)日：2010-11-30
申请号：US12169458
申请日：2008-07-08
申请人： Christos Dimitrios Dimitrakopoulos , Christos John Georgiou
发明人： Christos Dimitrios Dimitrakopoulos , Christos John Georgiou
IPC分类号： H01L21/00
CPC分类号： F28F21/02 , F28D2015/0225 , F28D2021/0029 , F28F2255/00 , F28F2260/02 , H01L23/373 , H01L2924/0002 , H01L2924/00
摘要： The invention relates to a semiconductive device comprising a die with at least one defined hot-spot area lying in a plane on the die and a cooling structure comprising nanotubes such as carbon nanotubes extending in a plane different than the plane of the hot-spot area and outwardly from the plane of the hot-spot area. The nanotubes are operatively associated with the hot-spot area to decrease any temperature gradient between the hot-spot area and at least one other area on the die defined by a temperature lower than the hot-spot area. A matrix material comprising a second heat conducting material substantially surrounds the nanotubes and is operatively associated with and in heat conducting relation with the other area on the die defined by a temperature lower than the hot-spot area. The heat conductivity of the nanotubes is greater than the heat conductivity of the matrix material, with the distal ends of the nanotubes exposed to present a distal surface comprising the first heat conducting means for direct contact with a medium comprising a cooling fluid. The inventors also disclose processes for manufacturing and using the device and products produced by the processes.
摘要翻译：本发明涉及一种半导体器件，其包括具有位于管芯上的平面中的至少一个限定热点区域的管芯和包括在不同于热点区域的平面的平面内延伸的碳纳米管的纳米管的冷却结构并从热点区域的平面向外。纳米管与热点区域可操作地相关联，以降低由热点区域和模具上的至少一个其它区域之间的温度梯度，该温度梯度由低于热点区域的温度限定。包括第二导热材料的基质材料基本上围绕纳米管，并且与由热点区域的温度限定的模具上的另一个区域可操作地相关联并与其导热。纳米管的导热性大于基体材料的导热性，其中纳米管的远端暴露于远侧表面，该远端表面包括用于与包含冷却流体的介质直接接触的第一导热装置。本发明人还公开了用于制造和使用由该方法生产的装置和产品的方法。

12. 发明申请

US20090171853A1 Method and System for Hosting an In-Store Electronic Auction 审中-公开
标题翻译：托管店内电子拍卖的方法和系统
公开(公告)号：US20090171853A1
公开(公告)日：2009-07-02
申请号：US11967554
申请日：2007-12-31
申请人： Christos John Georgiou , Bernice Ellen Rogowitz , Myron Flickner
发明人： Christos John Georgiou , Bernice Ellen Rogowitz , Myron Flickner
IPC分类号： G06Q30/00
CPC分类号： G06Q30/08 , G06Q50/188
摘要： A system for hosting an in-store electronic auction including a plurality of shoppers including a store server capable of synchronizing with handheld portable devices within a predetermined geographic area, a plurality of customers having portable electronic devices. The portable electronic devices are capable of synchronizing with the store server, such that the plurality of customers can individually send and receive auction information therethrough, as well as an inventory of products within the predetermined geographic area from which a customer can shop. The store server identifies the shoppers in the predetermined geographical area through the portable electronic device, and determines a shopper's eligibility to participate in the auction. If the shopper is determined to be eligible to participate, the system synchronizes the shopper's portable electronic device to the store server. Upon receiving an offer for the purchase of an item from the inventory of products from a first eligible shopper, placed through the shopper's portable electronic device, the system determines if the first shopper's offer for the item in inventory is above a predetermined price, if the offer from the first shopper is above a predetermined price, system approves and authorizes the sales transaction. If the offer from the first shopper is not above a predetermined price the server notifies other eligible shoppers from the plurality of an auction for the item in inventory through the eligible shoppers' portable electronic device. The system then receives offers for the purchase of the item from the eligible shoppers of the plurality through the eligible shoppers' portable electronic device.
摘要翻译：一种用于托管店内电子拍卖的系统，包括多个购物者，包括能够与预定地理区域内的手持便携式设备同步的商店服务器，多个具有便携式电子设备的客户。便携式电子设备能够与商店服务器同步，使得多个客户可以单独地发送和接收拍摄信息，以及客户可以在其中购买的预定地理区域内的产品库存。商店服务器通过便携式电子设备识别预定地理区域中的购物者，并确定购物者参与拍卖的资格。如果购物者被确定有资格参与，系统将购物者的便携式电子设备同步到商店服务器。在从通过购物者的便携式电子设备放置的第一合格购物者的产品库存中收到要购买的物品的报价时，系统确定第一购物者对库存中的商品的报价是否高于预定价格，如果第一位顾客的报价高于预定价格，系统批准并授权销售交易。如果来自第一购物者的报价不高于预定价格，则服务器通过合格的购物者的便携式电子设备向库存中的物品的多次拍卖通知其他合格的购物者。然后，系统通过合格的购物者的便携式电子设备从多个的合格购物者接收购买物品的报价。

13. 发明授权

US07003597B2 Dynamic reallocation of data stored in buffers based on packet size 失效
标题翻译：基于数据包大小动态重新分配存储在缓冲区中的数据
公开(公告)号：US07003597B2
公开(公告)日：2006-02-21
申请号：US10604295
申请日：2003-07-09
申请人： Christos John Georgiou , Valentina Salapura
发明人： Christos John Georgiou , Valentina Salapura
IPC分类号： G06F12/02
CPC分类号： H04L49/9078 , H04L49/90 , H04L49/901 , H04L49/9021 , H04L49/9052
摘要： A method and system is provided to efficiently manage memory in a network device that receives packets of variable size. The memory is allocated into portions whereby each portion, comprising multiple equally-sized buffers, receives packets of a particular size. One portion is used for smaller packet sizes and another portion is for larger packet sizes, although other portions may be created. As packets are received at the network device, they are stored into the appropriate memory portion based on their size. The number of available buffers in each portion is monitored so that, when it falls below a threshold, buffers are reallocated to the other thereby increasing the overall memory efficiency.
摘要翻译：提供了一种方法和系统来有效地管理接收可变大小的分组的网络设备中的存储器。存储器被分配到部分，由此包括多个相等大小的缓冲器的每个部分接收特定大小的分组。一部分用于较小的分组大小，另一部分用于较大的分组大小，但可以创建其他部分。当在网络设备处接收到分组时，它们基于它们的大小被存储到适当的存储器部分中。监视每个部分中的可用缓冲器的数量，使得当其低于阈值时，缓冲器被重新分配到另一个，从而增加整体存储器效率。

14. 发明授权

US6032245A Method and system for interrupt handling in a multi-processor computer system executing speculative instruction threads 失效
标题翻译：用于执行推测性指令线程的多处理器计算机系统中的中断处理方法和系统
公开(公告)号：US6032245A
公开(公告)日：2000-02-29
申请号：US914301
申请日：1997-08-18
申请人： Christos John Georgiou , Daniel A. Prener
发明人： Christos John Georgiou , Daniel A. Prener
IPC分类号： G06F9/48 , G06F9/30
CPC分类号： G06F9/4812
摘要： In the system bus controller of a multi-processor system, apparatus is provided for selecting one of the processors to handle an interrupt. A mask is provided for each respective task being executed on each one of the processors. Each mask includes a speculation bit identifying whether the task is speculative. Each mask includes a plurality of class enable bits identifying whether the task can be interrupted by a respective class of interrupts associated with each of the plurality of class enable bits. Control lines in the system bus receive an interrupt having a received interrupt class. A subset of the processors is identified; processors in the subset can be interrupted by the received interrupt based on the received interrupt class and the respective speculation bit and class enable bits assigned to the task being executed on each respective processor. A Boolean AND operation is performed on the mask associated with the respective task executing on each processor. The AND operation is performed on the speculation bit and the class enable bit which corresponds to the received interrupt class, so as to determine whether that processor is included in the subset. One of the processors in the subset is selected to process the received interrupt, if the subset includes at least one processor.
摘要翻译：在多处理器系统的系统总线控制器中，提供了用于选择一个处理器来处理中断的装置。为在每个处理器上执行的每个相应任务提供掩码。每个掩码包括识别任务是否是推测性的推测位。每个掩码包括多个类允许位，用于识别该任务是否可以被与多个类使能位中的每一个相关联的相应类别的中断来中断。系统总线中的控制线接收到具有接收到的中断类的中断。识别处理器的一个子集; 子集中的处理器可以基于所接收到的中断类别以及分配给在每个相应处理器上执行的任务的相应的推测位和类使能位被中断。对与在每个处理器上执行的相应任务相关联的掩码执行布尔AND运算。在与所接收的中断类对应的推测位和类使能位上执行“与”运算，以便确定该处理器是否包括在该子集中。如果子集包括至少一个处理器，则选择该子集中的一个处理器来处理所接收的中断。

15. 发明申请

US20100326924A1 CO-DISPOSAL AND CO-STORAGE OF DESALINATION CONCENTRATED BRINE WASTE PRODUCT AND CARBON DIOXIDE WASTE PRODUCT 失效
标题翻译：脱盐浓缩锌废物和二氧化碳废物的共处理和共存
公开(公告)号：US20100326924A1
公开(公告)日：2010-12-30
申请号：US12491527
申请日：2009-06-25
申请人： Christos John Georgiou , Ulisses Thibes Mello
发明人： Christos John Georgiou , Ulisses Thibes Mello
IPC分类号： C02F1/58 , B01D53/14 , B09B1/00
CPC分类号： E21B41/0064 , B01D2257/504 , C02F2103/08 , E21B41/0057 , Y02C10/14
摘要： A method for disposal of desalination concentrated brine waste product from a desalination process provides that the desalination concentrated brine waste product is injected, along with a carbon dioxide waste product, typically into an imperviously capped porous rock formation, typically including a saline aquifer. The desalination concentrated brine waste product and the carbon dioxide waste product (i.e., which may be injected as a supercritical liquid) may be injected simultaneously or sequentially. The method provides for environmentally acceptable disposal of the desalination concentrated brine waste product and the carbon dioxide waste product.
摘要翻译：用于从脱盐过程处理脱盐浓缩盐水废物的方法提供了将脱盐浓缩的盐水废物与二氧化碳废物一起注入通常包含盐水含水层的不透水的多孔岩层中。可以同时或依次注入脱盐浓缩的盐水废物和二氧化碳废物（即可以作为超临界液体注入）。该方法提供了对脱盐浓缩盐水废物和二氧化碳废物的环境可接受处理。

16. 发明授权

US07676588B2 Programmable network protocol handler architecture 失效
标题翻译：可编程网络协议处理器架构
公开(公告)号：US07676588B2
公开(公告)日：2010-03-09
申请号：US11387875
申请日：2006-03-24
申请人： Christos John Georgiou , Monty Montague Denneau
发明人： Christos John Georgiou , Monty Montague Denneau
IPC分类号： G06F15/16 , G06F3/00
CPC分类号： H04L47/10 , G06F9/5027 , G06F2209/5018 , H04L47/125
摘要： An architecture that achieves high speed performance in a network protocol handler combines parallelism and pipelining in multiple programmable processors, along with specialized front-end logic at the network interface that handles time critical protocol operations. The multiple processors are interconnected via a high-speed interconnect, using a multi-token counter protocol for data transmission between processors and between processors and memory. Each processor's memory is globally accessible by other processors, and memory synchronization operations are used to obviate the need for “spin-locks”. Each processor has multiple threads, each capable of fully executing programs. Threads within a processor are assigned the processing of various protocol functions in a parallel/pipelined fashion. Data frame processing is done by one or more of the threads to identify related frames. Related frames are dispatched to the same thread so as to minimize the overhead associated with memory accesses and general protocol processing.
摘要翻译：在网络协议处理器中实现高速性能的架构将多个可编程处理器中的并行性和流水线结合在一起，以及处理时间关键协议操作的网络接口处的专用前端逻辑。多处理器通过高速互连互连，使用多令牌计数器协议在处理器之间以及处理器和存储器之间进行数据传输。每个处理器的存储器可由其他处理器全局访问，并且使用存储器同步操作来消除对“自旋锁”的需要。每个处理器有多个线程，每个线程都能完全执行程序。处理器中的线程以并行/流水线方式分配各种协议功能的处理。数据帧处理由一个或多个线程完成以识别相关帧。相关帧被调度到相同的线程，以便最小化与存储器访问和通用协议处理相关联的开销。

17. 发明授权

US07426674B2 Method of computing partial CRCs 失效
标题翻译：部分CRC的计算方法
公开(公告)号：US07426674B2
公开(公告)日：2008-09-16
申请号：US11224994
申请日：2005-09-14
申请人： Richard E. Anderson , Christos John Georgiou , Peter A. Sandon
发明人： Richard E. Anderson , Christos John Georgiou , Peter A. Sandon
IPC分类号： H03M13/00
CPC分类号： H04L1/0041 , H03M13/09 , H03M13/091 , H03M13/093 , H03M13/6516 , H04L1/0061
摘要： Method of generating cyclic redundancy checks (CRCs) for a message with N data blocks. The method includes calculating a partial CRC for an out of order data block and storing the result, generating, using a division operation, a CRC remainder multiplier associated with the out of order data block and storing the result, repeating the calculating and generating steps until all N data blocks for the message are received, and combining the results of the calculating step and the generating step.
摘要翻译：为具有N个数据块的消息生成循环冗余校验（CRC）的方法。该方法包括计算一个无序数据块的部分CRC并存储该结果，使用除法运算产生与该次序数据块相关联的CRC余数乘数并存储该结果，重复该计算和生成步骤直到接收消息的所有N个数据块，并将计算步骤的结果与生成步骤进行组合。

18. 发明授权

US06836808B2 Pipelined packet processing 失效
标题翻译：流水线包处理
公开(公告)号：US06836808B2
公开(公告)日：2004-12-28
申请号：US09683863
申请日：2002-02-25
申请人： Robert Michael Bunce , Christos John Georgiou , Valentina Salapura
发明人： Robert Michael Bunce , Christos John Georgiou , Valentina Salapura
IPC分类号： G06F300
CPC分类号： H04L49/1546 , H04L49/103 , H04L49/3018 , H04L49/357 , H04L49/90
摘要： A method and system for increasing the efficiency of packet processing within a packet protocol handler. In accordance with the method of the present invention packet processing tasks are performed on multiple processors or threads concurrently and in a pipelined fashion. Subsequent protocol packet processing tasks for processing a single packet are performed on multiple processors or threads, acting as stages of a pipeline. The assignment of tasks to processors or threads is performed dynamically, by checking the availability of a processor or thread in the subsequent pipeline stage. The availability determination includes determining the available capacity of the input work queue associated with each processor or thread. If the subsequent pipeline stage is overloaded, the task is assigned to another processor or thread that is not overloaded.
摘要翻译：一种用于提高分组协议处理程序内的分组处理效率的方法和系统。根据本发明的方法，在多个处理器或线程上同时并以流水线方式执行分组处理任务。用于处理单个分组的后续协议分组处理任务在作为流水线的阶段的多个处理器或线程上执行。通过检查后续流水线阶段中的处理器或线程的可用性，动态地对处理器或线程分配任务。可用性确定包括确定与每个处理器或线程相关联的输入工作队列的可用容量。如果随后的流水线阶段过载，则将任务分配给另一个未重载的处理器或线程。

19. 发明授权

US6047248A Performance-temperature optimization by cooperatively varying the voltage and frequency of a circuit 有权
标题翻译：通过协调改变电路的电压和频率进行性能温度优化
公开(公告)号：US6047248A
公开(公告)日：2000-04-04
申请号：US226097
申请日：1998-10-19
申请人： Christos John Georgiou , Edward Scott Kirkpatrick , Thor Arne Larsen
发明人： Christos John Georgiou , Edward Scott Kirkpatrick , Thor Arne Larsen
IPC分类号： G05D23/24 , G06F1/20 , G06F1/32 , G05D23/00
CPC分类号： G06F1/324 , G05D23/1913 , G05D23/24 , G06F1/206 , G06F1/3203 , G06F1/3296 , Y02B60/1217 , Y02B60/1275 , Y02B60/1285
摘要： A system and method using thermal feedback to cooperatively vary a voltage and frequency of a circuit to control heating while maintaining synchronization. Preferably, on-chip thermal sensors are used for feedback. A system having features of the invention includes: a thermal sensor coupled to the circuit, the thermal sensor generating a temperature signal which is a function of a temperature associated with the functional unit; a temperature decoder having an input and an output, the input coupled to the thermal sensor for decoding the temperature signal; a comparator having one input coupled to the decoder for comparing a decoded temperature signal with a predetermined temperature threshold signal coupled to a second input, the comparator enabling a voltage/clock control signal as a function of the decoded temperature signal and the predetermined temperature threshold; an adjustable voltage regulator coupled to the voltage/clock control signal; and a clock selector coupled to the voltage/clock control signal; wherein the voltage regulator and the clock selector are adapted to cooperatively vary the voltage and the frequency of the circuit to a predetermined voltage-frequency pair, responsive to the voltage/clock control signal.
摘要翻译：使用热反馈的系统和方法协调地改变电路的电压和频率以控制加热同时保持同步。优选地，片上热传感器用于反馈。具有本发明特征的系统包括：耦合到电路的热传感器，热传感器产生温度信号，温度信号是与功能单元相关联的温度的函数; 具有输入和输出的温度解码器，所述输入耦合到所述热传感器，用于解码所述温度信号; 比较器，其具有耦合到解码器的一个输入端，用于将解码的温度信号与耦合到第二输入端的预定温度阈值信号进行比较，所述比较器使电压/时钟控制信号作为解码温度信号和预定温度阈值的函数; 耦合到电压/时钟控制信号的可调电压调节器; 以及时钟选择器，耦合到所述电压/时钟控制信号; 其中所述电压调节器和所述时钟选择器适于根据所述电压/时钟控制信号协调地将所述电路的电压和频率改变为预定的电压 - 频率对。

20. 发明授权

US5798918A Performance-temperature optimization by modulating the switching factor of a circuit 失效
标题翻译：通过调制电路的开关因数进行性能温度优化
公开(公告)号：US5798918A
公开(公告)日：1998-08-25
申请号：US639396
申请日：1996-04-29
申请人： Christos John Georgiou , Edward Scott Kirkpatrick , Thor Arne Larsen
发明人： Christos John Georgiou , Edward Scott Kirkpatrick , Thor Arne Larsen
IPC分类号： G05B13/02
CPC分类号： G06F9/3836 , G05B13/024
摘要： A system and method for modulating the switching factor of a circuit to control heating and which does not require modulation of the circuit's clock frequency. The switching factor refers to the fact that due to gating requirements, latency and data transfer characteristics, the rate at which a circuit's inputs are addressed is some fraction of the circuit clock frequency. Application can be made to many existing systems which incorporate single or multiple VLSI circuits such as superscalar microprocessors, parallel processors, DSPs, microcontrollers and MPEG decoders. A method for controlling a switching factor of a multi-functional unit processor includes the steps of: scheduling instructions stored in a memory for execution on each functional unit; generating a first temperature signal for a first functional unit and a second temperature signal for a second functional unit, each temperature signal being a function of a temperature associated with each functional unit; identifying the first functional unit and the second functional unit associated with each temperature signal, responsive to the generating step; comparing the first temperature signal with a first predetermined temperature threshold signal; generating a first temperature delay signal when the first temperature signal exceeds the first predetermined threshold, responsive to the comparison; and reducing the switching factor of the first functional unit according to the first temperature delay signal by delaying scheduling instructions for execution on the first functional unit. Further reduction in power dissipation may be achieved by using thermal feedback to cooperatively vary the voltage and frequency of a circuit.
摘要翻译：用于调制电路的开关因数以控制加热并且不需要调制电路的时钟频率的系统和方法。开关因素是指由于门控要求，等待时间和数据传输特性，电路输入的寻址速率是电路时钟频率的一小部分。可以应用于许多现有的系统，它们集成了单个或多个VLSI电路，如超标量微处理器，并行处理器，DSP，微控制器和MPEG解码器。一种用于控制多功能单元处理器的切换因子的方法，包括以下步骤：调度存储在存储器中的指令，以执行每个功能单元; 产生用于第一功能单元的第一温度信号和用于第二功能单元的第二温度信号，每个温度信号是与每个功能单元相关联的温度的函数; 响应于所述生成步骤，识别与每个温度信号相关联的第一功能单元和第二功能单元; 将第一温度信号与第一预定温度阈值信号进行比较; 响应于所述比较，当所述第一温度信号超过所述第一预定阈值时，产生第一温度延迟信号; 以及通过延迟用于在所述第一功能单元上执行的调度指令来降低根据所述第一温度延迟信号的所述第一功能单元的开关因数。可以通过使用热反馈来协调地改变电路的电压和频率来实现功率耗散的进一步降低。

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