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11. 发明授权

US06830998B1 Gate dielectric quality for replacement metal gate transistors 失效
标题翻译：更换金属栅极晶体管的栅极介电质量得到改善
公开(公告)号：US06830998B1
公开(公告)日：2004-12-14
申请号：US10462667
申请日：2003-06-17
申请人： James Pan , Paul Besser , Christy Mei-Chu Woo , Minh Van Ngo , Jinsong Yin
发明人： James Pan , Paul Besser , Christy Mei-Chu Woo , Minh Van Ngo , Jinsong Yin
IPC分类号： H01L213205
CPC分类号： H01L29/66606 , H01L21/28088 , H01L29/4966 , H01L29/66545
摘要： Gate dielectric degradation due to plasma damage during replacement metal gate processing is cured and prevented from further plasma degradation by treatment of the gate dielectric after removing the polysilicon gate. Embodiments include low temperature vacuum annealing after metal deposition and CMP, annealing in oxygen and argon, ozone or a forming gas before metal deposition, or heat soaking in silane or disilane, before metal deposition.
摘要翻译：在更换金属栅极处理期间由于等离子体损坏引起的栅极介质劣化被固化并且通过在去除多晶硅栅极之后处理栅极电介质来防止进一步的等离子体劣化。实施例包括在金属沉积之前的金属沉积和CMP之后的低温真空退火，在氧气和氩气中的退火，在金属沉积之前的臭氧或形成气体，或者在金属沉积之前的硅烷或乙硅烷中的热浸渍。

12. 发明授权

US06727560B1 Engineered metal gate electrode 有权
公开(公告)号：US06727560B1
公开(公告)日：2004-04-27
申请号：US10360719
申请日：2003-02-10
申请人： James N. Pan , Paul R. Besser , Christy Woo , Minh Van Ngo , Jinsong Yin
发明人： James N. Pan , Paul R. Besser , Christy Woo , Minh Van Ngo , Jinsong Yin
IPC分类号： H01L2976
CPC分类号： H01L29/66545 , H01L21/28088 , H01L29/4966
摘要： A metal gate electrode is formed with an intrinsic electric field to modify its work function and the threshold voltage of the transistor. Embodiments include forming an opening in a dielectric layer by removing a removable gate, depositing one or more layers of tantalum nitride such that the nitrogen content increases from the bottom of the layer adjacent the gate dielectric layer upwardly. Other embodiments include forming the intrinsic electric field to control the work function by doping one or more metal layers and forming metal alloys. Embodiments further include the use of barrier layers when forming metal gate electrodes.

13. 发明授权

US07023046B2 Undoped oxide liner/BPSG for improved data retention 有权
标题翻译：未掺杂氧化物衬垫/ BPSG，以改善数据保留
公开(公告)号：US07023046B2
公开(公告)日：2006-04-04
申请号：US10617450
申请日：2003-07-11
申请人： Minh Van Ngo , Angela Hui , Ning Cheng , Jeyong Park , Jean Yee-Mei Yang , Robert A. Huertas , Tazrien Kamal , Pei-Yuan Gao , Tyagamohan Gottipati
发明人： Minh Van Ngo , Angela Hui , Ning Cheng , Jeyong Park , Jean Yee-Mei Yang , Robert A. Huertas , Tazrien Kamal , Pei-Yuan Gao , Tyagamohan Gottipati
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L21/02129 , H01L21/02164 , H01L21/022 , H01L21/02271 , H01L21/31612 , H01L21/31625 , H01L27/115 , H01L29/511
摘要： Semiconductor devices with improved data retention are formed by depositing an undoped oxide liner on spaced apart transistors followed by in situ deposition of a BPSG layer. Embodiments include depositing an undoped silicon oxide liner derived from TEOS, as at a thickness of 400 Å to 600 Å, on transistors of a non-volatile semiconductor device, as by sub-atmospheric chemical vapor deposition, followed by depositing the BPSG layer in the same deposition chamber.
摘要翻译：具有改进的数据保留的半导体器件通过将未掺杂的氧化物衬底沉积在间隔开的晶体管上，然后原位沉积BPSG层来形成。实施例包括在非易失性半导体器件的晶体管上沉积衍生自TEOS的未掺杂的氧化硅衬垫，如非易失性半导体器件的晶体管，如通过亚大气压化学气相沉积，然后将BPSG层沉积在相同的沉积室。

14. 发明授权

US06479348B1 Method of making memory wordline hard mask extension 有权
标题翻译：制作内存字线硬掩模扩展的方法
公开(公告)号：US06479348B1
公开(公告)日：2002-11-12
申请号：US10109516
申请日：2002-08-27
申请人： Tazrien Kamal , Minh Van Ngo , Mark T. Ramsbey , Jeffrey Shields , Jean Y. Yang , Emmanuil Lingunis , Hidehiko Shiraiwa , Angela T. Hui
发明人： Tazrien Kamal , Minh Van Ngo , Mark T. Ramsbey , Jeffrey Shields , Jean Y. Yang , Emmanuil Lingunis , Hidehiko Shiraiwa , Angela T. Hui
IPC分类号： H01L218247
CPC分类号： H01L27/11568 , H01L27/115
摘要： A manufacturing method is provided for an integrated circuit memory with closely spaced wordlines formed by using hard mask extensions. A charge-trapping dielectric material is deposited over a semiconductor substrate and first and second bitlines are formed therein. A wordline material and a hard mask material are deposited over the wordline material. A photoresist material is deposited over the hard mask material and is processed to form a patterned photoresist material. The hard mask material is processed using the patterned photoresist material to form a patterned hard mask material. The patterned photoresist is then removed. A hard mask extension material is deposited over the wordline material and is processed to form a hard mask extension. The wordline material is processed using the patterned hard mask material and the hard mask extension to form a wordline, and the patterned hard mask material and the hard mask extension are then removed.
摘要翻译：提供了一种用于通过使用硬掩模延伸部形成的具有紧密间隔的字线的集成电路存储器的制造方法。在半导体衬底上沉积电荷俘获电介质材料，并在其中形成第一和第二位线。字线材料和硬掩模材料沉积在字线材料上。光致抗蚀剂材料沉积在硬掩模材料上并被处理以形成图案化的光致抗蚀剂材料。使用图案化的光致抗蚀剂材料处理硬掩模材料以形成图案化的硬掩模材料。然后去除图案化的光致抗蚀剂。硬掩模延伸材料沉积在字线材料上并被处理以形成硬掩模延伸部。使用图案化的硬掩模材料和硬掩模延伸部来处理字线材料以形成字线，然后去除图案化的硬掩模材料和硬掩模延伸部。

15. 发明授权

US07927723B1 Film stacks to prevent UV-induced device damage 有权
标题翻译：电影堆叠以防止紫外线引起的设备损坏
公开(公告)号：US07927723B1
公开(公告)日：2011-04-19
申请号：US11091524
申请日：2005-03-29
申请人： Angela T. Hui , Ning Cheng , Minh Van Ngo , Hirokazu Tokuno , Wenmei Li
发明人： Angela T. Hui , Ning Cheng , Minh Van Ngo , Hirokazu Tokuno , Wenmei Li
IPC分类号： G02B1/10 , G02B5/28 , B32B9/00 , B32B19/00
CPC分类号： G02B5/208
摘要： A film stack includes an interlayer dielectric formed over one or more devices. The film stack further includes a first layer having a high extinction coefficient formed on the interlayer dielectric and a second layer having a low extinction coefficient formed on the first layer. The first and second layers prevent ultraviolet induced damage to the one or more devices while minimizing reflectivity for lithographic processes.
摘要翻译：膜堆叠包括在一个或多个器件上形成的层间电介质。薄膜叠层还包括形成在层间电介质上的具有高消光系数的第一层和形成在第一层上的具有低消光系数的第二层。第一层和第二层防止对一种或多种设备的紫外线诱发的损坏，同时最小化光刻工艺的反射率。

16. 发明授权

US07704878B2 Contact spacer formation using atomic layer deposition 有权
标题翻译：使用原子层沉积接触间隔物形成
公开(公告)号：US07704878B2
公开(公告)日：2010-04-27
申请号：US11240468
申请日：2005-10-03
申请人： Minh Van Ngo , Angela T. Hui , Amol Ramesh Joshi , Wenmei Li , Ning Cheng , Ankur Bhushan Agarwal , Norimitsu Takagi
发明人： Minh Van Ngo , Angela T. Hui , Amol Ramesh Joshi , Wenmei Li , Ning Cheng , Ankur Bhushan Agarwal , Norimitsu Takagi
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L21/76831
摘要： A contact structure in a semiconductor device includes a layer of dielectric material and a via formed through the dielectric material. The contact structure further includes a spacer formed on sidewalls of the via using atomic layer deposition (ALD) and a metal deposited in the via.
摘要翻译：半导体器件中的接触结构包括介电材料层和通过介电材料形成的通孔。接触结构还包括通过使用原子层沉积（ALD）和沉积在通孔中的金属在通孔的侧壁上形成的间隔物。

17. 发明授权

US07300886B1 Interlayer dielectric for charge loss improvement 有权
标题翻译：用于电荷损耗改善的层间电介质
公开(公告)号：US07300886B1
公开(公告)日：2007-11-27
申请号：US11147208
申请日：2005-06-08
申请人： Minh Van Ngo , Ning Cheng , Wenmei Li , Angela T. Hui , Pei-Yuan Gao , Robert A. Huertas
发明人： Minh Van Ngo , Ning Cheng , Wenmei Li , Angela T. Hui , Pei-Yuan Gao , Robert A. Huertas
IPC分类号： H01L21/31
CPC分类号： H01L21/31625 , H01L21/02129 , H01L21/02271 , H01L27/115 , H01L27/11568
摘要： A method of manufacturing a memory device includes forming a first dielectric layer over a substrate and forming a charge storage element over the first dielectric layer. The method also includes forming a second dielectric layer over the charge storage element and forming a control gate over the second dielectric layer. The method further includes depositing an interlayer dielectric over the control gate at a high temperature.
摘要翻译：一种制造存储器件的方法包括在衬底上形成第一介电层，并在第一介电层上形成电荷存储元件。该方法还包括在电荷存储元件上形成第二电介质层，并在第二电介质层上形成控制栅极。该方法还包括在高温下在控制栅极上沉积层间电介质。

18. 发明授权

US07091088B1 UV-blocking etch stop layer for reducing UV-induced charging of charge storage layer in memory devices in BEOL processing 有权
标题翻译：用于减少BEOL处理中的存储器件中的电荷存储层的UV诱导的充电的UV阻挡蚀刻停止层
公开(公告)号：US07091088B1
公开(公告)日：2006-08-15
申请号：US10861437
申请日：2004-06-03
申请人： Ning Cheng , Clarence B. Ferguson , Emmanuil H. Lingunis , Minh Van Ngo , Joerg Reiss , Jean Y. Yang , Jeffrey A. Shields , Cyrus Tabery
发明人： Ning Cheng , Clarence B. Ferguson , Emmanuil H. Lingunis , Minh Van Ngo , Joerg Reiss , Jean Y. Yang , Jeffrey A. Shields , Cyrus Tabery
IPC分类号： H01L21/336
CPC分类号： H01L23/53295 , H01L21/76829 , H01L27/115 , H01L27/11568 , H01L2924/0002 , Y10S438/954 , H01L2924/00
摘要： A method of protecting a charge trapping dielectric flash memory cell from UV-induced charging, including fabricating a charge trapping dielectric flash memory cell in a semiconductor device; depositing over the charge trapping dielectric flash memory cell at least one UV-protective layer; forming at least one layer over the at least one UV-protective layer; and etching the at least one layer to form an opening therein with an etchant species selective to stop on a layer below the at least one UV-protective layer, wherein the UV-protective layer comprises a substantially UV-opaque material.
摘要翻译：一种保护电荷捕获电介质闪速存储器单元免受UV感应充电的方法，包括在半导体器件中制造电荷俘获电介质闪存单元; 在电荷捕获电介质闪存单元上沉积至少一个UV保护层; 在所述至少一个UV保护层上形成至少一层; 以及蚀刻所述至少一个层以在其中形成具有选择性地停留在所述至少一个UV保护层下方的层上的蚀刻剂物质的开口，其中所述UV保护层包括基本上不透紫外线的材料。

19. 发明授权

US06989563B1 Flash memory cell with UV protective layer 有权
标题翻译：具有UV保护层的闪存单元
公开(公告)号：US06989563B1
公开(公告)日：2006-01-24
申请号：US10770260
申请日：2004-02-02
申请人： Krishnashree Achuthan , Patrick K. Cheung , Cyrus Tabery , Jean Y. Yang , Ning Cheng , Minh Van Ngo
发明人： Krishnashree Achuthan , Patrick K. Cheung , Cyrus Tabery , Jean Y. Yang , Ning Cheng , Minh Van Ngo
IPC分类号： H01L29/788
CPC分类号： H01L29/7923 , H01L23/53295 , H01L23/552 , H01L29/66833 , H01L2924/0002 , H01L2924/00
摘要： A method of protecting a charge trapping dielectric flash memory cell from UV-induced charging, including fabricating a charge trapping dielectric flash memory cell in a semiconductor device; depositing and planarizing an interlevel dielectric layer over the charge trapping dielectric flash memory cell and depositing over the planarized interlevel dielectric layer at least one UV-protective layer, the UV-protective layer including a substantially UV-opaque material.
摘要翻译：一种保护电荷捕获电介质闪速存储器单元免受UV感应充电的方法，包括在半导体器件中制造电荷俘获电介质闪存单元; 在电荷俘获电介质闪存单元上沉积和平坦化层间电介质层，并在平坦化的层间电介质层上沉积至少一个UV保护层，UV保护层包括基本上不透紫外线的材料。

20. 发明授权

US07238571B1 Non-volatile memory device with increased reliability 有权
标题翻译：非易失性存储器件具有更高的可靠性
公开(公告)号：US07238571B1
公开(公告)日：2007-07-03
申请号：US11063560
申请日：2005-02-24
申请人： Hirokazu Tokuno , Wenmei Li , Ning Cheng , Minh Van Ngo , Angela T. Hui , Cinti X. Chen
发明人： Hirokazu Tokuno , Wenmei Li , Ning Cheng , Minh Van Ngo , Angela T. Hui , Cinti X. Chen
IPC分类号： H01L29/80 , H01L31/112
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11568
摘要： A memory device may include a number of memory cells, a first interlayer dielectric formed over the memory cells and at least one metal layer formed over the interlayer dielectric. A dielectric layer may be formed over the metal layer. The dielectric layer may represent a cap layer formed at or near an upper surface of the memory device and may be deposited at a relatively low temperature.
摘要翻译：存储器件可以包括多个存储器单元，形成在存储器单元上的第一层间电介质和形成在层间电介质上的至少一个金属层。介电层可以形成在金属层的上方。电介质层可以表示在存储器件的上表面处或附近形成的覆盖层，并且可以在相对低的温度下沉积。

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