专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US5193515A Ignition system for an engine 失效
标题翻译：发动机点火系统
公开(公告)号：US5193515A
公开(公告)日：1993-03-16
申请号：US851001
申请日：1992-03-12
申请人： Nobuyuki Oota , Yasutoshi Yamada
发明人： Nobuyuki Oota , Yasutoshi Yamada
IPC分类号： F02P3/00 , F02P3/08 , F02P15/10
CPC分类号： F02P3/0892 , F02P15/10
摘要： An ignition system for two ignition current circuits including a condenser to supply the ignition current to the plug. The ignition current circuits provide the ignition current to the plug alternately in response to an ignition timing signal so that the first and second current circuit to supply the ignition current constantly.
摘要翻译：一种用于两个点火电流回路的点火系统，包括一个冷凝器，用于将点火电流提供给插头。点火电流电路响应于点火定时信号而交替地提供点火电流，使得第一和第二电流电路不断地提供点火电流。

12. 发明授权

US5134357A DC voltage converting device 失效
标题翻译：直流电压转换装置
公开(公告)号：US5134357A
公开(公告)日：1992-07-28
申请号：US500832
申请日：1990-03-29
申请人： Shinichiro Iwasaki , Motonobu Akagi , Nobuyuki Oota , Yasutoshi Yamada
发明人： Shinichiro Iwasaki , Motonobu Akagi , Nobuyuki Oota , Yasutoshi Yamada
IPC分类号： H02M3/155 , H02M3/156
CPC分类号： H02M3/1563
摘要： A DC voltage converting device having a choke coil, a switching device, a capacitor for accumulating electric energy, an inhibition setting device for setting and releasing an inhibition of charging, a current detecting device for detecting a charge current of the choke coil, a charge/discharge setting device for setting a discharge of the choke coil, and a driving device for conductively energizing the switching device. Based on this construction, when a capacitor voltage exceeds a predetermined voltage, only a time for interrupting the charge is extended.
摘要翻译：一种具有扼流线圈的直流电压转换装置，开关装置，用于蓄积电能的电容器，用于设定和释放禁止充电的禁止设定装置，用于检测扼流线圈的充电电流的电流检测装置，充电用于设定扼流线圈放电的放电设定装置，以及用于对开关装置进行导通的驱动装置。基于这种结构，当电容器电压超过预定电压时，仅延长中断充电的时间。

13. 发明授权

US5056497A Ignition control system 失效
标题翻译：点火控制系统
公开(公告)号：US5056497A
公开(公告)日：1991-10-15
申请号：US511231
申请日：1990-04-19
申请人： Motonobu Akagi , Nobuyuki Oota , Yasutoshi Yamada
发明人： Motonobu Akagi , Nobuyuki Oota , Yasutoshi Yamada
IPC分类号： F02P3/045 , F02P3/05 , F02P15/10
CPC分类号： F02P15/10 , F02P3/0453 , F02P3/051
摘要： An ignition system for generating multiple ignitions during a spark interval of an engine cylinder. For controlling an energy of each one of the multiple ignitions, a ramp signal which linearly rises from an initial peak value of a primary charge current for each one of the multiple ignitions of a primary winding of the ignition coil is compared with a preset value and a charge of the primary winding for each one of the multiple ignitions is stopped when the ramp signal exceeds the preset value. After a predetermined time, a primary charge current is supplied again to the primary winding until the ramp signal exceeds the preset value.
摘要翻译：一种用于在发动机气缸的火花间隔期间产生多个点火的点火系统。为了控制多个点火中的每个点火的能量，将与点火线圈的初级绕组的多个点火中的每一个点的初级充电电流的初始峰值线性上升的斜坡信号与预设值进行比较，当斜坡信号超过预设值时，停止多个点火中的每一个的初级绕组的电荷。在预定时间之后，再次向初级绕组提供初级充电电流，直到斜坡信号超过预设值。

14. 发明授权

US07933141B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07933141B2
公开(公告)日：2011-04-26
申请号：US12416432
申请日：2009-04-01
申请人： Kazuhiko Kajigaya , Soichiro Yoshida , Tomonori Sekiguchi , Riichiro Takemura , Yasutoshi Yamada
发明人： Kazuhiko Kajigaya , Soichiro Yoshida , Tomonori Sekiguchi , Riichiro Takemura , Yasutoshi Yamada
IPC分类号： G11C11/24
CPC分类号： G11C5/147 , G11C7/04 , G11C11/4076 , G11C11/4091 , G11C11/4097
摘要： In a semiconductor memory device, a memory cell is connected with a local sense amplifier and a global sense amplifier via a local bit line and a global bit line. The local sense amplifier is a single-ended sense amplifier including a single MOS transistor, which detects a potential of the local bit line which varies when reading and writing data with the memory cell. The threshold voltage of the MOS transistor is monitored so as to produce a high-level write voltage and a low-level write voltage, which are corrected and shifted based on the monitoring result so as to properly perform a reload operation on the memory cell by the global local sense amplifier. Thus, it is possible to cancel out temperature-dependent variations of the threshold voltage and shifting of the threshold voltage due to dispersions of manufacturing processes.
摘要翻译：在半导体存储器件中，存储单元通过局部位线和全局位线与本地读出放大器和全局读出放大器连接。本地读出放大器是包括单个MOS晶体管的单端读出放大器，其检测当与存储单元读取和写入数据时变化的局部位线的电位。监视MOS晶体管的阈值电压，以产生高电平写入电压和低电平写入电压，这些电压根据监视结果进行校正和移位，从而通过以下方式适当地执行对存储器单元的重新加载操作：全局局部感测放大器。因此，可以消除阈值电压的温度变化和由于制造工艺的分散造成的阈值电压的偏移。

15. 发明授权

US07903449B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07903449B2
公开(公告)日：2011-03-08
申请号：US12485568
申请日：2009-06-16
申请人： Kazuhiko Kajigaya , Soichiro Yoshida , Tomonori Sekiguchi , Riichiro Takemura , Yasutoshi Yamada
发明人： Kazuhiko Kajigaya , Soichiro Yoshida , Tomonori Sekiguchi , Riichiro Takemura , Yasutoshi Yamada
IPC分类号： G11C11/24
CPC分类号： G11C7/02 , G11C11/4074 , G11C11/4099 , H01L27/0207 , H01L27/0688 , H01L27/10852 , H01L27/10894 , H01L27/10897 , H01L28/91
摘要： A semiconductor memory device (e.g. DRAM) is constituted of a memory cell array including a plurality of memory cells, a plurality of word line drivers, a plurality of sense amplifiers, and a plurality of dummy capacitors. The memory cells, each of which includes a transistor and a capacitor, are positioned at intersections between the word lines and the bit lines. The first electrodes of the capacitors are connected to the transistors in the memory cells. The first electrodes of the dummy capacitors are connected together and are supplied with a second potential (e.g. VDD or VSS). The second electrodes of the dummy capacitors are connected together with the second electrodes of the capacitors of the memory cells and are supplied with a first potential (e.g. VPL). The dummy capacitors serve as smoothing capacitances for the plate voltage VPL so as to reduce plate noise.
摘要翻译：半导体存储器件（例如DRAM）由包括多个存储单元，多个字线驱动器，多个读出放大器和多个虚拟电容器的存储单元阵列构成。每个存储单元包括晶体管和电容器，位于字线和位线之间的交点处。电容器的第一电极连接到存储单元中的晶体管。虚拟电容器的第一电极连接在一起并被提供第二电位（例如VDD或VSS）。虚拟电容器的第二电极与存储单元的电容器的第二电极连接在一起并被提供有第一电位（例如VPL）。虚拟电容器用作板电压VPL的平滑电容，以减少板噪声。

16. 发明申请

US20090323399A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20090323399A1
公开(公告)日：2009-12-31
申请号：US12485568
申请日：2009-06-16
申请人： Kazuhiko KAJIGAYA , Soichiro Yoshida , Tomonori Sekiguchi , Riichiro Takemura , Yasutoshi Yamada
发明人： Kazuhiko KAJIGAYA , Soichiro Yoshida , Tomonori Sekiguchi , Riichiro Takemura , Yasutoshi Yamada
IPC分类号： G11C11/24 , G11C8/08 , H01L27/108
CPC分类号： G11C7/02 , G11C11/4074 , G11C11/4099 , H01L27/0207 , H01L27/0688 , H01L27/10852 , H01L27/10894 , H01L27/10897 , H01L28/91
摘要： A semiconductor memory device (e.g. DRAM) is constituted of a memory cell array including a plurality of memory cells, a plurality of word line drivers, a plurality of sense amplifiers, and a plurality of dummy capacitors. The memory cells, each of which includes a transistor and a capacitor, are positioned at intersections between the word lines and the bit lines. The first electrodes of the capacitors are connected to the transistors in the memory cells. The first electrodes of the dummy capacitors are connected together and are supplied with a second potential (e.g. VDD or VSS). The second electrodes of the dummy capacitors are connected together with the second electrodes of the capacitors of the memory cells and are supplied with a first potential (e.g. VPL). The dummy capacitors serve as smoothing capacitances for the plate voltage VPL so as to reduce plate noise.
摘要翻译：半导体存储器件（例如DRAM）由包括多个存储单元，多个字线驱动器，多个读出放大器和多个虚拟电容器的存储单元阵列构成。每个存储单元包括晶体管和电容器，位于字线和位线之间的交点处。电容器的第一电极连接到存储单元中的晶体管。虚拟电容器的第一电极连接在一起并被提供第二电位（例如VDD或VSS）。虚拟电容器的第二电极与存储单元的电容器的第二电极连接在一起并被提供有第一电位（例如VPL）。虚拟电容器用作板电压VPL的平滑电容，以减少板噪声。

17. 发明授权

US08988958B2 Sense amplifier circuit and semiconductor device 有权
公开(公告)号：US08988958B2
公开(公告)日：2015-03-24
申请号：US14306293
申请日：2014-06-17
申请人： Kazuhiko Kajigaya , Soichiro Yoshida , Yasutoshi Yamada
发明人： Kazuhiko Kajigaya , Soichiro Yoshida , Yasutoshi Yamada
IPC分类号： G11C7/00 , G11C7/06 , G11C11/4091 , G11C5/14 , G11C7/10
CPC分类号： G11C7/06 , G11C5/147 , G11C7/065 , G11C7/067 , G11C7/1087 , G11C11/4091
摘要： A single-ended sense amplifier circuit of the invention comprises first and second MOS transistors and first and second precharge circuits. The first MOS transistor drives the bit line to a predetermined voltage and switches connection between the bit line and a sense node and the second MOS transistor whose gate is connected to the sense node amplifies the signal via the first MOS transistor. The first precharge circuit precharges the bit line to a first potential and the second precharge circuit precharges the sense node to a second potential. Before sensing operation, the bit line is driven to the predetermined voltage when the above gate voltage is controlled to decrease. The predetermined voltage is appropriately set so that a required voltage difference at the sense node between high and low levels can be obtained near a changing point between charge transfer/distributing modes.

18. 发明授权

US08605532B2 Semiconductor device having hierarchical bit line structure 有权
标题翻译：具有分层位线结构的半导体器件
公开(公告)号：US08605532B2
公开(公告)日：2013-12-10
申请号：US13299285
申请日：2011-11-17
申请人： Kazuhiko Kajigaya , Yasutoshi Yamada
发明人： Kazuhiko Kajigaya , Yasutoshi Yamada
IPC分类号： G11C7/00 , G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： G11C7/06 , G11C7/1048 , G11C8/12 , G11C11/402 , G11C11/406 , G11C11/4091 , G11C11/4097
摘要： Disclosed herein is a semiconductor device comprising a memory cell, a local bit line coupled to the memory cell, a global bit line provided correspondingly to the local bit line, and a bit line control circuit coupled between the local bit line and the global bit line. The bit line control circuit includes a restoring circuit that is activated in a refresh mode to refresh data of the memory cell while being in electrical isolation from the global bit line.
摘要翻译：本文公开了一种半导体器件，包括存储器单元，耦合到存储器单元的局部位线，对应于局部位线提供的全局位线，以及耦合在局部位线和全局位线之间的位线控制电路。位线控制电路包括在刷新模式下被激活以在与全局位线电隔离的同时刷新存储器单元的数据的恢复电路。

19. 发明授权

US08217541B2 Wiring component for motor coil 失效
标题翻译：电机线圈接线部件
公开(公告)号：US08217541B2
公开(公告)日：2012-07-10
申请号：US12609278
申请日：2009-10-30
申请人： Toshiya Sugiyama , Jun Abiko , Yasutoshi Yamada , Hiroyuki Nagata
发明人： Toshiya Sugiyama , Jun Abiko , Yasutoshi Yamada , Hiroyuki Nagata
IPC分类号： H02K11/00 , H02K3/00 , H02K3/46
CPC分类号： H02K3/50 , H02K2203/06 , H02K2203/09
摘要： A wiring component for a motor coil includes a wire coil configured by a plurality of wire segments arranged in a circumferential direction so as to form a ring shape, each of the wire segments including an arc-shaped main-body portion made of a conductive wire rod bent in an arc shape, protruding portions formed at both end portions of the main-body portion, and upright portions respectively formed at end portions of the protruding portions in a manner of bending one of end portions of each of the protruding portions so that the upright portions protrude in a direction vertical relative to a planar surface including the main-body portion. The wire coil is arranged to form a plurality of layers, thereby forming a cylindrical shape, and the upright portions, at which the adjacent wire segments contact each other in the circumferential direction thereof, are electrically connected to each other.
摘要翻译：一种电动机线圈用配线部件，具有由圆周方向配置的多个线段构成的线圈构成环状，每个线段包括由导线形成的圆弧状的主体部杆弯曲成弧形，形成在主体部分的两个端部的突出部分和分别形成在突出部分的端部处的竖立部分，以弯曲每个突出部分的一个端部的方式使得直立部分在相对于包括主体部分的平面的垂直方向上突出。线圈被布置成形成多个层，从而形成圆柱形，并且相邻的线段在其圆周方向上彼此接触的直立部分彼此电连接。

20. 发明申请

US20120127816A1 SEMICONDUCTOR DEVICE HAVING HIERARCHICAL BIT LINE STRUCTURE 有权
标题翻译：具有分层线结构的半导体器件
公开(公告)号：US20120127816A1
公开(公告)日：2012-05-24
申请号：US13299285
申请日：2011-11-17
申请人： Kazuhiko Kajigaya , Yasutoshi Yamada
发明人： Kazuhiko Kajigaya , Yasutoshi Yamada
IPC分类号： G11C7/06 , G11C11/402
CPC分类号： G11C7/06 , G11C7/1048 , G11C8/12 , G11C11/402 , G11C11/406 , G11C11/4091 , G11C11/4097
摘要： Disclosed herein is a semiconductor device comprising a memory cell, a local bit line coupled to the memory cell, a global bit line provided correspondingly to the local bit line, and a bit line control circuit coupled between the local bit line and the global bit line. The bit line control circuit includes a restoring circuit that is activated in a refresh mode to refresh data of the memory cell while being in electrical isolation from the global bit line.
摘要翻译：本文公开了一种半导体器件，包括存储器单元，耦合到存储器单元的局部位线，对应于局部位线提供的全局位线，以及耦合在局部位线和全局位线之间的位线控制电路。位线控制电路包括在刷新模式下被激活以在与全局位线电隔离的同时刷新存储器单元的数据的恢复电路。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式