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11. 发明授权

US07107344B2 Connection allocation technology 失效
标题翻译：连接分配技术
公开(公告)号：US07107344B2
公开(公告)日：2006-09-12
申请号：US09931540
申请日：2001-08-16
申请人： Gordon Taylor Davis , Clark Debs Jeffries , Mark Anthony Rinaldi
发明人： Gordon Taylor Davis , Clark Debs Jeffries , Mark Anthony Rinaldi
IPC分类号： G06F15/16
CPC分类号： H04L69/16 , H04L67/14 , H04L69/163
摘要： A method and apparatus useful in network management which makes intelligent, high speed, connection allocation decisions, overcoming difficulties encountered heretofore and providing enhanced network services. During episodes of network congestion, some connection requests for a class of service of low value and with currently a high number of existing connections may be purposefully ignored (not acknowledged with an Acknowledge (ACK) packet) so that the processing capability of a device will not become overwhelmed, causing the dropping of new connection is to note the numbers of connections of different classes relative to their service-level contracts, to ignore abundant, low-value connection requests in accordance with value policies when and only when necessary, and to insure that valuable new connection requests that conform to their contract connection rates can be intelligently accommodated.
摘要翻译：一种在网络管理中有用的方法和装置，其实现智能，高速，连接分配决策，克服迄今遇到的困难并提供增强的网络服务。在网络拥塞发生期间，可以有目的地忽略一些低价值服务和当前具有大量现有连接的连接请求（未被确认（ACK）分组确认），使得设备的处理能力将不会变得不堪重负，导致新连接的下降是注意到不同类别与其服务级别合同的连接数量，当且仅在必要时根据价值政策忽略丰富的低价值连接请求，并且确保符合其合同连接率的有价值的新连接请求可以被智能地适应。

12. 发明授权

US06870811B2 Quality of service functions implemented in input interface circuit interface devices in computer network hardware 失效
标题翻译：服务质量在计算机网络硬件的输入接口电路接口设备中实现
公开(公告)号：US06870811B2
公开(公告)日：2005-03-22
申请号：US09764954
申请日：2001-01-18
申请人： Kenneth James Barker , Gordon Taylor Davis , Clark Debs Jeffries , Mark Anthony Rinaldi , Kartik Sudeep
发明人： Kenneth James Barker , Gordon Taylor Davis , Clark Debs Jeffries , Mark Anthony Rinaldi , Kartik Sudeep
IPC分类号： H04L12/56 , H04L12/28
CPC分类号： H04L47/32 , H04L47/10 , H04L47/12
摘要： The decision to discard or forward a packet is made by a flow control mechanism, upstream from the forwarding engine in the node of a communication network. The forwarding engine includes a switch with mechanism to detect congestion in the switch and return a binary signal B indicating congestion or no congestion. The flow control mechanism uses B and other network related information to generate a probability transmission table against which received packets are tested to determine proactively whether a packet is to be discarded or forwarded.
摘要翻译：通过在通信网络的节点中的转发引擎的上游的流控制机制来进行丢弃或转发分组的决定。转发引擎包括具有检测交换机拥塞的机制的交换机，并返回指示拥塞或不拥塞的二进制信号B. 流控制机制使用B和其他网络相关信息来生成概率传输表，对其接收到的分组进行测试，以主动确定分组是否被丢弃或转发。

13. 发明授权

US06829697B1 Multiple logical interfaces to a shared coprocessor resource 失效
标题翻译：到共享协处理器资源的多个逻辑接口
公开(公告)号：US06829697B1
公开(公告)日：2004-12-07
申请号：US09656582
申请日：2000-09-06
申请人： Gordon Taylor Davis , Marco C. Heddes , Ross Boyd Leavens , Mark Anthony Rinaldi
发明人： Gordon Taylor Davis , Marco C. Heddes , Ross Boyd Leavens , Mark Anthony Rinaldi
IPC分类号： G06F1500
CPC分类号： G06F15/7864
摘要： An embedded processor complex contains multiple protocol processor units (PPUs). Each unit includes at least one, and preferably two independently functioning core language processors (CLPs). Each CLP supports dual threads thread which interact through logical coprocessor execution or data interfaces with a plurality of special purpose coprocessors that serve each PPU. Operating instructions enable the PPU to identify long and short latency events and to control and shift priority for thread execution based on this identification. The instructions also enable the conditional execution of specific coprocessor operations upon the occurrence or non occurrence of certain specified events.
摘要翻译：嵌入式处理器复合体包含多个协议处理器单元（PPU）。每个单元包括至少一个，优选两个独立运行的核心语言处理器（CLP）。每个CLP支持双线程线程，其通过逻辑协处理器执行或数据接口与多个为每个PPU服务的专用协处理器进行交互。操作指令使PPU能够识别长时间和短的延迟事件，并根据此标识控制和转移线程执行的优先级。指令还可以在某些指定事件的发生或不发生时使特定协处理器操作的条件执行。

14. 发明授权

US06637019B1 Software modeling of computer hardware 有权
标题翻译：计算机硬件的软件建模
公开(公告)号：US06637019B1
公开(公告)日：2003-10-21
申请号：US09546458
申请日：2000-04-10
申请人： Mark Anthony Rinaldi
发明人： Mark Anthony Rinaldi
IPC分类号： G06F944
CPC分类号： G06F8/34
摘要： Software modeling of hardware components is conducted by partitioning the software into components or parts that are comparable to the components of the hardware. The parts are then configured through the use of plugs and connectors to replicate the hardware. The plugs are either import, export, splitter or compound plugs. The connectors ensure that the parts are capable of interfacing with one another in a communicative manner.
摘要翻译：通过将软件分成与硬件组件相当的组件或部件来实现硬件组件的软件建模。然后通过使用插头和连接器配置部件来复制硬件。插头是导入，导出，分配器或复合插头。连接器确保部件能够以交际的方式相互接触。

15. 发明授权

US06463500B1 Apparatus and method to access computer memory by processing object data as sub-object and shape parameter 失效
公开(公告)号：US06463500B1
公开(公告)日：2002-10-08
申请号：US09477775
申请日：2000-01-04
申请人： Marco C. Heddes , Piyush Chunilal Patel , Mark Anthony Rinaldi
发明人： Marco C. Heddes , Piyush Chunilal Patel , Mark Anthony Rinaldi
IPC分类号： G06F1200
CPC分类号： G06F17/30607 , G06F12/0207 , G06F17/3061
摘要： A method is provided for utilizing a memory system which allows for the fast and efficient writing and reading of objects to and from diverse memory chips. A computer system and memory system complex according to method is also provided. The invention defines objects in terms of “shapes.” The shape of an object is defined by two parameters: “Width” and “Height.” Memory system memory chips may comprise sets of different kinds of memory modules which vary in terms of access speed, latency and memory width, such as for example DRAM or SRAM memory modules. The Height of an object denotes the number of consecutive address locations at which the object is stored on a memory module. The Width of an object denotes the number of memory modules at which the object is stored. An advantage of the invention is that objects are defined in terms of “sub-objects” optimized for the memory system memory modules. The sub-objects match the line-width of the memory, thereby allowing the objects to be efficiently written to different memories or memory banks. A further advantage of the invention is that the sub-object shape is transparent to the requester (i.e. transparent to application assembly language). A further advantage of the invention is that sub-objects are handled independently by the memory arbiter, i.e. they can be written to the memory or read from the memory in any order. The complex may further comprise a Tree Search Memory (TSM) system that utilizes a “tree” object hierarchy to perform high-speed memory lookups. Shaping is used to specify how an object is stored in the TSM. The trees consist of different kinds of objects with different shapes. An important advantage of the invention is that the concept of shapes can be used for memory bandwidth distribution and performance increase, allowing objects that are frequently read from memory to be distributed in specific sub-object ordering.

16. 发明授权

US07116664B2 Lookups by collisionless direct tables and CAMs 失效
标题翻译：通过无碰撞直接表和CAM进行查找
公开(公告)号：US07116664B2
公开(公告)日：2006-10-03
申请号：US10144610
申请日：2002-05-13
申请人： Gordon Taylor Davis , Andreas Guenther Herkersdorf , Clark Debs Jeffries , Mark Anthony Rinaldi
发明人： Gordon Taylor Davis , Andreas Guenther Herkersdorf , Clark Debs Jeffries , Mark Anthony Rinaldi
IPC分类号： G06F12/00 , H04L12/56
CPC分类号： H04L49/3009 , H04L45/745 , H04L45/7453 , H04L49/351
摘要： A structure and technique for preventing collisions using a hash table in conjunction with a CAM to identify and prevent collisions of binary keys. A portion of the hash value of a binary key, which does not collide with a portion of the hash value of any other reference binary key, is used as an entry in the hash table. If two or more binary keys have identical values of the portions of the hash values, each of these binary keys are stored in their entirety, in the CAM. The key in the CAM provides a pointer to a data structure where the action associated with that binary key is stored. If the binary key is not found in the CAM, the binary key is hashed, and a specific entry in the hash table is selected using a portion of this hash value.
摘要翻译：一种用于使用散列表与CAM结合来防止冲突的结构和技术，以识别和防止二进制键的冲突。不与任何其他参考二进制密钥的散列值的一部分相冲突的二进制密钥的散列值的一部分被用作散列表中的条目。如果两个或更多个二进制密钥具有相同的哈希值部分的值，则这些二进制密钥中的每一个都将全部存储在CAM中。 CAM中的关键字提供了指向数据结构的指针，其中存储与该二进制密钥相关联的动作。如果在CAM中没有找到二进制密钥，则二进制密钥被散列，并且使用该哈希值的一部分来选择散列表中的特定条目。

17. 发明授权

US07107265B1 Software management tree implementation for a network processor 失效
标题翻译：网络处理器的软件管理树实现
公开(公告)号：US07107265B1
公开(公告)日：2006-09-12
申请号：US09545100
申请日：2000-04-06
申请人： Jean Louis Calvignac , Marco C. Heddes , Clark Debs Jeffries , Piyush Chunilal Patel , Mark Anthony Rinaldi
发明人： Jean Louis Calvignac , Marco C. Heddes , Clark Debs Jeffries , Piyush Chunilal Patel , Mark Anthony Rinaldi
IPC分类号： G06F17/30 , G06F15/00 , G06F9/44
CPC分类号： H04L45/742 , G06F17/30961 , G06F17/30985 , Y10S707/99933 , Y10S707/99936 , Y10S707/99937
摘要： Novel data structures, methods and apparatus for a Software Managed Tree (SMT) which provides a mechanism to create tree structures that follow a search mechanism defined by a control point processor. The search mechanism does not require storage on the previous pointer and uses only a forward pointer along with a next bit or group of bits to test thereby reducing storage space for nodes. The search mechanism processes multiple filter rules for an application without requiring multiple searches and also allows various filter rules to be chained. Two patterns of the same length are stored in each leaf to define a range compare. A compare at the end operation is either a compare under range or a compare under mask. In a compare under range, the input key is checked to determine if it is in the range defined by the two patterns. In a compare under mask, the bits in the input key are compared with the bits in a first leaf pattern under a mask specified in a second leaf pattern.
摘要翻译：用于软件管理树（SMT）的新型数据结构，方法和装置，其提供了一种机制，用于创建遵循由控制点处理器定义的搜索机制的树结构。搜索机制不需要在前一个指针上存储，并且仅使用前向指针以及下一个位或一组位来进行测试，从而减少节点的存储空间。搜索机制处理应用程序的多个过滤器规则，而不需要多次搜索，并且还允许链接各种过滤器规则。在每个叶中存储相同长度的两个图案以定义范围比较。在最终操作中的比较是在范围之下的比较或掩码下的比较。在范围比较范围内，检查输入键以确定是否在两种模式定义的范围内。在掩码下的比较中，将输入密钥中的比特与在第二叶图案中指定的掩码下的第一叶图案中的比特进行比较。

18. 发明授权

US06588008B1 Assembler tool for processor-coprocessor computer systems 失效
标题翻译：处理器 - 协处理器计算机系统的汇编工具
公开(公告)号：US06588008B1
公开(公告)日：2003-07-01
申请号：US09546755
申请日：2000-04-11
申请人： Marco C. Heddes , Ross Boyd Leavens , Mark Anthony Rinaldi
发明人： Marco C. Heddes , Ross Boyd Leavens , Mark Anthony Rinaldi
IPC分类号： G06F945
CPC分类号： G06F9/30043 , G06F8/47 , G06F9/30101 , G06F9/30145 , G06F9/30167 , G06F9/3885
摘要： A central processor-coprocessor assembly comprising an assembler software tool for extending the base central processor tasks into at least one coprocessor. What is important is that the assembler software tool does not need to be rebuilt when changes are made to the coprocessor elements. The invention allows assembly time extension of a base core language processing (CLP) programming model, without the need to rebuild the assembler tool itself. The assembler tool comprises a set of commands which enable the central processor to manipulate the coprocessor registers, and a coprocessor execute instruction, which initiates command processing on the coprocessor. The present invention simplifies the maintenance of the assembler tool through multiple hardware revisions by enabling hardware designers to update their coprocessor definition files to reflect new or modified coprocessors.
摘要翻译：一种中央处理器 - 协处理器组件，其包括用于将基本中央处理器任务扩展到至少一个协处理器的汇编器软件工具。重要的是，当对协处理器元素进行更改时，汇编程序软件工具不需要重新构建。本发明允许基本核心语言处理（CLP）编程模型的组装时间扩展，而不需要重建汇编器工具本身。汇编器工具包括使得中央处理器能够操纵协处理器寄存器的一组命令，以及协处理器执行指令，其在协处理器上启动命令处理。本发明通过使得硬件设计者能够更新其协处理器定义文件以反映新的或修改的协处理器，通过多个硬件修订来简化了汇编工具的维护。

19. 发明授权

US06298340B1 System and method and computer program for filtering using tree structure 失效
标题翻译：使用树结构进行过滤的系统和方法以及计算机程序
公开(公告)号：US06298340B1
公开(公告)日：2001-10-02
申请号：US09312148
申请日：1999-05-14
申请人： Jean Louis Calvignac , Everett Arthur Corl, Jr. , Anthony Matteo Gallo , Marco C. Heddes , Clark Debs Jeffries , Piyush Chunilal Patel , Mark Anthony Rinaldi , Colin Beaton Verrilli
发明人： Jean Louis Calvignac , Everett Arthur Corl, Jr. , Anthony Matteo Gallo , Marco C. Heddes , Clark Debs Jeffries , Piyush Chunilal Patel , Mark Anthony Rinaldi , Colin Beaton Verrilli
IPC分类号： G06F1730
CPC分类号： G06F17/30961 , Y10S707/99931 , Y10S707/99933 , Y10S707/99943 , Y10S707/99944
摘要： A classification system includes a software managed tree testing bits from a key which labels an item. The bits are chosen by application of the Choice Bit Algorithm to the Rules in a Database of Rules. A controller including logic parses an unknown Key for bits to be tested in the decision nodes of a binary tree. Tests dictated by the tree are conducted in a predetermined way until all but one Rule from the database or all but a few Rules from the database are eliminated from consideration, whereupon the Key is fully tested by the one remaining Rule or in a lattice constructed of the remaining plurality of Rules, to determine an action to enforce on the item. Certain compare tests are used in the binary tree for the case that otherwise identical or similar rules are applied to integer ranges of key values which do not fall upon power of 2 boundaries. Furthermore, some very frequently occurring rules in such final tests might be designated as secondary rules, the remaining rules designated as primary rules, the entire decision tree recalculated using only primary rules, and the primary rules then connected to secondary rules only when logically necessary by means of a system of pointers making use of relative priorities of rules.
摘要翻译：分类系统包括从标签项目的键的软件管理树测试位。通过将选择位算法应用于规则数据库中的规则来选择位。包含逻辑的控制器在二叉树的决策节点中解析要测试的位的未知密钥。由树进行的测试以预定的方式进行，直到从数据库中除了一个规则之外的所有除了数据库中的所有规则或从数据库中除了少数几个规则之外的所有测试都被消除，由此Key被完整的一个规则或由剩余的多个规则，以确定对该项目执行的操作。在二叉树中使用某些比较测试，否则相同或相似的规则应用于不落在2边界的幂的关键值的整数范围。此外，这些最终测试中的一些非常频繁出现的规则可能被指定为次要规则，剩余的规则被指定为主要规则，仅使用主要规则重新计算的整个决策树，然后仅在逻辑上必要时连接到次级规则的主要规则使用指针的相对优先级的指针系统的手段。

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