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11. 发明授权

US07812749B2 DC offset detection and correction for user traffic 有权
标题翻译： DC偏移检测和用户流量校正
公开(公告)号：US07812749B2
公开(公告)日：2010-10-12
申请号：US12380639
申请日：2009-03-02
申请人： Christopher Abel , Mohammad Mobin , Robert Kapuschinsky , Lane Smith , Paul Tracy , Gregory Sheets
发明人： Christopher Abel , Mohammad Mobin , Robert Kapuschinsky , Lane Smith , Paul Tracy , Gregory Sheets
IPC分类号： H03M1/06
CPC分类号： H04L25/061
摘要： In described embodiments, a communication system employing, for example, clock and data recovery (CDR) detects and applies correction for DC offset in an input data stream signal, termed as “DC offset calibration”. DC offset calibration applies static calibration for DC offset in input circuits, such as an input amplifier and detection latches, without input data, and applies statistical calibration for DC offset during operation with an input data stream to correct for dynamic shifts in DC level. Such DC offset calibration employs data eye measurements of the input data stream for detection of DC offset, and applies an opposite DC offset to maintain a relatively balanced data eye during live traffic.
摘要翻译：在所描述的实施例中，采用例如时钟和数据恢复（CDR）的通信系统在输入数据流信号中检测并应用校正DC偏移，称为“DC偏移校准”。 DC偏移校准在输入电路（如输入放大器和检测锁存器）中对直流偏移进行静态校准，无输入数据，并在输入数据流运行期间对DC偏移进行统计校准，以校正直流电平的动态偏移。这种DC偏移校准使用用于检测DC偏移的输入数据流的数据眼睛测量，并施加相反的DC偏移以在实时业务期间维持相对平衡的数据眼睛。

12. 发明申请

US20070074084A1 Method and apparatus for monitoring and compensating for skew on a high speed parallel bus 有权
标题翻译：用于监视和补偿高速并行总线上的偏斜的方法和装置
公开(公告)号：US20070074084A1
公开(公告)日：2007-03-29
申请号：US11235872
申请日：2005-09-27
申请人： Mohammad Mobin , Gregory Sheets , Lane Smith
发明人： Mohammad Mobin , Gregory Sheets , Lane Smith
IPC分类号： G11B20/20 , G06K5/04 , G11B5/00
CPC分类号： G06F13/4213
摘要： Methods and apparatus are provided for monitoring and compensating for skew on a high speed parallel bus. Delay skew for a plurality of signals on a parallel bus is monitored by obtaining a plurality of samples of the plurality of signals for each unit interval; and identifying a location of transitions in the plurality of signals based on the samples. The samples can be obtained, for example, by sampling the plurality of signals using a plurality of latches and estimating a value of one or more of the plurality of signals by comparing values of the latches. A microprocessor can optionally be employed to determine a relative distribution of transitions in the plurality of signals and to align transitions in the plurality of signals to a common position. The transitions in the plurality of signals can be aligned to a common position by adjusting a delay control setting for a buffer associated with each of the plurality of signals.
摘要翻译：提供了用于监视和补偿高速并行总线上的偏斜的方法和装置。通过获得每个单位间隔的多个信号的多个样本来监视并行总线上的多个信号的延迟偏移; 以及基于所述样本来识别所述多个信号中的转变的位置。可以例如通过使用多个锁存器对多个信号进行采样并且通过比较锁存器的值来估计多个信号中的一个或多个的值来获得样本。可以可选地使用微处理器来确定多个信号中的转变的相对分布并且将多个信号中的转变对准到公共位置。通过调整与多个信号中的每个信号相关联的缓冲器的延迟控制设置，多个信号中的转换可以对齐到公共位置。

13. 发明申请

US20070018694A1 HIGH-SPEED CML CIRCUIT DESIGN 有权
标题翻译：高速CML电路设计
公开(公告)号：US20070018694A1
公开(公告)日：2007-01-25
申请号：US11421675
申请日：2006-06-01
申请人： Jinghong Chen , Gregory Sheets , Lane Smith
发明人： Jinghong Chen , Gregory Sheets , Lane Smith
IPC分类号： H03K19/094
CPC分类号： H03K19/09432 , H03K19/01707
摘要： A current mode logic digital circuit is provided comprising a logic circuit component having at least one data input node and at least one output node. A load is coupled between a power supply node and the output node. The load comprises a folded active inductor coupled to the output node.
摘要翻译：提供了一种电流模式逻辑数字电路，包括具有至少一个数据输入节点和至少一个输出节点的逻辑电路组件。负载耦合在电源节点和输出节点之间。负载包括耦合到输出节点的折叠有源电感器。

14. 发明申请

US20070013440A1 ANALOG AMPLIFIER HAVING DC OFFSET CANCELLATION CIRCUIT AND METHOD OF OFFSET CANCELLATION FOR ANALOG AMPLIFIERS 有权
标题翻译：具有直流偏移消除电路的模拟放大器和模拟放大器偏移消除方法
公开(公告)号：US20070013440A1
公开(公告)日：2007-01-18
申请号：US11420177
申请日：2006-05-24
申请人： Jinghong Chen , Gregory Sheets , Joseph Anidjar , Robert Kapuschinsky , Lane Smith
发明人： Jinghong Chen , Gregory Sheets , Joseph Anidjar , Robert Kapuschinsky , Lane Smith
IPC分类号： H03F1/02
CPC分类号： H03F3/45973 , H03F3/45977 , H03F2203/45101 , H03F2203/45434 , H03F2203/45564 , H03F2203/45588 , H03F2203/45622
摘要： An amplifier having DC offset compensation includes at least one input node and a pair of differential output nodes, a biasing circuit coupled to the input node; and a plurality of current sources. Selected ones of said current sources are coupled to the input node to adjust a DC voltage at the input node to provide DC offset compensation for the amplifier
摘要翻译：具有DC偏移补偿的放大器包括至少一个输入节点和一对差分输出节点，耦合到输入节点的偏置电路; 和多个电流源。所选择的所述电流源耦合到输入节点以调整输入节点处的DC电压，以为放大器提供DC偏移补偿

15. 发明申请

US20060215782A1 Methods and apparatus for asynchronous serial channel connections in communication systems 有权
标题翻译：通信系统中异步串行通道连接的方法和装置
公开(公告)号：US20060215782A1
公开(公告)日：2006-09-28
申请号：US11089216
申请日：2005-03-24
申请人： Yasser Ahmed , Robert Brink , Gregory Sheets , Lane Smith
发明人： Yasser Ahmed , Robert Brink , Gregory Sheets , Lane Smith
IPC分类号： H04L27/10
CPC分类号： H04L7/0012 , H04J3/0638 , H04L7/005
摘要： An integrated circuit device for use in a node of a communication system is provided. The integrated circuit device includes a memory configured to store data written thereto by a receiver associated with the node in accordance with a receiver clock, and to read data therefrom by a transmitter associated with the node in accordance with a transmitter clock. The integrated circuit device also includes a control logic circuit that is in communication with the memory, and is configured to send a control signal to the transmitter to adjust a speed of the transmitter clock responsive to an operating condition of the memory.
摘要翻译：提供一种在通信系统的节点中使用的集成电路装置。集成电路装置包括被配置为存储由根据接收机时钟与节点相关联的接收机写入的数据的存储器，并且根据发射机时钟由与节点相关联的发射机从其读取数据。集成电路装置还包括与存储器通信的控制逻辑电路，并且被配置为响应于存储器的操作条件向发射器发送控制信号以调整发射机时钟的速度。

16. 发明申请

US20070195874A1 Method and apparatus for generating one or more clock signals for a decision-feedback equalizer using DFE detected data 有权
标题翻译：用于使用DFE检测数据为判决反馈均衡器生成一个或多个时钟信号的方法和装置
公开(公告)号：US20070195874A1
公开(公告)日：2007-08-23
申请号：US11356691
申请日：2006-02-17
申请人： Pervez Aziz , Gregory Sheets , Lane Smith
发明人： Pervez Aziz , Gregory Sheets , Lane Smith
IPC分类号： H03H7/30 , H04L7/00
CPC分类号： H04L7/0062 , H04L7/033 , H04L7/04 , H04L2025/0349
摘要： Methods and apparatus are provided for generating one or more clock signals for a decision-feedback equalizer using DFE detected data. A received signal is sampled using a data clock and a transition clock to generate a data sample signal and a transition sample signal, respectively. A DFE correction is obtained for each of the data sample and transition sample signals to generate DFE detected data and a DFE transition data. The DFE detected data and DFE transition data are then applied to a phase detector that generates a signal to adjust a phase of one or more of the data clock and transition clock. In a multi-level implementation, the received signal is sampled using a clock associated with each of the levels and the samples are latched using a vertical slicing technique to generate DFE data associated with each of said levels.
摘要翻译：提供了用于使用DFE检测数据为判决反馈均衡器生成一个或多个时钟信号的方法和装置。使用数据时钟和转换时钟对接收到的信号进行采样，以分别产生数据采样信号和转换采样信号。为每个数据采样和转换采样信号获得DFE校正，以产生DFE检测数据和DFE转换数据。 DFE检测数据和DFE转换数据然后被施加到产生信号以调整数据时钟和转换时钟中的一个或多个的相位的相位检测器。在多级实现中，使用与每个级别相关联的时钟对接收到的信号进行采样，并且使用垂直限幅技术来锁存样本以生成与每个所述级别相关联的DFE数据。

17. 发明授权

US07570708B2 Serdes auto calibration and load balancing 有权
标题翻译： Serdes自动校准和负载平衡
公开(公告)号：US07570708B2
公开(公告)日：2009-08-04
申请号：US11046669
申请日：2005-01-31
申请人： Donald Laturell , Gregory Sheets , Lane Smith , Mohammad S. Mobin
发明人： Donald Laturell , Gregory Sheets , Lane Smith , Mohammad S. Mobin
IPC分类号： H04K1/02
CPC分类号： H04L1/205
摘要： The present invention is used to automatically calibrate a SERDES device by utilizing information provided in the eye diagram of the received signal. In particular, the invention mitigates the components of determininistic jitter, such as ISI and frequency distortion. To achieve this goal, the invention enables the receive side of the SERDES to evaluate the quality of the eye received using a cost function. The invention calculates the cost function associated with the received data and then uses this information to effect an auto calibration of the SERDES device.
摘要翻译：本发明用于通过利用在接收信号的眼图中提供的信息来自动校准SERDES设备。特别地，本发明减轻了确定性抖动的组成部分，例如ISI和频率失真。为了实现这个目标，本发明使得SERDES的接收端能够使用成本函数评估所接收的眼睛的质量。本发明计算与接收到的数据相关联的成本函数，然后使用该信息来实现SERDES设备的自动校准。

18. 发明申请

US20070214277A1 Peer-to-peer network communications using SATA/SAS technology 审中-公开
标题翻译：使用SATA / SAS技术的对等网络通信
公开(公告)号：US20070214277A1
公开(公告)日：2007-09-13
申请号：US11444845
申请日：2006-05-31
申请人： Ali Ahmed , Gregory Sheets , Lane Smith , David Thompson
发明人： Ali Ahmed , Gregory Sheets , Lane Smith , David Thompson
IPC分类号： G06F15/16
CPC分类号： H04L12/2838 , H04L69/03 , H04L69/32
摘要： A conventional serial communications protocol that is limited to supporting only host-to-slave communications, such as SATA or SAS, is extended to support peer-to-peer communications, e.g., by adding a memory-map layer into the conventional protocol stack between the link layer and the protocol layer. The addition of the memory-map layer enables two (or more) non-host devices (i.e., peer devices) to communicate with one another without using a host computer and without relying on conventional protocol-bridging techniques.
摘要翻译：仅限于支持诸如SATA或SAS的主机到从机通信的常规串行通信协议被扩展以支持对等通信，例如通过将存储器映射层添加到常规协议栈之间链路层和协议层。存储器映射图层的添加使得两个（或多个）非主机设备（即，对等设备）彼此通信，而不使用主计算机，而不依赖于传统的协议桥接技术。

19. 发明申请

US20070237275A1 Method and apparatus for a time domain zero phase start using binary sampled data 审中-公开
标题翻译：使用二进制采样数据的时域零相位开始的方法和装置
公开(公告)号：US20070237275A1
公开(公告)日：2007-10-11
申请号：US11399647
申请日：2006-04-06
申请人： Pervez Aziz , Gregory Sheets
发明人： Pervez Aziz , Gregory Sheets
IPC分类号： H04L7/00
CPC分类号： H04L7/042 , H04L7/10 , H04L2007/047
摘要： Methods and apparatus are provided for obtaining a phase offset estimate from a data stream. A binary sampled version of the data stream is obtained based on a clock. A first dot product of the binary sampled version of the data stream and an ideal sequence and a second dot product of the binary sampled version of the data stream and a delayed ideal sequence are accumulated. A phase offset of the clock is adjusted until the accumulated first and second dot product satisfy one or more predefined conditions. For example, the predefined conditions can comprise a transition of at least one of the accumulated first and second dot product or whether at least one of the accumulated first and second dot product transition to a final value.
摘要翻译：提供了用于从数据流获得相位偏移估计的方法和装置。基于时钟获得数据流的二进制采样版本。数据流的二进制采样版本和数据流的二进制采样版本和延迟的理想序列的理想序列和第二点积的第一点积积分。调整时钟的相位偏移，直到累积的第一和第二点积满足一个或多个预定条件。例如，预定条件可以包括累积的第一和第二点积中的至少一个的过渡，或者累积的第一和第二点积转换中的至少一个是否到最终值。

20. 发明申请

US20070206711A1 Method and apparatus for reducing latency in a clock and data recovery (CDR) circuit 有权
标题翻译：用于减少时钟和数据恢复（CDR）电路中的延迟的方法和装置
公开(公告)号：US20070206711A1
公开(公告)日：2007-09-06
申请号：US11367214
申请日：2006-03-03
申请人： Pervez Aziz , Gregory Sheets
发明人： Pervez Aziz , Gregory Sheets
IPC分类号： H03D3/24
CPC分类号： H03D13/003 , H03L7/081 , H03L7/0812 , H03L7/087 , H03L7/093 , H04L7/033
摘要： Disclosed is a system and method for a clock and data recovery (CDR) circuit. A phase selection circuit (PSC) generates a signal comprising frequency and phase. A voltage controlled oscillator (VCO) connected to the PSC generates a clock signal. The clock signal controls the frequency of the signal. The CDR circuit also includes a phase adjustment signal generator connected to the PSC for generating a phase adjustment signal. The phase adjustment signal controls the phase of the signal.
摘要翻译：公开了一种用于时钟和数据恢复（CDR）电路的系统和方法。相位选择电路（PSC）产生包括频率和相位的信号。连接到PSC的压控振荡器（VCO）产生时钟信号。时钟信号控制信号的频率。 CDR电路还包括连接到PSC的相位调整信号发生器，用于产生相位调整信号。相位调整信号控制信号的相位。

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