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1. 发明申请

US20060215782A1 Methods and apparatus for asynchronous serial channel connections in communication systems 有权
标题翻译：通信系统中异步串行通道连接的方法和装置
公开(公告)号：US20060215782A1
公开(公告)日：2006-09-28
申请号：US11089216
申请日：2005-03-24
申请人： Yasser Ahmed , Robert Brink , Gregory Sheets , Lane Smith
发明人： Yasser Ahmed , Robert Brink , Gregory Sheets , Lane Smith
IPC分类号： H04L27/10
CPC分类号： H04L7/0012 , H04J3/0638 , H04L7/005
摘要： An integrated circuit device for use in a node of a communication system is provided. The integrated circuit device includes a memory configured to store data written thereto by a receiver associated with the node in accordance with a receiver clock, and to read data therefrom by a transmitter associated with the node in accordance with a transmitter clock. The integrated circuit device also includes a control logic circuit that is in communication with the memory, and is configured to send a control signal to the transmitter to adjust a speed of the transmitter clock responsive to an operating condition of the memory.
摘要翻译：提供一种在通信系统的节点中使用的集成电路装置。集成电路装置包括被配置为存储由根据接收机时钟与节点相关联的接收机写入的数据的存储器，并且根据发射机时钟由与节点相关联的发射机从其读取数据。集成电路装置还包括与存储器通信的控制逻辑电路，并且被配置为响应于存储器的操作条件向发射器发送控制信号以调整发射机时钟的速度。

2. 发明申请

US20060114811A1 Multilevel amplitude modulated signaling in fibre channel 有权
公开(公告)号：US20060114811A1
公开(公告)日：2006-06-01
申请号：US10998679
申请日：2004-11-29
申请人： Ali Ahmed , Robert Brink , Gregory Sheets , Lane Smith
发明人： Ali Ahmed , Robert Brink , Gregory Sheets , Lane Smith
IPC分类号： H04J9/00
CPC分类号： H04L25/4908 , H04L27/04 , H04L27/06
摘要： In a communication system comprising first and second nodes, a multilevel amplitude modulated signaling technique is utilized. The first and second nodes may communicate over a Fibre Channel link or other medium. The first and second nodes comprise respective transmitter and receiver pairs, with the transmitter of the first node configured for communication with the receiver of the second node and the receiver of the first node configured for communication with the transmitter of the second node. The first node is configured to generate a signal for transmission over a serial data channel to the second node, the signal having a multilevel amplitude modulated format in which, within a given clock cycle of the signal, multiple bits are represented by a given signal level.

3. 发明申请

US20090175395A1 DATA ALIGNMENT METHOD FOR ARBITRARY INPUT WITH PROGRAMMABLE CONTENT DESKEWING INFO 有权
标题翻译：具有可编程内容描述信息的仲裁输入的数据对齐方法
公开(公告)号：US20090175395A1
公开(公告)日：2009-07-09
申请号：US11969440
申请日：2008-01-04
申请人： Yasser AHMED , Xingdong Dai , Vladimir Sindalovsky , Lane Smith
发明人： Yasser AHMED , Xingdong Dai , Vladimir Sindalovsky , Lane Smith
IPC分类号： H04L7/00
CPC分类号： H03M9/00 , H04L7/005 , H04L7/04
摘要： In an exemplary embodiment, a data alignment system comprises a First-In First-Out register (FIFO), a programmable pattern generator connected to the FIFO, and a controller connected to the programmable pattern generator and the FIFO. The FIFO is configured to provide data to or receive data from a first data lane of a serial data link having one or more lanes. Each data lane of the serial data link is configured to transmit a respective serial data stream. The programmable pattern generator is configured to generate a plurality of alignment symbols. The controller is configured to manage the alignment of the one or more data lanes of the serial data link and the insertion of a selected one of the plurality of alignment symbols into each of the serial data streams.
摘要翻译：在示例性实施例中，数据对准系统包括先进先出寄存器（FIFO），连接到FIFO的可编程模式发生器和连接到可编程模式发生器和FIFO的控制器。 FIFO被配置为向具有一个或多个通道的串行数据链路的第一数据通道提供数据或从其接收数据。串行数据链路的每个数据通道被配置为发送相应的串行数据流。可编程模式发生器被配置为生成多个对准符号。控制器被配置为管理串行数据链路的一个或多个数据通道的对准以及将多个对准符号中选择的一个对准符号插入到每个串行数据流中。

4. 发明申请

US20080010552A1 Method and apparatus for testing a dual mode interface 有权
标题翻译：用于测试双模式接口的方法和装置
公开(公告)号：US20080010552A1
公开(公告)日：2008-01-10
申请号：US11418401
申请日：2006-05-04
申请人： Yasser Ahmed , Robert Kapuschinsky , Ashok Khandelwal , Samuel Khoo , Lane Smith
发明人： Yasser Ahmed , Robert Kapuschinsky , Ashok Khandelwal , Samuel Khoo , Lane Smith
IPC分类号： G06F11/00
CPC分类号： G06F11/221
摘要： Disclosed is a system and method for testing a dual mode interface. The dual mode interface includes a first strobe circuit and a second strobe circuit configured to be operable during a first operational mode and inoperable during a second operational mode. The dual mode interface also includes a first data circuit and a second data circuit configured to be operable during the first operational mode and the second operational mode. The dual mode interface also includes a signal line connecting an output of the second strobe circuit with an input of the first strobe circuit and a switch element configured to activate said signal line in response to receipt of a test signal.
摘要翻译：公开了用于测试双模式接口的系统和方法。双模式接口包括第一选通电路和第二选通电路，其被配置为在第一操作模式期间可操作并且在第二操作模式期间不可操作。双模式接口还包括第一数据电路和第二数据电路，其被配置为在第一操作模式和第二操作模式期间可操作。双模式接口还包括将第二选通电路的输出与第一选通电路的输入连接的信号线和被配置为响应于接收到测试信号而激活所述信号线的开关元件。

5. 发明授权

US07995695B2 Data alignment method for arbitrary input with programmable content deskewing info 有权
标题翻译：用于可编程内容的任意输入的数据对齐方法
公开(公告)号：US07995695B2
公开(公告)日：2011-08-09
申请号：US11969440
申请日：2008-01-04
申请人： Yasser Ahmed , Xingdong Dai , Vladimir Sindalovsky , Lane Smith
发明人： Yasser Ahmed , Xingdong Dai , Vladimir Sindalovsky , Lane Smith
IPC分类号： H04L7/00 , H04L25/00 , H04L25/40
CPC分类号： H03M9/00 , H04L7/005 , H04L7/04
摘要： In an exemplary embodiment, a data alignment system comprises a First-In First-Out register (FIFO), a programmable pattern generator connected to the FIFO, and a controller connected to the programmable pattern generator and the FIFO. The FIFO is configured to provide data to or receive data from a first data lane of a serial data link having one or more lanes. Each data lane of the serial data link is configured to transmit a respective serial data stream. The programmable pattern generator is configured to generate a plurality of alignment symbols. The controller is configured to manage the alignment of the one or more data lanes of the serial data link and the insertion of a selected one of the plurality of alignment symbols into each of the serial data streams.
摘要翻译：在示例性实施例中，数据对准系统包括先进先出寄存器（FIFO），连接到FIFO的可编程模式发生器和连接到可编程模式发生器和FIFO的控制器。 FIFO被配置为向具有一个或多个通道的串行数据链路的第一数据通道提供数据或从其接收数据。串行数据链路的每个数据通道被配置为发送相应的串行数据流。可编程模式发生器被配置为生成多个对准符号。控制器被配置为管理串行数据链路的一个或多个数据通道的对准以及将多个对准符号中选择的一个对准符号插入到每个串行数据流中。

6. 发明授权

US07812749B2 DC offset detection and correction for user traffic 有权
标题翻译： DC偏移检测和用户流量校正
公开(公告)号：US07812749B2
公开(公告)日：2010-10-12
申请号：US12380639
申请日：2009-03-02
申请人： Christopher Abel , Mohammad Mobin , Robert Kapuschinsky , Lane Smith , Paul Tracy , Gregory Sheets
发明人： Christopher Abel , Mohammad Mobin , Robert Kapuschinsky , Lane Smith , Paul Tracy , Gregory Sheets
IPC分类号： H03M1/06
CPC分类号： H04L25/061
摘要： In described embodiments, a communication system employing, for example, clock and data recovery (CDR) detects and applies correction for DC offset in an input data stream signal, termed as “DC offset calibration”. DC offset calibration applies static calibration for DC offset in input circuits, such as an input amplifier and detection latches, without input data, and applies statistical calibration for DC offset during operation with an input data stream to correct for dynamic shifts in DC level. Such DC offset calibration employs data eye measurements of the input data stream for detection of DC offset, and applies an opposite DC offset to maintain a relatively balanced data eye during live traffic.
摘要翻译：在所描述的实施例中，采用例如时钟和数据恢复（CDR）的通信系统在输入数据流信号中检测并应用校正DC偏移，称为“DC偏移校准”。 DC偏移校准在输入电路（如输入放大器和检测锁存器）中对直流偏移进行静态校准，无输入数据，并在输入数据流运行期间对DC偏移进行统计校准，以校正直流电平的动态偏移。这种DC偏移校准使用用于检测DC偏移的输入数据流的数据眼睛测量，并施加相反的DC偏移以在实时业务期间维持相对平衡的数据眼睛。

7. 发明申请

US20070074084A1 Method and apparatus for monitoring and compensating for skew on a high speed parallel bus 有权
标题翻译：用于监视和补偿高速并行总线上的偏斜的方法和装置
公开(公告)号：US20070074084A1
公开(公告)日：2007-03-29
申请号：US11235872
申请日：2005-09-27
申请人： Mohammad Mobin , Gregory Sheets , Lane Smith
发明人： Mohammad Mobin , Gregory Sheets , Lane Smith
IPC分类号： G11B20/20 , G06K5/04 , G11B5/00
CPC分类号： G06F13/4213
摘要： Methods and apparatus are provided for monitoring and compensating for skew on a high speed parallel bus. Delay skew for a plurality of signals on a parallel bus is monitored by obtaining a plurality of samples of the plurality of signals for each unit interval; and identifying a location of transitions in the plurality of signals based on the samples. The samples can be obtained, for example, by sampling the plurality of signals using a plurality of latches and estimating a value of one or more of the plurality of signals by comparing values of the latches. A microprocessor can optionally be employed to determine a relative distribution of transitions in the plurality of signals and to align transitions in the plurality of signals to a common position. The transitions in the plurality of signals can be aligned to a common position by adjusting a delay control setting for a buffer associated with each of the plurality of signals.
摘要翻译：提供了用于监视和补偿高速并行总线上的偏斜的方法和装置。通过获得每个单位间隔的多个信号的多个样本来监视并行总线上的多个信号的延迟偏移; 以及基于所述样本来识别所述多个信号中的转变的位置。可以例如通过使用多个锁存器对多个信号进行采样并且通过比较锁存器的值来估计多个信号中的一个或多个的值来获得样本。可以可选地使用微处理器来确定多个信号中的转变的相对分布并且将多个信号中的转变对准到公共位置。通过调整与多个信号中的每个信号相关联的缓冲器的延迟控制设置，多个信号中的转换可以对齐到公共位置。

8. 发明授权

US07570708B2 Serdes auto calibration and load balancing 有权
标题翻译： Serdes自动校准和负载平衡
公开(公告)号：US07570708B2
公开(公告)日：2009-08-04
申请号：US11046669
申请日：2005-01-31
申请人： Donald Laturell , Gregory Sheets , Lane Smith , Mohammad S. Mobin
发明人： Donald Laturell , Gregory Sheets , Lane Smith , Mohammad S. Mobin
IPC分类号： H04K1/02
CPC分类号： H04L1/205
摘要： The present invention is used to automatically calibrate a SERDES device by utilizing information provided in the eye diagram of the received signal. In particular, the invention mitigates the components of determininistic jitter, such as ISI and frequency distortion. To achieve this goal, the invention enables the receive side of the SERDES to evaluate the quality of the eye received using a cost function. The invention calculates the cost function associated with the received data and then uses this information to effect an auto calibration of the SERDES device.
摘要翻译：本发明用于通过利用在接收信号的眼图中提供的信息来自动校准SERDES设备。特别地，本发明减轻了确定性抖动的组成部分，例如ISI和频率失真。为了实现这个目标，本发明使得SERDES的接收端能够使用成本函数评估所接收的眼睛的质量。本发明计算与接收到的数据相关联的成本函数，然后使用该信息来实现SERDES设备的自动校准。

9. 发明申请

US20070253477A1 Method and apparatus for determining a position of an offset latch employed for decision-feedback equalization 有权
标题翻译：用于确定用于判决反馈均衡的偏移锁存器的位置的方法和装置
公开(公告)号：US20070253477A1
公开(公告)日：2007-11-01
申请号：US11414522
申请日：2006-04-28
申请人： Christopher Abel , Mohammad Mobin , Gregory Sheets , Vladimir Sindalovsky , Lane Smith
发明人： Christopher Abel , Mohammad Mobin , Gregory Sheets , Vladimir Sindalovsky , Lane Smith
IPC分类号： H03H7/30
CPC分类号： H04L25/062 , H04L25/03057
摘要： Methods and apparatus are provided for determining a position of an offset latch employed for decision-feedback equalization. The position of an offset latch is determined by obtaining a plurality of samples of a data eye associated with a signal, the data eye comprised of a plurality of trajectories for transitions out of a given binary state; determining an amplitude of at least two of the trajectories based on the samples; and determining a position of an offset latch based on the determined amplitudes. The initial position of the offset latch can be placed, for example, approximately in the middle of the determined amplitudes for at least two of the trajectories. The initial position of the offset latch can be optionally skewed by a predefined amount to improve the noise margin.
摘要翻译：提供了用于确定用于判决反馈均衡的偏移锁存器的位置的方法和装置。通过获得与信号相关联的数据眼睛的多个采样来确定偏移锁存器的位置，数据眼睛包括用于从给定二进制状态转换的多个轨迹; 基于样本确定至少两个轨迹的振幅; 以及基于所确定的振幅来确定偏移锁存器的位置。偏移锁存器的初始位置可以被放置在例如至少两个轨迹的确定幅度的大约中间。偏移锁存器的初始位置可以可选地倾斜预定义的量以改善噪声容限。

10. 发明申请

US20070214277A1 Peer-to-peer network communications using SATA/SAS technology 审中-公开
标题翻译：使用SATA / SAS技术的对等网络通信
公开(公告)号：US20070214277A1
公开(公告)日：2007-09-13
申请号：US11444845
申请日：2006-05-31
申请人： Ali Ahmed , Gregory Sheets , Lane Smith , David Thompson
发明人： Ali Ahmed , Gregory Sheets , Lane Smith , David Thompson
IPC分类号： G06F15/16
CPC分类号： H04L12/2838 , H04L69/03 , H04L69/32
摘要： A conventional serial communications protocol that is limited to supporting only host-to-slave communications, such as SATA or SAS, is extended to support peer-to-peer communications, e.g., by adding a memory-map layer into the conventional protocol stack between the link layer and the protocol layer. The addition of the memory-map layer enables two (or more) non-host devices (i.e., peer devices) to communicate with one another without using a host computer and without relying on conventional protocol-bridging techniques.
摘要翻译：仅限于支持诸如SATA或SAS的主机到从机通信的常规串行通信协议被扩展以支持对等通信，例如通过将存储器映射层添加到常规协议栈之间链路层和协议层。存储器映射图层的添加使得两个（或多个）非主机设备（即，对等设备）彼此通信，而不使用主计算机，而不依赖于传统的协议桥接技术。

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