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11. 发明授权

US06844590B2 Semiconductor device with trench isolation between two regions having different gate insulating films 失效
标题翻译：在具有不同栅极绝缘膜的两个区域之间具有沟槽隔离的半导体器件
公开(公告)号：US06844590B2
公开(公告)日：2005-01-18
申请号：US10180328
申请日：2002-06-27
申请人： Akira Goda , Mitsuhiro Noguchi , Yuji Takeuchi , Michiharu Matsui , Hiroaki Hazama
发明人： Akira Goda , Mitsuhiro Noguchi , Yuji Takeuchi , Michiharu Matsui , Hiroaki Hazama
IPC分类号： H01L27/115 , H01L21/762 , H01L21/8234 , H01L21/8246 , H01L27/105 , H01L29/792
CPC分类号： H01L27/11568 , H01L21/76232 , H01L21/823462 , H01L21/823481 , H01L27/105 , H01L27/11573
摘要： The major surface of a semiconductor substrate of a semiconductor device includes first and second regions and a boundary area therebetween. A first gate insulating film and a first gate electrode are formed in the first region. A second gate insulating film different from the first gate insulating film and a second gate electrode are formed in the second region. A device isolation region is formed in the boundary area. This device isolation region includes a trench formed in the major surface, and an insulating layer having a portion buried in the trench and a portion projecting upward from the major surface. The bottom of the trench has depths different with portions.
摘要翻译：半导体器件的半导体衬底的主表面包括第一和第二区域以及它们之间的边界区域。第一栅极绝缘膜和第一栅电极形成在第一区域中。在第二区域中形成与第一栅极绝缘膜和第二栅极电极不同的第二栅极绝缘膜。在边界区域形成器件隔离区。该器件隔离区域包括形成在主表面中的沟槽，以及绝缘层，其具有埋在沟槽中的部分和从主表面向上突出的部分。沟槽的底部具有与部分不同的深度。

12. 发明授权

US06809967B2 Data writing method for semiconductor memory device and semiconductor memory device 失效
标题翻译：半导体存储器件和半导体存储器件的数据写入方法
公开(公告)号：US06809967B2
公开(公告)日：2004-10-26
申请号：US10077757
申请日：2002-02-20
申请人： Mitsuhiro Noguchi , Akira Goda , Yuji Takeuchi
发明人： Mitsuhiro Noguchi , Akira Goda , Yuji Takeuchi
IPC分类号： G11C1606
CPC分类号： G11C16/3445 , G11C16/0416 , G11C16/0483 , G11C16/12 , G11C16/3468
摘要： A semiconductor integrated circuit device includes a first data transfer line electrically connected to a first memory cell block, a second data transfer line electrically connected to a second memory cell block, a charge circuit which charges any one of the first and second data transfer lines, a first data store circuit, second and third data store circuits electrically connected to the first data store circuit, a charge/discharge circuit which charges or discharges a voltage node on the basis of the data held in the third data store circuit, a first connecting circuit which electrically connects the voltage node to any one of the first and second data transfer lines, a fourth data store circuit, and a second connecting circuit which electrically connects the fourth data store circuit to the voltage node.
摘要翻译：半导体集成电路装置包括电连接到第一存储单元块的第一数据传送线，与第二存储单元块电连接的第二数据传送线，对第一和第二数据传送线中的任何一个进行充电的充电电路，电连接到第一数据存储电路的第一数据存储电路，第二和第三数据存储电路，基于保存在第三数据存储电路中的数据对电压节点进行充电或放电的充电/放电电路，第一连接将电压节点电连接到第一和第二数据传输线中的任一个的第一数据存储电路和将第四数据存储电路与电压节点电连接的第二连接电路。

13. 发明授权

US06784041B2 Semiconductor device and method of manufacturing the same 有权
公开(公告)号：US06784041B2
公开(公告)日：2004-08-31
申请号：US10727647
申请日：2003-12-05
申请人： Yuji Takeuchi , Masayuki Ichige , Akira Goda
发明人： Yuji Takeuchi , Masayuki Ichige , Akira Goda
IPC分类号： H01L218238
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524 , H01L2924/0002 , H01L2924/00
摘要： A NAND type semiconductor device is disclosed, in which a first insulating film embedded between the memory cell gates and between the memory cell gates and the selecting gate does not contain nitrogen as a major component, a second insulating film is formed on the first insulating film, and an interlayer insulating film is formed on the second insulating film whose major component is different from a manor component of the second insulating film.

14. 发明授权

US06720612B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06720612B2
公开(公告)日：2004-04-13
申请号：US10098130
申请日：2002-03-15
申请人： Yuji Takeuchi , Masayuki Ichige , Akira Goda
发明人： Yuji Takeuchi , Masayuki Ichige , Akira Goda
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524 , H01L2924/0002 , H01L2924/00
摘要： A NAND type semiconductor device is disclosed, in which a first insulating film embedded between the memory cell gates and between the memory cell gates and the selecting gate does not contain nitrogen as a major component, a second insulating film is formed on the first insulating film, and an interlayer insulating film is formed on the second insulating film whose major component is different from a major component of the second insulating film.
摘要翻译：公开了一种NAND型半导体器件，其中嵌入在存储单元栅极之间以及存储单元栅极和选择栅极之间的第一绝缘膜不包含氮作为主要成分，第二绝缘膜形成在第一绝缘膜上并且在主要成分不同于第二绝缘膜的主要成分的第二绝缘膜上形成层间绝缘膜。

15. 发明授权

US06611010B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06611010B2
公开(公告)日：2003-08-26
申请号：US09726582
申请日：2000-12-01
申请人： Akira Goda , Kazuhiro Shimizu , Yuji Takeuchi , Riichiro Shirota , Seiichi Aritome
发明人： Akira Goda , Kazuhiro Shimizu , Yuji Takeuchi , Riichiro Shirota , Seiichi Aritome
IPC分类号： H01L2710
CPC分类号： H01L21/76877 , H01L21/76885 , H01L23/5226 , H01L27/10885 , H01L27/10888 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： In a bit line contact section, a contact hole is formed through a silicon oxide film, and a contact plug made of a polysilicon film doped with impurities is buried in the contact hole. The silicon oxide film is formed with a wiring groove overlapping the contact hole. A bit line made of a metal film is buried in the wiring groove. The contact plug extends through the bit line, and has its upper surface substantially coplanar with an upper surface of the bit line. The contact plug is in contact with the bit line only on its side surfaces.
摘要翻译：在位线接触部分中，通过氧化硅膜形成接触孔，并且在接触孔中埋设由掺杂杂质的多晶硅膜制成的接触塞。氧化硅膜形成有与接触孔重叠的布线槽。由金属膜制成的位线埋在布线槽中。接触插塞延伸穿过位线，并且其上表面与位线的上表面基本上共面。接触插塞仅在其侧面与位线接触。

16. 发明申请

US20110186921A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING ELEMENT ISOLATING REGION OF TRENCH TYPE 有权
标题翻译：具有元件分离区域的非挥发性半导体存储器件
公开(公告)号：US20110186921A1
公开(公告)日：2011-08-04
申请号：US13085884
申请日：2011-04-13
申请人： Michiharu MATSUI , Seiichi Mori , Riichiro Shirota , Yuji Takeuchi , Takeshi Kamigaichi
发明人： Michiharu MATSUI , Seiichi Mori , Riichiro Shirota , Yuji Takeuchi , Takeshi Kamigaichi
IPC分类号： H01L29/788
CPC分类号： H01L27/11526 , H01L21/76229 , H01L27/105 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11529 , H01L27/11531 , H01L27/11543 , H01L29/7887
摘要： Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.
摘要翻译：公开是选择性栅极区域的半导体器件，包括半导体层，形成在半导体层上的第一绝缘膜，形成在第一绝缘层上的第一电极层，元件隔离区域，其包括形成为延伸穿过的元件隔离绝缘膜所述第一电极层和所述第一绝缘膜到达所述半导体层的内部区域，所述元件隔离区域隔离元件区域并且与所述第一电极层自对准;第二绝缘膜，形成在所述第一电极层上，元件隔离区域，暴露在第二绝缘膜中形成的第一电极层的表面的开口部分和形成在第二绝缘膜和第一电极层的暴露表面上的第二电极层，第二电极层是电子经由开口部与第一电极层连接。

17. 发明授权

US07893477B2 Nonvolatile semiconductor memory 有权
公开(公告)号：US07893477B2
公开(公告)日：2011-02-22
申请号：US11829320
申请日：2007-07-27
申请人： Hiroshi Watanabe , Hiroshi Nakamura , Kazuhiro Shimizu , Seiichi Aritome , Toshitake Yaegashi , Yuji Takeuchi , Kenichi Imamiya , Ken Takeuchi , Hideko Oodaira
发明人： Hiroshi Watanabe , Hiroshi Nakamura , Kazuhiro Shimizu , Seiichi Aritome , Toshitake Yaegashi , Yuji Takeuchi , Kenichi Imamiya , Ken Takeuchi , Hideko Oodaira
IPC分类号： H01L27/108 , H01L29/73
CPC分类号： H01L27/11521 , G11C16/0483 , G11C16/10 , H01L27/105 , H01L27/115 , H01L27/11524 , H01L27/11526 , H01L27/11529
摘要： A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has contact areas. The second-level conductive layer has its portions removed that are located above the contact areas. Two adjacent select gate electrodes that are adjacent to each other in the column direction are arranged such that the contact areas of one select gate electrode are not opposed to the contact areas of the other select gate electrode. One select gate electrode has its first- and second-level conductive layers removed in their portions that are opposed to the contact areas of the other select gate electrode.

18. 发明申请

US20110010402A1 DATA-DRIVEN DATABASE PROCESSOR 有权
标题翻译：数据驱动数据库处理器
公开(公告)号：US20110010402A1
公开(公告)日：2011-01-13
申请号：US12812016
申请日：2008-12-24
申请人： Ken Takeuchi , Yuji Takeuchi , Takahiro Yodo
发明人： Ken Takeuchi , Yuji Takeuchi , Takahiro Yodo
IPC分类号： G06F7/00
CPC分类号： G06F17/3051 , G06F17/30371 , G06F17/30595
摘要： Provided is a technique for a data-driven database which frees a user from having to be conscious of a sequence in which instructions of a program for accessing a database are described, an interrelation of data items, and the like, and from having to describe redundant instructions. A data-driven database processor includes: schema definition storage means 2 for storing a schema definition of a database 24; derived definition storage means 3 for storing a derived definition describing a cause-and-effect relationship that exists when a value of a given data item is derived from a value of another data item; derived definition processing means 26 for generating a trigger program 27 that makes a chain of changes to values of data items based on the cause-and-effect relationship described in the derived definition; and a database management system 23 for executing the trigger program 27 when a change is made to the other data item that affects the value of the given data item.
摘要翻译：提供了一种用于数据驱动数据库的技术，其释放用户不必意识到描述用于访问数据库的程序的指令，数据项的相关性等的序列，并且不必描述冗余指令。数据驱动数据库处理器包括：用于存储数据库24的模式定义的模式定义存储装置2; 派生定义存储装置3，用于存储描述当从另一数据项的值导出给定数据项的值时存在的因果关系的派生定义; 导出定义处理装置26，用于基于导出的定义中描述的因果关系，产生触发程序27，触发程序27使数据项的值变化链; 以及数据库管理系统23，用于当对影响给定数据项的值的其他数据项进行改变时，执行触发程序27。

19. 发明授权

US07595522B2 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US07595522B2
公开(公告)日：2009-09-29
申请号：US11565822
申请日：2006-12-01
申请人： Yuji Takeuchi
发明人： Yuji Takeuchi
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L29/42336 , H01L27/115 , H01L27/11521
摘要： According to the invention, there is provided a nonvolatile semiconductor memory having: a floating gate electrode formed on a gate insulating film on an element region isolated by an element isolation region on a semiconductor substrate; an inter-gate insulating film formed to cover a portion from an upper surface to a middle of a side surface of the floating gate electrode; and a control gate electrode formed on the floating gate electrode via the inter-gate insulating film, wherein a portion from the upper surface of the floating gate electrode to at least a middle of the portion of the side surface which is covered with the inter-gate insulating film has a tapered shape largely inclined to a direction perpendicular to a surface of the semiconductor substrate, compared to the other portion of the side surface.
摘要翻译：根据本发明，提供了一种非易失性半导体存储器，其具有：形成在由半导体衬底上的元件隔离区域隔离的元件区域上的栅极绝缘膜上的浮栅电极; 形成为覆盖从所述浮栅电极的侧面的上表面到中间的部分的栅极间绝缘膜; 以及通过所述栅极间绝缘膜形成在所述浮栅上的控制栅电极，其中，从所述浮栅电极的上表面到所述侧表面的所述部分的至少中间的部分，与侧面的其他部分相比，栅极绝缘膜具有大致倾斜于垂直于半导体衬底的表面的方向的锥形形状。

20. 发明授权

US07504294B2 Method of manufacturing an electrically erasable programmable read-only memory (EEPROM) 有权
标题翻译：制造电可擦除可编程只读存储器（EEPROM）的方法
公开(公告)号：US07504294B2
公开(公告)日：2009-03-17
申请号：US10881180
申请日：2004-07-01
申请人： Kikuko Sugimae , Hiroyuki Kutsukake , Masayuki Ichige , Michiharu Matsui , Yuji Takeuchi , Riichiro Shirota
发明人： Kikuko Sugimae , Hiroyuki Kutsukake , Masayuki Ichige , Michiharu Matsui , Yuji Takeuchi , Riichiro Shirota
IPC分类号： H01L21/8238
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11529
摘要： A semiconductor device comprises a memory cell array portion and peripheral circuit portion, wherein a first insulation film including elements as main components other than nitrogen fills between the memory cell gate electrodes of the memory cell array portion, the first insulation film is formed as a liner on a sidewall of a peripheral gate electrode of the peripheral circuit portion simultaneously with the memory cell portion, and a second insulation film including nitrogen as the main component is formed on the sidewall of the peripheral gate electrode via the first insulation film, thus enabling not only the formation of the memory cell portion having high reliability, but also the formation of a peripheral circuit with good efficiency, simultaneously, and avoiding gate offset of a peripheral gate.
摘要翻译：半导体器件包括存储单元阵列部分和外围电路部分，其中包括作为除氮之外的主要成分的元素的第一绝缘膜填充在存储单元阵列部分的存储单元栅电极之间，第一绝缘膜形成为衬垫在周边电路部分的外围栅电极的侧壁上与存储单元部分同时，并且通过第一绝缘膜在外围栅电极的侧壁上形成包括氮作为主要成分的第二绝缘膜，从而不能仅形成具有高可靠性的存储单元部分，而且形成具有良好效率的周边电路，同时避免了外围栅极的栅极偏移。

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