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1. 发明授权

US07245534B2 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US07245534B2
公开(公告)日：2007-07-17
申请号：US11135415
申请日：2005-05-24
申请人： Akira Goda , Mitsuhiro Noguchi , Minori Kajimoto , Yuji Takeuchi
发明人： Akira Goda , Mitsuhiro Noguchi , Minori Kajimoto , Yuji Takeuchi
IPC分类号： G11C11/34
CPC分类号： G11C8/10 , G11C16/0483 , G11C16/08 , G11C16/10 , H01L27/115 , H01L27/11521
摘要： A nonvolatile semiconductor memory includes: a memory cell array constituted by word lines, bit lines, and electrically erasable/rewritable memory cell transistors, which have respective tunnel insulating films and are arranged at the intersections of the word lines and the bit lines; and a word line transfer transistor, which is separated by an element isolation region, has a source diffusion layer, a channel region, a gate insulating film on the channel region, and a drain diffusion layer, and is connected to a word line and a gate electrode formed on the gate insulating film via a word line contact plug formed in the drain diffusion layer. The channel width of the word line transfer transistor is at least six times width of the word line contact plug, and the distance in a second direction between the word line contact plug and corresponding element isolation region is greater than distance in a first direction between the word line contact plug and corresponding element isolation region where, the first direction denotes a direction from the source diffusion layer towards the drain diffusion layer, and the second direction denotes a direction perpendicular to the first direction.
摘要翻译：非易失性半导体存储器包括：由字线，位线和电可擦除/可重写存储单元晶体管构成的存储单元阵列，其具有相应的隧道绝缘膜并且布置在字线和位线的交点处; 并且由元件隔离区隔开的字线传输晶体管在沟道区上具有源极扩散层，沟道区，栅极绝缘膜和漏极扩散层，并且连接到字线和栅极通过形成在漏极扩散层中的字线接触插塞形成在栅极绝缘膜上。字线传输晶体管的沟道宽度是字线接触插塞的至少六倍宽度，并且字线接触插塞和对应元件隔离区域之间的第二方向上的距离大于第二方向上的距离字线接触插塞和对应元件隔离区域，其中第一方向表示从源极扩散层朝向漏极扩散层的方向，第二方向表示与第一方向垂直的方向。

2. 发明授权

US06969660B2 Method of manufacturing a semiconductor device with trench isolation between two regions having different gate insulating films 失效
标题翻译：在具有不同栅极绝缘膜的两个区域之间制造具有沟槽隔离的半导体器件的方法
公开(公告)号：US06969660B2
公开(公告)日：2005-11-29
申请号：US11007462
申请日：2004-12-09
申请人： Akira Goda , Mitsuhiro Noguchi , Yuji Takeuchi , Michiharu Matsui , Hiroaki Hazama
发明人： Akira Goda , Mitsuhiro Noguchi , Yuji Takeuchi , Michiharu Matsui , Hiroaki Hazama
IPC分类号： H01L27/115 , H01L21/762 , H01L21/8234 , H01L21/8246 , H01L27/105 , H01L21/336
CPC分类号： H01L27/11568 , H01L21/76232 , H01L21/823462 , H01L21/823481 , H01L27/105 , H01L27/11573
摘要： The major surface of a semiconductor substrate of a semiconductor device includes first and second regions and a boundary area therebetween. A first gate insulating film and a first gate electrode are formed in the first region. A second gate insulating film different from the first gate insulating film and a second gate electrode are formed in the second region. A device isolation region is formed in the boundary area. This device isolation region includes a trench formed in the major surface, and an insulating layer having a portion buried in the trench and a portion projecting upward from the major surface. The bottom of the trench has depths different with portions.
摘要翻译：半导体器件的半导体衬底的主表面包括第一和第二区域以及它们之间的边界区域。第一栅极绝缘膜和第一栅电极形成在第一区域中。在第二区域中形成与第一栅极绝缘膜和第二栅极电极不同的第二栅极绝缘膜。在边界区域形成器件隔离区。该器件隔离区域包括形成在主表面中的沟槽，以及绝缘层，其具有埋在沟槽中的部分和从主表面向上突出的部分。沟槽的底部具有与部分不同的深度。

3. 发明授权

US06943453B2 Superconductor device and method of manufacturing the same 失效
公开(公告)号：US06943453B2
公开(公告)日：2005-09-13
申请号：US10318257
申请日：2002-12-13
申请人： Akira Goda , Mitsuhiro Noguchi , Yuji Takeuchi , Hiroaki Hazama
发明人： Akira Goda , Mitsuhiro Noguchi , Yuji Takeuchi , Hiroaki Hazama
IPC分类号： H01L21/28 , H01L21/768 , H01L21/8246 , H01L21/8247 , H01L23/485 , H01L23/522 , H01L27/105 , H01L27/115 , H01L29/423 , H01L29/43 , H01L29/49 , H01L29/788 , H01L29/792 , H01L29/40
CPC分类号： H01L27/11568 , H01L21/76838 , H01L23/485 , H01L23/522 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11531 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device comprising element regions formed in a semiconductor substrate, conductor plugs embedded in an interlayer insulation film, and wiring layers connected to the plugs, wherein the plugs are arranged on a straight line orthogonal to a longitudinal direction of the wiring layer in the same pitch as the wiring layers such that the straight line and upper surfaces of the plugs are superposed each other, and when the plugs are viewed in a cross section parallel to a main surface of the substrate and a distance which is between those two edge points of each of the plugs where a split line which passes through a center of each of the plugs passes is defined as a contact diameter, the contact diameter has three or more maximum values and three or more minimum values while the split line is rotated in the cross section by 360 degrees.

4. 发明申请

US20050133874A1 Method of manufactoring a semiconductor device with trench isolation between two regions having different gate insulating films 失效
标题翻译：在具有不同栅极绝缘膜的两个区域之间制造具有沟槽隔离的半导体器件的方法
公开(公告)号：US20050133874A1
公开(公告)日：2005-06-23
申请号：US11007462
申请日：2004-12-09
申请人： Akira Goda , Mitsuhiro Noguchi , Yuji Takeuchi , Michiharu Matsui , Hiroaki Hazama
发明人： Akira Goda , Mitsuhiro Noguchi , Yuji Takeuchi , Michiharu Matsui , Hiroaki Hazama
IPC分类号： H01L27/115 , H01L21/762 , H01L21/8234 , H01L21/8246 , H01L27/105 , H01L29/76
CPC分类号： H01L27/11568 , H01L21/76232 , H01L21/823462 , H01L21/823481 , H01L27/105 , H01L27/11573
摘要： The major surface of a semiconductor substrate of a semiconductor device includes first and second regions and a boundary area therebetween. A first gate insulating film and a first gate electrode are formed in the first region. A second gate insulating film different from the first gate insulating film and a second gate electrode are formed in the second region. A device isolation region is formed in the boundary area. This device isolation region includes a trench formed in the major surface, and an insulating layer having a portion buried in the trench and a portion projecting upward from the major surface. The bottom of the trench has depths different with portions.
摘要翻译：半导体器件的半导体衬底的主表面包括第一和第二区域以及它们之间的边界区域。第一栅极绝缘膜和第一栅电极形成在第一区域中。在第二区域中形成与第一栅极绝缘膜和第二栅极电极不同的第二栅极绝缘膜。在边界区域形成器件隔离区。该器件隔离区域包括形成在主表面中的沟槽，以及绝缘层，其具有埋在沟槽中的部分和从主表面向上突出的部分。沟槽的底部具有与部分不同的深度。

5. 发明授权

US06958938B2 Data writing method for semiconductor memory device and semiconductor memory device 有权
标题翻译：半导体存储器件和半导体存储器件的数据写入方法
公开(公告)号：US06958938B2
公开(公告)日：2005-10-25
申请号：US11007461
申请日：2004-12-09
申请人： Mitsuhiro Noguchi , Akira Goda , Yuji Takeuchi
发明人： Mitsuhiro Noguchi , Akira Goda , Yuji Takeuchi
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/12 , G11C16/34 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/3445 , G11C16/0416 , G11C16/0483 , G11C16/12 , G11C16/3468
摘要： A data writing method for a semiconductor memory device includes writing data into the first memory cell, rewriting the data into the first memory cell when an insufficiency of the data of the first memory cell is determined as a result of verifying the data of the first memory cell at one first reference threshold voltage, writing data into the second memory cell following writing the data into the first memory cell, and rewriting the data into the first memory cell following writing the data into the second memory cell when an insufficiency of the data of the first memory cell is determined as a result of verifying the data of the first memory cell at one second reference threshold voltage. The first reference threshold voltage is set to be different from the second reference threshold voltage.
摘要翻译：半导体存储器件的数据写入方法包括将数据写入第一存储单元，当确定第一存储单元的数据不足时，将数据重新写入第一存储器单元作为验证第一存储器的数据的结果在一个第一参考阈值电压下，将数据写入第一存储单元之后，将数据写入第二存储单元，并且当数据不足时将数据写入第二存储单元中作为第一存储单元的数据在一秒钟的参考阈值电压下进行验证的结果来确定第一存储单元。第一参考阈值电压被设置为不同于第二参考阈值电压。

6. 发明申请

US20050157558A1 DATA WRITING METHOD FOR SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：用于半导体存储器件和半导体存储器件的数据写入方法
公开(公告)号：US20050157558A1
公开(公告)日：2005-07-21
申请号：US11007461
申请日：2004-12-09
申请人： Mitsuhiro Noguchi , Akira Goda , Yuji Takeuchi
发明人： Mitsuhiro Noguchi , Akira Goda , Yuji Takeuchi
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/12 , G11C16/34 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/3445 , G11C16/0416 , G11C16/0483 , G11C16/12 , G11C16/3468
摘要： A data writing method for a semiconductor memory device includes writing data into the first memory cell, rewriting the data into the first memory cell when an insufficiency of the data of the first memory cell is determined as a result of verifying the data of the first memory cell at one first reference threshold voltage, writing data into the second memory cell following writing the data into the first memory cell, and rewriting the data into the first memory cell following writing the data into the second memory cell when an insufficiency of the data of the first memory cell is determined as a result of verifying the data of the first memory cell at one second reference threshold voltage. The first reference threshold voltage is set to be different from the second reference threshold voltage.
摘要翻译：半导体存储器件的数据写入方法包括将数据写入第一存储单元，当确定第一存储单元的数据不足时，将数据重新写入第一存储器单元作为验证第一存储器的数据的结果在一个第一参考阈值电压下，将数据写入第一存储单元之后，将数据写入第二存储单元，并且当数据不足时将数据写入第二存储单元中作为第一存储单元的数据在一秒钟的参考阈值电压下进行验证的结果来确定第一存储单元。第一参考阈值电压被设置为不同于第二参考阈值电压。

7. 发明授权

US06870773B2 Data writing method for semiconductor memory device and semiconductor memory device 失效
标题翻译：半导体存储器件和半导体存储器件的数据写入方法
公开(公告)号：US06870773B2
公开(公告)日：2005-03-22
申请号：US10796180
申请日：2004-03-10
申请人： Mitsuhiro Noguchi , Akira Goda , Yuji Takeuchi
发明人： Mitsuhiro Noguchi , Akira Goda , Yuji Takeuchi
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06 , G11C16/10 , G11C16/12 , G11C16/34 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/3445 , G11C16/0416 , G11C16/0483 , G11C16/12 , G11C16/3468
摘要： A semiconductor memory device includes a first memory cell block capable of rewriting data and having at least one first memory cell, and a second memory cell block capable of rewriting data and having at least one second memory cell adjoining the first memory cell. A data writing method for the semiconductor memory device includes writing data into the first memory cell, writing data into the second memory cell following writing the data into the first memory cell, verifying the data of the first memory cell after writing the data into the second memory cell, and rewriting the data into the first memory cell when insufficiency of the data of the first memory cell as a result of verifying the data of the first memory cell.
摘要翻译：半导体存储器件包括能够重写数据并具有至少一个第一存储单元的第一存储单元块和能够重写数据并具有与第一存储单元相邻的至少一个第二存储单元的第二存储单元块。一种用于半导体存储器件的数据写入方法，包括将数据写入第一存储单元，将数据写入第一存储单元之后将数据写入第二存储单元，在将数据写入第二存储单元之后，验证第一存储单元的数据并且当由于验证第一存储单元的数据而使第一存储器单元的数据不足时将数据重新写入第一存储器单元。

8. 发明授权

US07026241B2 Superconductor device and method of manufacturing the same 失效
公开(公告)号：US07026241B2
公开(公告)日：2006-04-11
申请号：US10943250
申请日：2004-09-17
申请人： Akira Goda , Mitsuhiro Noguchi , Yuji Takeuchi , Hiroaki Hazama
发明人： Akira Goda , Mitsuhiro Noguchi , Yuji Takeuchi , Hiroaki Hazama
IPC分类号： H01L21/4763
CPC分类号： H01L27/11568 , H01L21/76838 , H01L23/485 , H01L23/522 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11531 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device comprising element regions formed in a semiconductor substrate, conductor plugs embedded in an interlayer insulation film, and wiring layers connected to the plugs, wherein the plugs are arranged on a straight line orthogonal to a longitudinal direction of the wiring layer in the same pitch as the wiring layers such that the straight line and upper surfaces of the plugs are superposed each other, and when the plugs are viewed in a cross section parallel to a main surface of the substrate and a distance which is between those two edge points of each of the plugs where a split line which passes through a center of each of the plugs passes is defined as a contact diameter, the contact diameter has three or more maximum values and three or more minimum values while the split line is rotated in the cross section by 360 degrees.

9. 发明申请

US20050037612A1 Superconductor device and method of manufacturing the same 失效
标题翻译：超导体装置及其制造方法
公开(公告)号：US20050037612A1
公开(公告)日：2005-02-17
申请号：US10943250
申请日：2004-09-17
申请人： Akira Goda , Mitsuhiro Noguchi , Yuji Takeuchi , Hiroaki Hazama
发明人： Akira Goda , Mitsuhiro Noguchi , Yuji Takeuchi , Hiroaki Hazama
IPC分类号： H01L21/28 , H01L21/768 , H01L21/8246 , H01L21/8247 , H01L23/485 , H01L23/522 , H01L27/105 , H01L27/115 , H01L29/423 , H01L29/43 , H01L29/49 , H01L29/788 , H01L29/792 , H01L21/4763 , H01L21/44
CPC分类号： H01L27/11568 , H01L21/76838 , H01L23/485 , H01L23/522 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11531 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device comprising element regions formed in a semiconductor substrate, conductor plugs embedded in an interlayer insulation film, and wiring layers connected to the plugs, wherein the plugs are arranged on a straight line orthogonal to a longitudinal direction of the wiring layer in the same pitch as the wiring layers such that the straight line and upper surfaces of the plugs are superposed each other, and when the plugs are viewed in a cross section parallel to a main surface of the substrate and a distance which is between those two edge points of each of the plugs where a split line which passes through a center of each of the plugs passes is defined as a contact diameter, the contact diameter has three or more maximum values and three or more minimum values while the split line is rotated in the cross section by 360 degrees.
摘要翻译：一种半导体器件，包括形成在半导体衬底中的元件区域，嵌入在层间绝缘膜中的导体插塞和连接到插头的布线层，其中插头布置在与其中的布线层的纵向正交的直线上作为布线层的间距，使得插塞的直线和上表面彼此重叠，并且当在与基板的主表面平行的横截面中观察插塞时，并且在两个边缘点之间的距离通过每个塞子的中心的分割线通过的每个插头被定义为接触直径，接触直径具有三个或更多个最大值和三个或更多个最小值，同时分叉线在十字形中旋转截面360度。

10. 发明申请

US20050265109A1 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US20050265109A1
公开(公告)日：2005-12-01
申请号：US11135415
申请日：2005-05-24
申请人： Akira Goda , Mitsuhiro Noguchi , Minori Kajimoto , Yuji Takeuchi
发明人： Akira Goda , Mitsuhiro Noguchi , Minori Kajimoto , Yuji Takeuchi
IPC分类号： H01L27/10 , G11C8/00 , G11C8/10 , G11C16/04 , G11C16/08 , G11C16/10 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C8/10 , G11C16/0483 , G11C16/08 , G11C16/10 , H01L27/115 , H01L27/11521
摘要： A nonvolatile semiconductor memory includes: a memory cell array constituted by word lines, bit lines, and electrically erasable/rewritable memory cell transistors, which have respective tunnel insulating films and are arranged at the intersections of the word lines and the bit lines; and a word line transfer transistor, which is separated by an element isolation region, has a source diffusion layer, a channel region, a gate insulating film on the channel region, and a drain diffusion layer, and is connected to a word line and a gate electrode formed on the gate insulating film via a word line contact plug formed in the drain diffusion layer. The channel width of the word line transfer transistor is at least six times width of the word line contact plug, and the distance in a second direction between the word line contact plug and corresponding element isolation region is greater than distance in a first direction between the word line contact plug and corresponding element isolation region where, the first direction denotes a direction from the source diffusion layer towards the drain diffusion layer, and the second direction denotes a direction perpendicular to the first direction.
摘要翻译：非易失性半导体存储器包括：由字线，位线和电可擦除/可重写存储单元晶体管构成的存储单元阵列，其具有相应的隧道绝缘膜并且布置在字线和位线的交点处; 并且由元件隔离区隔开的字线传输晶体管在沟道区上具有源极扩散层，沟道区，栅极绝缘膜和漏极扩散层，并且连接到字线和栅极通过形成在漏极扩散层中的字线接触插塞形成在栅极绝缘膜上。字线传输晶体管的沟道宽度是字线接触插塞的至少六倍宽度，并且字线接触插塞和对应元件隔离区域之间的第二方向上的距离大于第二方向上的距离字线接触插塞和对应元件隔离区域，其中第一方向表示从源极扩散层朝向漏极扩散层的方向，第二方向表示与第一方向垂直的方向。

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