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11. 发明申请

US20080256551A1 System and Method For Storing State Information 审中-公开
标题翻译：用于存储状态信息的系统和方法
公开(公告)号：US20080256551A1
公开(公告)日：2008-10-16
申请号：US12067587
申请日：2005-09-21
申请人： Michael Priel , Dan Kuzmin , Leonid Smolyansky
发明人： Michael Priel , Dan Kuzmin , Leonid Smolyansky
IPC分类号： G06F9/46
CPC分类号： G06F9/462
摘要： A method for storing state information, the method includes storing, at a first circuit, state information representative of a state of a second circuit while the second circuit enters a low power mode; characterized by receiving an indication that a task switching from a first task to a second task should occur; storing a state information representative of a state of the second circuit, at the first circuit; receiving an indication that the first task should be resumed; and writing the stored state information from the first circuit to the second circuit. A system includes a first circuit and a second circuit, whereas the first circuit is connected to the second circuit and is adapted to store state information representative of a state of a second circuit; characterized by including a controller adapted to control a storage of the state information if at least a portion of the second circuit is powered down or if the second circuit is associated with a task switching operation.
摘要翻译：一种用于存储状态信息的方法，所述方法包括在第一电路处存储表示第二电路的状态的状态信息，同时第二电路进入低功率模式; 其特征在于接收从第一任务切换到第二任务的任务应发生的指示; 在所述第一电路处存储表示所述第二电路的状态的状态信息; 收到第一个任务应恢复的指示; 以及将所存储的状态信息从第一电路写入第二电路。一种系统包括第一电路和第二电路，而第一电路连接到第二电路，并适于存储表示第二电路的状态的状态信息; 其特征在于包括控制器，其适于在所述第二电路的至少一部分断电或者所述第二电路与任务切换操作相关联时控制所述状态信息的存储。

12. 发明授权

US09618988B2 Method and apparatus for managing a thermal budget of at least a part of a processing system 有权
公开(公告)号：US09618988B2
公开(公告)日：2017-04-11
申请号：US14410146
申请日：2012-07-03
申请人： Anton Rozen , Roy Drucker , Leonid Smolyansky
发明人： Anton Rozen , Roy Drucker , Leonid Smolyansky
IPC分类号： G06F1/32 , G06F1/28 , G06F9/46
CPC分类号： G06F1/28 , G06F1/3206 , G06F9/466
摘要： A method of managing a thermal budget, for at least a part of a processing system, is described. The method comprises, upon detection of a use case event, determining a thermal budget violation time window for a current use case scenario of the at least part of the processing system, and managing the thermal budget for the at least part of the processing system based at least partly on the determined thermal budget violation time window.

13. 发明申请

US20140325183A1 INTEGRATED CIRCUIT DEVICE, ASYMMETRIC MULTI-CORE PROCESSING MODULE, ELECTRONIC DEVICE AND METHOD OF MANAGING EXECUTION OF COMPUTER PROGRAM CODE THEREFOR 审中-公开
标题翻译：集成电路设备，不对称多核处理模块，电子设备及其计算机程序代码的执行方法
公开(公告)号：US20140325183A1
公开(公告)日：2014-10-30
申请号：US14358053
申请日：2011-11-28
申请人： Anton Rozen , Dan Kuzmin , Michael Priel , Leonid Smolyansky
发明人： Anton Rozen , Dan Kuzmin , Michael Priel , Leonid Smolyansky
IPC分类号： G06F15/76
CPC分类号： G06F15/76 , G06F9/5083 , G06F9/5094 , G06F2015/765 , Y02D10/22
摘要： An asymmetric multi-core processing module is described. The asymmetric multi-core processing module comprises at least one processing core of a first type, at least one processing core of at least one further type, and at least one core identifier configuration component. The at least one core identifier configuration component is arranged to enable dynamic configuration of a value of a core identifier of at least one of the processing cores of the first and at least one further types.
摘要翻译：描述了一种非对称多核处理模块。非对称多核处理模块包括至少一个第一类型的处理核心，至少一个另外类型的至少一个处理核心和至少一个核心标识符配置组件。至少一个核心标识符配置组件被布置成使得能够动态地配置第一和至少一个其它类型的至少一个处理核心的核心标识符的值。

14. 发明申请

US20130238912A1 METHOD AND APPARATUS FOR MANAGING POWER IN A MULTI-CORE PROCESSOR 有权
标题翻译：用于在多核处理器中管理功率的方法和装置
公开(公告)号：US20130238912A1
公开(公告)日：2013-09-12
申请号：US13989280
申请日：2010-11-25
申请人： Michael Priel , Anton Rozen , Leonid Smolyansky
发明人： Michael Priel , Anton Rozen , Leonid Smolyansky
IPC分类号： G06F1/26
CPC分类号： G06F1/26 , G06F1/324 , G06F1/3296 , G06F9/5094 , Y02D10/126 , Y02D10/172 , Y02D10/22
摘要： There is provided a method of managing power in a multi-core data processing system having two or more processing cores, comprising determining usage characteristics for the two or more processing cores within the multi-core processing unit, and dependent on the determined usage characteristics, adapting a frequency or voltage supplied to each of the two or more processing cores, and/or adapting enablement signals provided to each of the two or more processing cores. There is also provided an apparatus for carrying out the disclosed method.
摘要翻译：提供了一种在具有两个或多个处理核心的多核数据处理系统中管理电力的方法，包括确定多核处理单元内的两个或多个处理核心的使用特性，并且取决于确定的使用特性，适应提供给两个或多个处理核心中的每一个的频率或电压，和/或调整提供给两个或多个处理核心中的每一个的启用信号。还提供了一种用于实施所公开的方法的装置。

15. 发明授权

US08255723B2 Device having multiple instruction execution modules and a management method 有权
标题翻译：具有多个指令执行模块和管理方法的设备
公开(公告)号：US08255723B2
公开(公告)日：2012-08-28
申请号：US12509285
申请日：2009-07-24
申请人： Anton Rozen , Michael Priel , Leonid Smolyansky
发明人： Anton Rozen , Michael Priel , Leonid Smolyansky
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/3287 , G06F9/30189 , G06F9/3836 , G06F9/3869 , G06F9/3885 , Y02D10/171
摘要： A multiple instruction execution modules device that comprises a first instruction execution module and a second instruction execution module and a context switch controller; wherein the first instruction execution module is logically identical to the second instruction execution module but substantially differs from the second instruction execution module by at least one power consumption characteristic; wherein the context switch controller controls a context switch between the first instruction execution module and the second instruction execution module; wherein an instruction execution module that its context has been transferred is shut down.
摘要翻译：一种多指令执行模块装置，包括第一指令执行模块和第二指令执行模块以及上下文切换控制器; 其中所述第一指令执行模块在逻辑上与所述第二指令执行模块相同，但是与所述第二指令执行模块基本上不同于至少一个功耗特性; 其中所述上下文切换控制器控制所述第一指令执行模块和所述第二指令执行模块之间的上下文切换; 其中已经传送其上下文的指令执行模块被关闭。

16. 发明申请

US20100023653A1 SYSTEM AND METHOD FOR ARBITRATING BETWEEN MEMORY ACCESS REQUESTS 有权
标题翻译：在存储器访问请求之间进行仲裁的系统和方法
公开(公告)号：US20100023653A1
公开(公告)日：2010-01-28
申请号：US12179799
申请日：2008-07-25
申请人： Anton Rozen , Roman Mostinski , Michael Priel , Leonid Smolyansky
发明人： Anton Rozen , Roman Mostinski , Michael Priel , Leonid Smolyansky
IPC分类号： G06F12/00 , G06F13/28 , G06F1/08
CPC分类号： G06F13/1605 , Y02D10/14
摘要： A system having memory access capabilities, the system includes: (i) a dynamic voltage and frequency scaling (DVFS) controller, adapted to determine a level of a voltage supply supplied to a first memory access requester and a frequency of a clock signal provided to the first memory access requester and to generate a DVFS indication that is indicative of the determination; (ii) a hardware access request determination module, adapted to determine a priority of memory access request issued by the first memory access requester in response to the DVFS indication; and (iii) a direct memory access arbitrator, adapted to arbitrate between memory access requests issued by the first memory access requester and another memory access requester in response to priorities associated with the memory access requests.
摘要翻译：一种具有存储器访问能力的系统，该系统包括：（i）动态电压和频率缩放（DVFS）控制器，适于确定提供给第一存储器访问请求者的电压电平的电平和提供给所述第一存储器访问请求器并且生成指示所述确定的DVFS指示; （ii）硬件访问请求确定模块，用于响应于所述DVFS指示确定由所述第一存储器访问请求者发出的存储器访问请求的优先级; 以及（iii）直接存储器访问仲裁器，适于响应于与所述存储器访问请求相关联的优先级，在由所述第一存储器访问请求者发出的存储器访问请求与另一存储器访问请求者之间进行仲裁。

17. 发明授权

US09141178B2 Device and method for selective reduced power mode in volatile memory units 有权
标题翻译：易失性存储单元中选择性降低功耗模式的装置和方法
公开(公告)号：US09141178B2
公开(公告)日：2015-09-22
申请号：US13634999
申请日：2010-06-11
申请人： Michael Priel , Anton Rozen , Leonid Smolyansky
发明人： Michael Priel , Anton Rozen , Leonid Smolyansky
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32 , G06F11/00 , G01R31/28 , G01R31/3185 , G06F11/14
CPC分类号： G06F1/3275 , G01R31/318536 , G01R31/318558 , G06F1/3203 , G06F1/3287 , G06F11/1402 , Y02D10/14 , Y02D10/171
摘要： An information processing device comprises a first memory, a second memory, data transfer circuitry, power gating circuitry, and a controller. The first memory comprises at least two volatile memory units. The controller receives or generates a request for setting the information processing device into a reduced power mode; in response to the request, it selects specific memory units among the memory units; controls the data transfer circuitry to transfer data from the selected memory units to the second memory; and controls the power gating circuitry to power down the selected memory units.
摘要翻译：信息处理设备包括第一存储器，第二存储器，数据传输电路，电源门控电路和控制器。第一存储器包括至少两个易失性存储器单元。控制器接收或产生将信息处理设备设置为降低功率模式的请求; 响应于该请求，它选择存储单元中的特定存储单元; 控制数据传输电路将数据从所选存储器单元传送到第二存储器; 并控制电源门控电路使所选存储单元断电。

18. 发明申请

US20120226833A1 INTEGRATED CIRCUIT AND METHOD FOR REDUCING VIOLATIONS OF A TIMING COSTRAINT 有权
标题翻译：集成电路和减少时序成本的冲突的方法
公开(公告)号：US20120226833A1
公开(公告)日：2012-09-06
申请号：US13504737
申请日：2009-11-26
申请人： Roman Mostinski , Lavi Koch , Leonid Smolyansky
发明人： Roman Mostinski , Lavi Koch , Leonid Smolyansky
IPC分类号： G06F5/12
CPC分类号： G06F13/1673 , G06F13/1605
摘要： An integrated circuit and a method for reducing violations of a timing constraint. The integrated circuit comprises a shared resource for providing data and a buffer for storing data. A buffer level monitor is coupled to the buffer, for monitoring a monitored level of data in the buffer. A retrieving circuit is coupled to the buffer, for retrieving the data from the buffer, according to a timing constraint. A filling circuit is coupled to the buffer for writing the data to the buffer and coupled to the shared resource for receiving the data from the shared resource when the filling circuit has access to the shared resource. An access-requesting circuit is coupled to the shared resource for receiving the data from the shared resource when the access-requesting circuit has access to the shared resource. An arbiter is coupled to the shared resource, the filling circuit, and the access-requesting circuit, for receiving access requests from the filling circuit and from the access-requesting circuit, and for granting to a selected one thereof access to the shared resource. A controller is coupled to the buffer level monitor and to the access-requesting circuit, for causing the access-requesting circuit to reduce a rate of access requests sent to the arbiter when a condition indicating an anticipated violation of the timing constraint is fulfilled, the condition at least involving the monitored level of data in the buffer.
摘要翻译：一种用于减少违反定时约束的集成电路和方法。集成电路包括用于提供数据的共享资源和用于存储数据的缓冲器。缓冲器级监视器耦合到缓冲器，用于监视缓冲器中监视的数据级别。检索电路耦合到缓冲器，用于根据时序约束从缓冲器检索数据。填充电路耦合到缓冲器，用于将数据写入缓冲器并耦合到共享资源，用于当填充电路访问共享资源时从共享资源接收数据。访问请求电路耦合到共享资源，用于当访问请求电路访问共享资源时从共享资源接收数据。仲裁器耦合到共享资源，填充电路和访问请求电路，用于从填充电路和访问请求电路接收访问请求，并且向所选共享资源授予对共享资源的访问权限。控制器耦合到缓冲器级监视器和访问请求电路，用于使得访问请求电路当指示预期违反时序约束的条件得到满足时，降低发送给仲裁器的访问请求的速率，条件至少涉及缓冲区中监视的数据级别。

19. 发明授权

US08135966B2 Method and device for power management 有权
标题翻译：电源管理方法和装置
公开(公告)号：US08135966B2
公开(公告)日：2012-03-13
申请号：US12304854
申请日：2006-06-22
申请人： Anton Rozen , Michael Priel , Leonid Smolyansky
发明人： Anton Rozen , Michael Priel , Leonid Smolyansky
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3215 , G06F1/3228 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A device and method for power management. The method includes receiving an indication about a load of a circuit, determining at least one long-term activation parameter in view of a circuit load pattern during at least one long period; determining at least one short-term activation parameter in response to an expected short period load change of the circuit; and providing least one clock signal and at least one supply voltage in response to the long-term activation parameter and in response to the short-term supply parameter.
摘要翻译：一种用于电源管理的设备和方法。该方法包括接收关于电路的负载的指示，在至少一个长时间段期间根据电路负载模式确定至少一个长期激活参数; 响应于所述电路的期望的短周期负载变化来确定至少一个短期激活参数; 以及响应于所述长期激活参数和响应于所述短期供应参数而提供至少一个时钟信号和至少一个电源电压。

20. 发明申请

US20110022869A1 DEVICE HAVING MULTIPLE INSTRUCTION EXECUTION MODULES AND A MANAGEMENT METHOD 有权
标题翻译：具有多个指令执行模块的设备和管理方法
公开(公告)号：US20110022869A1
公开(公告)日：2011-01-27
申请号：US12509285
申请日：2009-07-24
申请人： Anton Rozen , Michael Priel , Leonid Smolyansky
发明人： Anton Rozen , Michael Priel , Leonid Smolyansky
IPC分类号： G06F1/32 , G06F9/30
CPC分类号： G06F1/3203 , G06F1/3287 , G06F9/30189 , G06F9/3836 , G06F9/3869 , G06F9/3885 , Y02D10/171
摘要： A multiple instruction execution modules device that comprises a first instruction execution module and a second instruction execution module and a context switch controller; wherein the first instruction execution module is logically identical to the second instruction execution module but substantially differs from the second instruction execution module by at least one power consumption characteristic; wherein the context switch controller controls a context switch between the first instruction execution module and the second instruction execution module; wherein an instruction execution module that its context has been transferred is shut down.
摘要翻译：一种多指令执行模块装置，包括第一指令执行模块和第二指令执行模块以及上下文切换控制器; 其中所述第一指令执行模块在逻辑上与所述第二指令执行模块相同，但是与所述第二指令执行模块基本上不同于至少一个功耗特性; 其中所述上下文切换控制器控制所述第一指令执行模块和所述第二指令执行模块之间的上下文切换; 其中已经传送其上下文的指令执行模块被关闭。

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